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2d24a3a7 WD |
1 | /* |
2 | * include/configs/mx1ads.h | |
49822e23 | 3 | * |
2d24a3a7 WD |
4 | * (c) Copyright 2004 |
5 | * Techware Information Technology, Inc. | |
6 | * http://www.techware.com.tw/ | |
7 | * | |
8 | * Ming-Len Wu <minglen_wu@techware.com.tw> | |
9 | * | |
10 | * This is the Configuration setting for Motorola MX1ADS board | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of | |
15 | * the License, or (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
281e00a3 | 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
2d24a3a7 WD |
20 | * GNU General Public License for more details. |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
25 | * MA 02111-1307 USA | |
26 | */ | |
27 | ||
2d24a3a7 WD |
28 | #ifndef __CONFIG_H |
29 | #define __CONFIG_H | |
30 | ||
2d24a3a7 WD |
31 | /* |
32 | * High Level Configuration Options | |
33 | * (easy to change) | |
34 | */ | |
35 | #define CONFIG_ARM920T 1 /* This is an ARM920T Core */ | |
281e00a3 WD |
36 | #define CONFIG_IMX 1 /* It's a Motorola MC9328 SoC */ |
37 | #define CONFIG_MX1ADS 1 /* on a Motorola MX1ADS Board */ | |
38 | #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ | |
2d24a3a7 | 39 | |
281e00a3 WD |
40 | /* |
41 | * Select serial console configuration | |
42 | */ | |
d3e55d07 | 43 | #define CONFIG_IMX_SERIAL |
281e00a3 WD |
44 | #define CONFIG_IMX_SERIAL1 /* internal uart 1 */ |
45 | /* #define _CONFIG_UART2 */ /* internal uart 2 */ | |
46 | /* #define CONFIG_SILENT_CONSOLE */ /* use this to disable output */ | |
2d24a3a7 | 47 | |
281e00a3 | 48 | #define BOARD_LATE_INIT 1 |
2d24a3a7 | 49 | #define USE_920T_MMU 1 |
2d24a3a7 | 50 | |
49822e23 | 51 | #if 0 |
6d0f6bcf JCPV |
52 | #define CONFIG_SYS_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */ |
53 | #define CONFIG_SYS_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */ | |
54 | #define CONFIG_SYS_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */ | |
49822e23 | 55 | #endif |
2d24a3a7 WD |
56 | |
57 | /* | |
58 | * Size of malloc() pool | |
59 | */ | |
60 | ||
6d0f6bcf | 61 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) |
281e00a3 WD |
62 | |
63 | ||
6d0f6bcf | 64 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
2d24a3a7 WD |
65 | |
66 | /* | |
67 | * CS8900 Ethernet drivers | |
68 | */ | |
b1c0eaac BW |
69 | #define CONFIG_NET_MULTI |
70 | #define CONFIG_CS8900 /* we have a CS8900 on-board */ | |
71 | #define CONFIG_CS8900_BASE 0x15000300 | |
72 | #define CONFIG_CS8900_BUS16 /* the Linux driver does accesses as shorts */ | |
2d24a3a7 WD |
73 | |
74 | /* | |
75 | * select serial console configuration | |
76 | */ | |
77 | ||
281e00a3 | 78 | /* #define CONFIG_UART1 */ |
2d24a3a7 WD |
79 | /* #define CONFIG_UART2 1 */ |
80 | ||
81 | #define CONFIG_BAUDRATE 115200 | |
82 | ||
2d24a3a7 | 83 | |
7f5c0157 JL |
84 | /* |
85 | * BOOTP options | |
86 | */ | |
87 | #define CONFIG_BOOTP_BOOTFILESIZE | |
88 | #define CONFIG_BOOTP_BOOTPATH | |
89 | #define CONFIG_BOOTP_GATEWAY | |
90 | #define CONFIG_BOOTP_HOSTNAME | |
91 | ||
92 | ||
5dc11a51 JL |
93 | /* |
94 | * Command line configuration. | |
95 | */ | |
96 | #include <config_cmd_default.h> | |
97 | ||
98 | #define CONFIG_CMD_CACHE | |
99 | #define CONFIG_CMD_REGINFO | |
100 | #define CONFIG_CMD_ELF | |
2d24a3a7 | 101 | |
2d24a3a7 WD |
102 | |
103 | #define CONFIG_BOOTDELAY 3 | |
281e00a3 | 104 | #define CONFIG_BOOTARGS "root=/dev/msdk mem=48M" |
2d24a3a7 | 105 | #define CONFIG_BOOTFILE "mx1ads" |
281e00a3 | 106 | #define CONFIG_BOOTCOMMAND "tftp; bootm" |
2d24a3a7 | 107 | |
5dc11a51 | 108 | #if defined(CONFIG_CMD_KGDB) |
2d24a3a7 WD |
109 | #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ |
110 | /* what's this ? it's not used anywhere */ | |
111 | #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ | |
112 | #endif | |
113 | ||
114 | /* | |
115 | * Miscellaneous configurable options | |
116 | */ | |
49822e23 | 117 | |
6d0f6bcf JCPV |
118 | #define CONFIG_SYS_HUSH_PARSER 1 |
119 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
49822e23 | 120 | |
6d0f6bcf | 121 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
2d24a3a7 | 122 | |
6d0f6bcf JCPV |
123 | #ifdef CONFIG_SYS_HUSH_PARSER |
124 | #define CONFIG_SYS_PROMPT "MX1ADS$ " /* Monitor Command Prompt */ | |
2d24a3a7 | 125 | #else |
6d0f6bcf | 126 | #define CONFIG_SYS_PROMPT "MX1ADS=> " /* Monitor Command Prompt */ |
2d24a3a7 WD |
127 | #endif |
128 | ||
6d0f6bcf JCPV |
129 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
130 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
2d24a3a7 | 131 | /* Print Buffer Size */ |
6d0f6bcf JCPV |
132 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
133 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
2d24a3a7 | 134 | |
6d0f6bcf JCPV |
135 | #define CONFIG_SYS_MEMTEST_START 0x09000000 /* memtest works on */ |
136 | #define CONFIG_SYS_MEMTEST_END 0x0AF00000 /* 63 MB in DRAM */ | |
2d24a3a7 | 137 | |
6d0f6bcf JCPV |
138 | #define CONFIG_SYS_LOAD_ADDR 0x08800000 /* default load address */ |
139 | /*#define CONFIG_SYS_HZ 1000 */ | |
140 | #define CONFIG_SYS_HZ 3686400 | |
141 | #define CONFIG_SYS_CPUSPEED 0x141 | |
2d24a3a7 WD |
142 | |
143 | /* valid baudrates */ | |
6d0f6bcf | 144 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
2d24a3a7 WD |
145 | |
146 | /*----------------------------------------------------------------------- | |
147 | * Stack sizes | |
148 | * | |
149 | * The stack sizes are set up in start.S using the settings below | |
150 | */ | |
151 | #define CONFIG_STACKSIZE (128*1024) /* regular stack */ | |
152 | #ifdef CONFIG_USE_IRQ | |
153 | #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ | |
154 | #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ | |
155 | #endif | |
156 | ||
157 | /*----------------------------------------------------------------------- | |
158 | * Physical Memory Map | |
159 | */ | |
49822e23 | 160 | |
281e00a3 WD |
161 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */ |
162 | #define PHYS_SDRAM_1 0x08000000 /* SDRAM on CSD0 */ | |
163 | #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ | |
2d24a3a7 | 164 | |
6d0f6bcf JCPV |
165 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* 1 bank of SyncFlash */ |
166 | #define CONFIG_SYS_FLASH_BASE 0x0C000000 /* SyncFlash on CSD1 */ | |
281e00a3 | 167 | #define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */ |
2d24a3a7 WD |
168 | |
169 | /*----------------------------------------------------------------------- | |
170 | * FLASH and environment organization | |
171 | */ | |
172 | ||
2d24a3a7 WD |
173 | #define CONFIG_SYNCFLASH 1 |
174 | #define PHYS_FLASH_SIZE 0x01000000 | |
6d0f6bcf JCPV |
175 | #define CONFIG_SYS_MAX_FLASH_SECT (16) |
176 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x00ff8000) | |
49822e23 | 177 | |
5a1aceb0 | 178 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
179 | #define CONFIG_ENV_SIZE 0x04000 /* Total Size of Environment Sector */ |
180 | #define CONFIG_ENV_SECT_SIZE 0x100000 | |
281e00a3 WD |
181 | |
182 | /*----------------------------------------------------------------------- | |
183 | * Enable passing ATAGS | |
184 | */ | |
185 | ||
186 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ | |
187 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
188 | ||
189 | #define CONFIG_SYS_CLK_FREQ 16780000 | |
190 | #define CONFIG_SYSPLL_CLK_FREQ 16000000 | |
191 | ||
2d24a3a7 | 192 | #endif /* __CONFIG_H */ |