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281e00a3 WD |
1 | /* |
2 | * Copyright (C) 2004 Sascha Hauer, Pengutronix | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License as | |
6 | * published by the Free Software Foundation; either version 2 of | |
7 | * the License, or (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
17 | * MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #ifndef __CONFIG_H | |
21 | #define __CONFIG_H | |
22 | ||
23 | #define CONFIG_ARM920T 1 /* this is an ARM920T CPU */ | |
24 | #define CONFIG_IMX 1 /* in a Motorola MC9328MXL Chip */ | |
25 | #define CONFIG_MX1FS2 1 /* on a mx1fs2 board */ | |
26 | #undef CONFIG_USE_IRQ /* don't need use IRQ/FIQ */ | |
27 | ||
28 | /* | |
29 | * Select serial console configuration | |
30 | */ | |
31 | #undef _CONFIG_UART1 /* internal uart 1 */ | |
32 | #define _CONFIG_UART2 /* internal uart 2 */ | |
33 | #undef _CONFIG_UART3 /* internal uart 3 */ | |
34 | #undef _CONFIG_UART4 /* internal uart 4 */ | |
35 | #undef CONFIG_SILENT_CONSOLE /* use this to disable output */ | |
36 | ||
5dc11a51 | 37 | |
7f5c0157 JL |
38 | /* |
39 | * BOOTP options | |
40 | */ | |
41 | #define CONFIG_BOOTP_BOOTFILESIZE | |
42 | #define CONFIG_BOOTP_BOOTPATH | |
43 | #define CONFIG_BOOTP_GATEWAY | |
44 | #define CONFIG_BOOTP_HOSTNAME | |
45 | ||
46 | ||
281e00a3 | 47 | /* |
5dc11a51 | 48 | * Command line configuration. |
281e00a3 | 49 | */ |
5dc11a51 JL |
50 | #include <config_cmd_default.h> |
51 | ||
52 | #define CONFIG_CMD_JFFS2 | |
53 | ||
54 | #undef CONFIG_CMD_LOADS | |
55 | #undef CONFIG_CMD_CONSOLE | |
56 | #undef CONFIG_CMD_AUTOSCRIPT | |
57 | #undef CONFIG_CMD_NET | |
58 | #undef CONFIG_CMD_PING | |
59 | #undef CONFIG_CMD_DHCP | |
60 | ||
281e00a3 WD |
61 | |
62 | /* | |
63 | * Boot options. Setting delay to -1 stops autostart count down. | |
64 | */ | |
65 | #define CONFIG_BOOTDELAY 10 | |
66 | #define CONFIG_BOOTARGS "root=/dev/mtdblock4 console=ttySMX0,115200n8 rootfstype=jffs2" | |
67 | #define CONFIG_BOOTCOMMAND "bootm 10080000" | |
68 | #define CONFIG_SHOW_BOOT_PROGRESS | |
69 | ||
70 | /* | |
71 | * General options for u-boot. Modify to save memory foot print | |
72 | */ | |
6d0f6bcf JCPV |
73 | #define CONFIG_SYS_LONGHELP /* undef saves memory */ |
74 | #define CONFIG_SYS_PROMPT "mx1fs2> " /* prompt string */ | |
75 | #define CONFIG_SYS_CBSIZE 256 /* console I/O buffer */ | |
76 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* print buffer size */ | |
77 | #define CONFIG_SYS_MAXARGS 16 /* max command args */ | |
78 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot args buf size */ | |
281e00a3 | 79 | |
6d0f6bcf JCPV |
80 | #define CONFIG_SYS_MEMTEST_START 0x08100000 /* memtest test area */ |
81 | #define CONFIG_SYS_MEMTEST_END 0x08F00000 | |
281e00a3 | 82 | |
6d0f6bcf | 83 | #undef CONFIG_SYS_CLKS_IN_HZ /* use HZ for freq. display */ |
281e00a3 | 84 | |
6d0f6bcf JCPV |
85 | #define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */ |
86 | #define CONFIG_SYS_CPUSPEED 0x141 /* core clock - register value */ | |
281e00a3 | 87 | |
6d0f6bcf | 88 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
281e00a3 WD |
89 | #define CONFIG_BAUDRATE 115200 |
90 | /* | |
91 | * Definitions related to passing arguments to kernel. | |
92 | */ | |
93 | #define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */ | |
94 | #define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */ | |
95 | #define CONFIG_INITRD_TAG 1 /* send initrd params */ | |
96 | #undef CONFIG_VFD /* do not send framebuffer setup */ | |
97 | ||
281e00a3 WD |
98 | /* |
99 | * Malloc pool need to host env + 128 Kb reserve for other allocations. | |
100 | */ | |
6d0f6bcf | 101 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128<<10) ) |
281e00a3 WD |
102 | |
103 | ||
6d0f6bcf | 104 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
281e00a3 WD |
105 | |
106 | #define CONFIG_STACKSIZE (120<<10) /* stack size */ | |
107 | ||
108 | #ifdef CONFIG_USE_IRQ | |
109 | #define CONFIG_STACKSIZE_IRQ (4<<10) /* IRQ stack */ | |
110 | #define CONFIG_STACKSIZE_FIQ (4<<10) /* FIQ stack */ | |
111 | #endif | |
112 | ||
113 | /* SDRAM Setup Values | |
114 | * 0x910a8300 Precharge Command CAS 3 | |
115 | * 0x910a8200 Precharge Command CAS 2 | |
116 | * | |
117 | * 0xa10a8300 AutoRefresh Command CAS 3 | |
118 | * 0xa10a8200 Set AutoRefresh Command CAS 2 | |
119 | */ | |
120 | #define PRECHARGE_CMD 0x910a8300 | |
121 | #define AUTOREFRESH_CMD 0xa10a8300 | |
122 | ||
281e00a3 WD |
123 | #define BUS32BIT_VERSION |
124 | /* | |
125 | * SDRAM Memory Map | |
126 | */ | |
127 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */ | |
128 | #define MX1FS2_SDRAM_1 0x08000000 /* SDRAM bank #1 */ | |
129 | #ifdef BUS32BIT_VERSION | |
130 | #define MX1FS2_SDRAM_1_SIZE (0x04000000 - 0x100000) /* 64 MB - 1M Framebuffer */ | |
131 | #else | |
132 | #define MX1FS2_SDRAM_1_SIZE (0x01FC0000 - 0x100000) /* 32 MB - 1M Framebuffer */ | |
133 | #endif | |
134 | /* | |
135 | * Flash Controller settings | |
136 | */ | |
137 | ||
6d0f6bcf JCPV |
138 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/ |
139 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* number of sector in FLASH bank */ | |
281e00a3 WD |
140 | |
141 | #ifdef BUS32BIT_VERSION | |
142 | #define MX1FS2_FLASH_BUS_WIDTH 4 /* we use 32 bit FLASH memory... */ | |
143 | #define MX1FS2_FLASH_INTERLEAVE 2 /* ... made of 2 chips */ | |
144 | #define MX1FS2_FLASH_BANK_SIZE 0x02000000 /* size of one flash bank*/ | |
145 | #define MX1FS2_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */ | |
281e00a3 WD |
146 | #else |
147 | #define MX1FS2_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */ | |
148 | #define MX1FS2_FLASH_INTERLEAVE 1 /* ... made of 1 chip */ | |
149 | #define MX1FS2_FLASH_BANK_SIZE 0x01000000 /* size of one flash bank*/ | |
150 | #define MX1FS2_FLASH_SECT_SIZE 0x00010000 /* size of erase sector */ | |
151 | #endif | |
152 | #define MX1FS2_FLASH_BASE 0x10000000 /* location of flash memory */ | |
153 | #define MX1FS2_FLASH_UNLOCK 1 /* perform hw unlock first */ | |
154 | ||
155 | /* This should be defined if CFI FLASH device is present. Actually benefit | |
156 | is not so clear to me. In other words we can provide more informations | |
157 | to user, but this expects more complex flash handling we do not provide | |
158 | now.*/ | |
6d0f6bcf | 159 | #undef CONFIG_SYS_FLASH_CFI |
281e00a3 | 160 | |
6d0f6bcf JCPV |
161 | #define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* timeout for Erase operation */ |
162 | #define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* timeout for Write operation */ | |
281e00a3 | 163 | |
6d0f6bcf | 164 | #define CONFIG_SYS_FLASH_BASE MX1FS2_FLASH_BASE |
281e00a3 WD |
165 | |
166 | /* | |
167 | * This is setting for JFFS2 support in u-boot. | |
168 | * Right now there is no gain for user, but later on booting kernel might be | |
169 | * possible. Consider using XIP kernel running from flash to save RAM | |
170 | * footprint. | |
7f5c0157 | 171 | * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. |
281e00a3 | 172 | */ |
700a0c64 WD |
173 | |
174 | /* | |
175 | * JFFS2 partitions | |
176 | */ | |
177 | /* No command line, one static partition, whole device */ | |
178 | /* | |
179 | #undef CONFIG_JFFS2_CMDLINE | |
180 | #define CONFIG_JFFS2_DEV "nor0" | |
181 | #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF | |
182 | #define CONFIG_JFFS2_PART_OFFSET 0x00050000 | |
183 | */ | |
184 | ||
185 | /* mtdparts command line support */ | |
186 | /* Note: fake mtd_id used, no linux mtd map file */ | |
187 | #define CONFIG_JFFS2_CMDLINE | |
188 | #define MTDIDS_DEFAULT "nor0=mx1fs2-0" | |
189 | ||
190 | #ifdef BUS32BIT_VERSION | |
191 | #define MTDPARTS_DEFAULT "mtdparts=mx1fs2-0:2m@5m(part0),5m@9m(part1)" | |
192 | #else | |
193 | #define MTDPARTS_DEFAULT "mtdparts=mx1fs2-0:-@320k(jffs2)" | |
194 | #endif | |
281e00a3 WD |
195 | |
196 | /* | |
197 | * Environment setup. Definitions of monitor location and size with | |
198 | * definition of environment setup ends up in 2 possibilities. | |
199 | * 1. Embeded environment - in u-boot code is space for environment | |
200 | * 2. Environment is read from predefined sector of flash | |
201 | * Right now we support 2. possiblity, but expecting no env placed | |
202 | * on mentioned address right now. This also needs to provide whole | |
203 | * sector for it - for us 256Kb is really waste of memory. U-boot uses | |
204 | * default env. and until kernel parameters could be sent to kernel | |
205 | * env. has no sense to us. | |
206 | */ | |
207 | ||
6d0f6bcf JCPV |
208 | #define CONFIG_SYS_MONITOR_BASE 0x10000000 |
209 | #define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128b ( 1 flash sector ) */ | |
5a1aceb0 | 210 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
211 | #define CONFIG_ENV_ADDR 0x10020000 /* absolute address for now */ |
212 | #define CONFIG_ENV_SIZE 0x20000 | |
281e00a3 WD |
213 | |
214 | #define CONFIG_ENV_OVERWRITE 1 /* env is not writable now */ | |
215 | ||
216 | /* Setup CS4 and CS5 */ | |
6d0f6bcf | 217 | #define CONFIG_SYS_GIUS_A_VAL 0x0003fffe |
281e00a3 WD |
218 | |
219 | /* | |
220 | * CSxU_VAL: | |
221 | * 63| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x|32 | |
222 | * |DTACK_SEL|0|BCD | BCS | PSZ|PME|SYNC| DOL | CNC| WSC | 0| WWS | EDC | | |
223 | * | |
224 | * CSxL_VAL: | |
225 | * 31| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x| 0 | |
226 | * | OEA | OEN | WEA | WEN | CSA |EBC| DSZ | 0|SP|0|WP| 0 0|PA|CSEN| | |
227 | */ | |
228 | ||
6d0f6bcf JCPV |
229 | #define CONFIG_SYS_CS0U_VAL 0x00008C00 |
230 | #define CONFIG_SYS_CS0L_VAL 0x22222601 | |
231 | #define CONFIG_SYS_CS1U_VAL 0x00008C00 | |
232 | #define CONFIG_SYS_CS1L_VAL 0x22222301 | |
233 | #define CONFIG_SYS_CS4U_VAL 0x00008C00 | |
234 | #define CONFIG_SYS_CS4L_VAL 0x22222301 | |
235 | #define CONFIG_SYS_CS5U_VAL 0x00008C00 | |
236 | #define CONFIG_SYS_CS5L_VAL 0x22222301 | |
281e00a3 WD |
237 | |
238 | /* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1) | |
239 | f_ref=16,777MHz | |
240 | ||
241 | 0x002a141f: 191,9944MHz | |
242 | 0x040b2007: 144MHz | |
243 | 0x042a141f: 96MHz | |
244 | 0x0811140d: 64MHz | |
245 | 0x040e200e: 150MHz | |
246 | 0x00321431: 200MHz | |
247 | ||
248 | 0x08001800: 64MHz mit 16er Quarz | |
249 | 0x04001800: 96MHz mit 16er Quarz | |
250 | 0x04002400: 144MHz mit 16er Quarz | |
251 | ||
252 | 31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0 | |
253 | |XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------| */ | |
254 | ||
6d0f6bcf JCPV |
255 | #define CONFIG_SYS_MPCTL0_VAL 0x07E723AD |
256 | #define CONFIG_SYS_MPCTL1_VAL 0x00000040 | |
257 | #define CONFIG_SYS_PCDR_VAL 0x00010005 | |
258 | #define CONFIG_SYS_GPCR_VAL 0x00000FFB | |
281e00a3 WD |
259 | |
260 | #define USE_16M_OSZI /* If you have one, you want to use it | |
261 | The internal 32kHz oszillator jitters */ | |
262 | #ifdef USE_16M_OSZI | |
263 | ||
6d0f6bcf JCPV |
264 | #define CONFIG_SYS_SPCTL0_VAL 0x04001401 |
265 | #define CONFIG_SYS_SPCTL1_VAL 0x0C000040 | |
266 | #define CONFIG_SYS_CSCR_VAL 0x07030003 | |
281e00a3 WD |
267 | #define CONFIG_SYS_CLK_FREQ 16780000 |
268 | #define CONFIG_SYSPLL_CLK_FREQ 16000000 | |
269 | ||
270 | #else | |
271 | ||
6d0f6bcf JCPV |
272 | #define CONFIG_SYS_SPCTL0_VAL 0x07E716D1 |
273 | #define CONFIG_SYS_CSCR_VAL 0x06000003 | |
281e00a3 WD |
274 | #define CONFIG_SYS_CLK_FREQ 16780000 |
275 | #define CONFIG_SYSPLL_CLK_FREQ 16780000 | |
276 | ||
277 | #endif | |
278 | ||
279 | /* | |
280 | * Well this has to be defined, but on the other hand it is used differently | |
281 | * one may expect. For instance loadb command do not cares :-) | |
282 | * So advice is - do not relay on this... | |
283 | */ | |
6d0f6bcf | 284 | #define CONFIG_SYS_LOAD_ADDR 0x08400000 |
281e00a3 | 285 | |
6d0f6bcf | 286 | #define CONFIG_SYS_FMCR_VAL 0x00000003 /* Reset Default */ |
281e00a3 WD |
287 | |
288 | /* Bit[0:3] contain PERCLK1DIV for UART 1 | |
289 | 0x000b00b ->b<- -> 192MHz/12=16MHz | |
290 | 0x000b00b ->8<- -> 144MHz/09=16MHz | |
291 | 0x000b00b ->3<- -> 64MHz/4=16MHz */ | |
292 | ||
293 | #ifdef _CONFIG_UART1 | |
294 | #define CONFIG_IMX_SERIAL1 | |
295 | #elif defined _CONFIG_UART2 | |
296 | #define CONFIG_IMX_SERIAL2 | |
297 | #elif defined _CONFIG_UART3 | defined _CONFIG_UART4 | |
298 | #define CONFIG_IMX_SERIAL_NONE | |
6d0f6bcf JCPV |
299 | #define CONFIG_SYS_NS16550 |
300 | #define CONFIG_SYS_NS16550_SERIAL | |
301 | #define CONFIG_SYS_NS16550_CLK 3686400 | |
302 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
281e00a3 WD |
303 | #define CONFIG_CONS_INDEX 1 |
304 | #ifdef _CONFIG_UART3 | |
6d0f6bcf | 305 | #define CONFIG_SYS_NS16550_COM1 0x15000000 |
281e00a3 | 306 | #elif defined _CONFIG_UART4 |
6d0f6bcf | 307 | #define CONFIG_SYS_NS16550_COM1 0x16000000 |
281e00a3 WD |
308 | #endif |
309 | #endif | |
310 | ||
311 | #endif /* __CONFIG_H */ |