[people/ms/u-boot.git] / include / configs / mx31ads.h

/*
 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
 *
 * Configuration settings for the MX31ADS Freescale board.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <asm/arch/mx31-regs.h>

 /* High Level Configuration Options */
#define CONFIG_ARM1136		1		/* This is an arm1136 CPU core */
#define CONFIG_MX31		1		/* in a mx31 */
#define CONFIG_MX31_HCLK_FREQ	26000000	/* RedBoot says 26MHz */
#define CONFIG_MX31_CLK32	32000

#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

/*
 * Disabled for now due to build problems under Debian and a significant increase
 * in the final file size: 144260 vs. 109536 Bytes.
 */
#if 0
#define CONFIG_OF_LIBFDT		1
#define CONFIG_FIT			1
#define CONFIG_FIT_VERBOSE		1
#endif

#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_INITRD_TAG		1

/*
 * Size of malloc() pool
 */
#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128 * 1024)
#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */

/*
 * Hardware drivers
 */

#define CONFIG_MX31_UART	1
#define CFG_MX31_UART1		1

#define CONFIG_HARD_SPI		1
#define CONFIG_MXC_SPI		1
#define CONFIG_MXC_SPI_IFACE	1	/* Default SPI interface number */

#define CONFIG_RTC_MC13783	1

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX	1
#define CONFIG_BAUDRATE		115200
#define CFG_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}

/***********************************************************
 * Command definition
 ***********************************************************/

#include <config_cmd_default.h>

#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_SPI
#define CONFIG_CMD_DATE

#define CONFIG_BOOTDELAY	3

#define CONFIG_LOADADDR		0x80800000	/* loadaddr env var */

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"uboot_addr=0xa0000000\0"					\
	"uboot=mx31ads/u-boot.bin\0"					\
	"kernel=mx31ads/uImage\0"					\
	"nfsroot=/opt/eldk/arm\0"					\
	"bootargs_base=setenv bootargs console=ttymxc0,115200\0"	\
	"bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "	\
		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"	\
	"bootcmd=run bootcmd_net\0"					\
	"bootcmd_net=run bootargs_base bootargs_nfs; "			\
		"tftpboot ${loadaddr} ${kernel}; bootm\0"		\
	"prg_uboot=tftpboot ${loadaddr} ${uboot}; "			\
		"protect off ${uboot_addr} 0xa003ffff; "		\
		"erase ${uboot_addr} 0xa003ffff; "			\
		"cp.b ${loadaddr} ${uboot_addr} ${filesize}; "		\
		"setenv filesize; saveenv\0"

#define CONFIG_DRIVER_CS8900	1
#define CS8900_BASE		0xb4020300
#define CS8900_BUS16		1	/* follow the Linux driver */

/*
 * The MX31ADS board seems to have a hardware "peculiarity" confirmed under
 * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A
 * controller inverted. The controller is capable of detecting and correcting
 * this, but it needs 4 network packets for that. Which means, at startup, you
 * will not receive answers to the first 4 packest, unless there have been some
 * broadcasts on the network, or your board is on a hub. Reducing the ARP
 * timeout from default 5 seconds to 200ms we speed up the initial TFTP
 * transfer, should the user wish one, significantly.
 */
#define CONFIG_ARP_TIMEOUT	200UL

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP		/* undef to save memory */
#define CFG_PROMPT		"=> "
#define CFG_CBSIZE		256		/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
#define CFG_MAXARGS		16		/* max number of command args */
#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */

#define CFG_MEMTEST_START	0		/* memtest works on */
#define CFG_MEMTEST_END		0x10000

#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */

#define CFG_LOAD_ADDR		CONFIG_LOADADDR

#define CFG_HZ			32000

#define CONFIG_CMDLINE_EDITING	1

/*-----------------------------------------------------------------------
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE	(128 * 1024)	/* regular stack */

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	1
#define PHYS_SDRAM_1		CSD0_BASE
#define PHYS_SDRAM_1_SIZE	(128 * 1024 * 1024)

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */
#define CFG_FLASH_BASE		CS0_BASE
#define CFG_MAX_FLASH_BANKS	1		/* max number of memory banks */
#define CFG_MAX_FLASH_SECT	262		/* max number of sectors on one chip */
#define CFG_MONITOR_BASE	CFG_FLASH_BASE	/* Monitor at beginning of flash */
#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256KiB */

#define	CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_SECT_SIZE	(32 * 1024)
#define CFG_ENV_SIZE		CFG_ENV_SECT_SIZE

/* Address and size of Redundant Environment Sector	*/
#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET + CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND	CFG_ENV_SIZE

/* S29WS256N NOR flash has 4 32KiB small sectors at the beginning and at the end.
 * The rest of 32MiB is in 128KiB big sectors. U-Boot occupies the low 4 sectors,
 * if we put environment next to it, we will have to occupy 128KiB for it.
 * Putting it at the top of flash we use only 32KiB. */
#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_ENV_SECT_SIZE)

/*-----------------------------------------------------------------------
 * CFI FLASH driver setup
 */
#define CFG_FLASH_CFI			1 /* Flash memory is CFI compliant */
#define CFG_FLASH_CFI_DRIVER		1 /* Use drivers/cfi_flash.c */
#define CONFIG_FLASH_SPANSION_S29WS_N	1 /* A non-standard buffered write algorithm */
#define CFG_FLASH_USE_BUFFER_WRITE	1 /* Use buffered writes (~10x faster) */
#define CFG_FLASH_PROTECTION		1 /* Use hardware sector protection */

/*
 * JFFS2 partitions
 */
#undef CONFIG_JFFS2_CMDLINE
#define CONFIG_JFFS2_DEV	"nor0"

#endif /* __CONFIG_H */
Commit	Line	Data
b5dc9b30 GL	1	/*
	2	* Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
	3	*
	4	* Configuration settings for the MX31ADS Freescale board.
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation; either version 2 of
	9	* the License, or (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	19	* MA 02111-1307 USA
	20	*/
	21
	22	#ifndef __CONFIG_H
	23	#define __CONFIG_H
	24
	25	#include <asm/arch/mx31-regs.h>
	26
	27	/* High Level Configuration Options */
	28	#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
	29	#define CONFIG_MX31 1 /* in a mx31 */
	30	#define CONFIG_MX31_HCLK_FREQ 26000000 /* RedBoot says 26MHz */
	31	#define CONFIG_MX31_CLK32 32000
	32
	33	#define CONFIG_DISPLAY_CPUINFO
	34	#define CONFIG_DISPLAY_BOARDINFO
	35
	36	/*
	37	* Disabled for now due to build problems under Debian and a significant increase
	38	* in the final file size: 144260 vs. 109536 Bytes.
	39	*/
	40	#if 0
	41	#define CONFIG_OF_LIBFDT 1
	42	#define CONFIG_FIT 1
	43	#define CONFIG_FIT_VERBOSE 1
	44	#endif
	45
	46	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	47	#define CONFIG_SETUP_MEMORY_TAGS 1
	48	#define CONFIG_INITRD_TAG 1
	49
	50	/*
	51	* Size of malloc() pool
	52	*/
	53	#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128 * 1024)
0a0b606f	54	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
b5dc9b30 GL	55
	56	/*
	57	* Hardware drivers
	58	*/
	59
	60	#define CONFIG_MX31_UART 1
	61	#define CFG_MX31_UART1 1
	62
0a0b606f GL	63	#define CONFIG_HARD_SPI 1
	64	#define CONFIG_MXC_SPI 1
	65	#define CONFIG_MXC_SPI_IFACE 1 /* Default SPI interface number */
	66
	67	#define CONFIG_RTC_MC13783 1
	68
b5dc9b30 GL	69	/* allow to overwrite serial and ethaddr */
	70	#define CONFIG_ENV_OVERWRITE
	71	#define CONFIG_CONS_INDEX 1
	72	#define CONFIG_BAUDRATE 115200
	73	#define CFG_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
	74
	75	/***********************************************************
	76	* Command definition
	77	***********************************************************/
	78
	79	#include <config_cmd_default.h>
	80
b5dc9b30	81	#define CONFIG_CMD_PING
7602ed50	82	#define CONFIG_CMD_DHCP
0a0b606f GL	83	#define CONFIG_CMD_SPI
0a0b606f GL	84	#define CONFIG_CMD_DATE
b5dc9b30 GL	85
	86	#define CONFIG_BOOTDELAY 3
	87
7602ed50	88	#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
0a0b606f GL	89
	90	#define CONFIG_EXTRA_ENV_SETTINGS \
	91	"netdev=eth0\0" \
	92	"uboot_addr=0xa0000000\0" \
	93	"uboot=mx31ads/u-boot.bin\0" \
	94	"kernel=mx31ads/uImage\0" \
	95	"nfsroot=/opt/eldk/arm\0" \
	96	"bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
	97	"bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \
	98	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
	99	"bootcmd=run bootcmd_net\0" \
	100	"bootcmd_net=run bootargs_base bootargs_nfs; " \
	101	"tftpboot ${loadaddr} ${kernel}; bootm\0" \
	102	"prg_uboot=tftpboot ${loadaddr} ${uboot}; " \
	103	"protect off ${uboot_addr} 0xa003ffff; " \
	104	"erase ${uboot_addr} 0xa003ffff; " \
	105	"cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \
	106	"setenv filesize; saveenv\0"
b5dc9b30 GL	107
	108	#define CONFIG_DRIVER_CS8900 1
	109	#define CS8900_BASE 0xb4020300
d23ff682 GL	110	#define CS8900_BUS16 1 /* follow the Linux driver */
	111
	112	/*
	113	* The MX31ADS board seems to have a hardware "peculiarity" confirmed under
	114	* U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A
	115	* controller inverted. The controller is capable of detecting and correcting
	116	* this, but it needs 4 network packets for that. Which means, at startup, you
	117	* will not receive answers to the first 4 packest, unless there have been some
	118	* broadcasts on the network, or your board is on a hub. Reducing the ARP
	119	* timeout from default 5 seconds to 200ms we speed up the initial TFTP
	120	* transfer, should the user wish one, significantly.
	121	*/
	122	#define CONFIG_ARP_TIMEOUT 200UL
b5dc9b30 GL	123
	124	/*
	125	* Miscellaneous configurable options
	126	*/
	127	#define CFG_LONGHELP /* undef to save memory */
	128	#define CFG_PROMPT "=> "
	129	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	130	/* Print Buffer Size */
d23ff682	131	#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
b5dc9b30 GL	132	#define CFG_MAXARGS 16 /* max number of command args */
	133	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	134
	135	#define CFG_MEMTEST_START 0 /* memtest works on */
	136	#define CFG_MEMTEST_END 0x10000
	137
	138	#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
	139
0a0b606f	140	#define CFG_LOAD_ADDR CONFIG_LOADADDR
b5dc9b30 GL	141
	142	#define CFG_HZ 32000
	143
	144	#define CONFIG_CMDLINE_EDITING 1
	145
	146	/*-----------------------------------------------------------------------
	147	* Stack sizes
	148	*
	149	* The stack sizes are set up in start.S using the settings below
	150	*/
	151	#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
	152
	153	/*-----------------------------------------------------------------------
	154	* Physical Memory Map
	155	*/
	156	#define CONFIG_NR_DRAM_BANKS 1
	157	#define PHYS_SDRAM_1 CSD0_BASE
	158	#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
	159
	160	/*-----------------------------------------------------------------------
	161	* FLASH and environment organization
	162	*/
	163	#define CFG_FLASH_BASE CS0_BASE
	164	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	165	#define CFG_MAX_FLASH_SECT 262 /* max number of sectors on one chip */
	166	#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at beginning of flash */
d23ff682	167	#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256KiB */
b5dc9b30 GL	168
	169	#define CFG_ENV_IS_IN_FLASH 1
	170	#define CFG_ENV_SECT_SIZE (32 * 1024)
	171	#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
d23ff682 GL	172
	173	/* Address and size of Redundant Environment Sector */
	174	#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE)
	175	#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
	176
b5dc9b30 GL	177	/* S29WS256N NOR flash has 4 32KiB small sectors at the beginning and at the end.
	178	* The rest of 32MiB is in 128KiB big sectors. U-Boot occupies the low 4 sectors,
	179	* if we put environment next to it, we will have to occupy 128KiB for it.
	180	* Putting it at the top of flash we use only 32KiB. */
d23ff682	181	#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_ENV_SECT_SIZE)
b5dc9b30 GL	182
	183	/*-----------------------------------------------------------------------
	184	* CFI FLASH driver setup
	185	*/
	186	#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */
	187	#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
d23ff682	188	#define CONFIG_FLASH_SPANSION_S29WS_N 1 /* A non-standard buffered write algorithm */
b5dc9b30	189	#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
b5dc9b30 GL	190	#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */
	191
	192	/*
	193	* JFFS2 partitions
	194	*/
	195	#undef CONFIG_JFFS2_CMDLINE
	196	#define CONFIG_JFFS2_DEV "nor0"
	197
	198	#endif /* __CONFIG_H */