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860b32ee FE |
1 | /* |
2 | * Copyright (C) 2011 Freescale Semiconductor, Inc. | |
3 | * | |
c4c596fb | 4 | * Configuration settings for the MX53SMD Freescale board. |
860b32ee | 5 | * |
3765b3e7 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
860b32ee FE |
7 | */ |
8 | ||
9 | #ifndef __CONFIG_H | |
10 | #define __CONFIG_H | |
11 | ||
c4c596fb FE |
12 | #define CONFIG_MACH_TYPE MACH_TYPE_MX53_SMD |
13 | ||
860b32ee FE |
14 | #include <asm/arch/imx-regs.h> |
15 | ||
16 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ | |
860b32ee FE |
17 | #define CONFIG_SETUP_MEMORY_TAGS |
18 | #define CONFIG_INITRD_TAG | |
fd622f23 | 19 | #define CONFIG_REVISION_TAG |
860b32ee | 20 | |
18fb0e3c | 21 | #define CONFIG_SYS_FSL_CLK |
5a416df0 | 22 | |
860b32ee FE |
23 | /* Size of malloc() pool */ |
24 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) | |
25 | ||
860b32ee | 26 | #define CONFIG_MXC_UART |
40f6fffe | 27 | #define CONFIG_MXC_UART_BASE UART1_BASE |
860b32ee FE |
28 | |
29 | /* I2C Configs */ | |
b089d039 | 30 | #define CONFIG_SYS_I2C |
31 | #define CONFIG_SYS_I2C_MXC | |
03544c66 AA |
32 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ |
33 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ | |
f8cb101e | 34 | #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ |
860b32ee FE |
35 | |
36 | /* MMC Configs */ | |
37 | #define CONFIG_FSL_ESDHC | |
38 | #define CONFIG_SYS_FSL_ESDHC_ADDR 0 | |
39 | #define CONFIG_SYS_FSL_ESDHC_NUM 1 | |
40 | ||
860b32ee FE |
41 | /* Eth Configs */ |
42 | #define CONFIG_HAS_ETH1 | |
860b32ee | 43 | #define CONFIG_MII |
860b32ee FE |
44 | |
45 | #define CONFIG_FEC_MXC | |
46 | #define IMX_FEC_BASE FEC_BASE_ADDR | |
47 | #define CONFIG_FEC_MXC_PHYADDR 0x1F | |
48 | ||
860b32ee FE |
49 | /* allow to overwrite serial and ethaddr */ |
50 | #define CONFIG_ENV_OVERWRITE | |
51 | #define CONFIG_CONS_INDEX 1 | |
860b32ee FE |
52 | |
53 | /* Command definition */ | |
860b32ee | 54 | |
28b119e9 | 55 | #define CONFIG_ETHPRIME "FEC0" |
860b32ee FE |
56 | |
57 | #define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */ | |
860b32ee FE |
58 | |
59 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
60 | "script=boot.scr\0" \ | |
61 | "uimage=uImage\0" \ | |
62 | "mmcdev=0\0" \ | |
63 | "mmcpart=2\0" \ | |
64 | "mmcroot=/dev/mmcblk0p3 rw\0" \ | |
65 | "mmcrootfstype=ext3 rootwait\0" \ | |
66 | "mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \ | |
67 | "root=${mmcroot} " \ | |
68 | "rootfstype=${mmcrootfstype}\0" \ | |
69 | "loadbootscript=" \ | |
70 | "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ | |
71 | "bootscript=echo Running bootscript from mmc ...; " \ | |
72 | "source\0" \ | |
73 | "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ | |
74 | "mmcboot=echo Booting from mmc ...; " \ | |
75 | "run mmcargs; " \ | |
76 | "bootm\0" \ | |
77 | "netargs=setenv bootargs console=ttymxc0,${baudrate} " \ | |
78 | "root=/dev/nfs " \ | |
79 | "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ | |
80 | "netboot=echo Booting from net ...; " \ | |
81 | "run netargs; " \ | |
82 | "dhcp ${uimage}; bootm\0" \ | |
83 | ||
84 | #define CONFIG_BOOTCOMMAND \ | |
66968110 | 85 | "mmc dev ${mmcdev}; if mmc rescan; then " \ |
860b32ee FE |
86 | "if run loadbootscript; then " \ |
87 | "run bootscript; " \ | |
88 | "else " \ | |
89 | "if run loaduimage; then " \ | |
90 | "run mmcboot; " \ | |
91 | "else run netboot; " \ | |
92 | "fi; " \ | |
93 | "fi; " \ | |
94 | "else run netboot; fi" | |
95 | #define CONFIG_ARP_TIMEOUT 200UL | |
96 | ||
97 | /* Miscellaneous configurable options */ | |
98 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
860b32ee | 99 | #define CONFIG_AUTO_COMPLETE |
860b32ee | 100 | |
860b32ee | 101 | #define CONFIG_SYS_MEMTEST_START 0x70000000 |
869aed7b | 102 | #define CONFIG_SYS_MEMTEST_END 0x70010000 |
860b32ee FE |
103 | |
104 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR | |
105 | ||
860b32ee FE |
106 | #define CONFIG_CMDLINE_EDITING |
107 | ||
860b32ee FE |
108 | /* Physical Memory Map */ |
109 | #define CONFIG_NR_DRAM_BANKS 2 | |
110 | #define PHYS_SDRAM_1 CSD0_BASE_ADDR | |
111 | #define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) | |
112 | #define PHYS_SDRAM_2 CSD1_BASE_ADDR | |
113 | #define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024) | |
114 | #define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE) | |
115 | ||
116 | #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) | |
117 | #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) | |
118 | #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) | |
119 | ||
120 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
121 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
122 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
123 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
124 | ||
e856bdcf | 125 | /* environment organization */ |
860b32ee FE |
126 | #define CONFIG_ENV_OFFSET (6 * 64 * 1024) |
127 | #define CONFIG_ENV_SIZE (8 * 1024) | |
860b32ee FE |
128 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
129 | ||
860b32ee | 130 | #endif /* __CONFIG_H */ |