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bc5833c4 JL |
1 | /* |
2 | * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * Configuration settings for the Freescale i.MX6Q Sabre Lite board. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
8 | * published by the Free Software Foundation; either version 2 of | |
9 | * the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
f5cdc117 | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
bc5833c4 JL |
14 | * GNU General Public License for more details. |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
19 | * MA 02111-1307 USA | |
20 | */ | |
21 | ||
22 | #ifndef __CONFIG_H | |
23 | #define __CONFIG_H | |
24 | ||
25 | #define CONFIG_MX6Q | |
f5cdc117 WD |
26 | #define CONFIG_SYS_MX6_HCLK 24000000 |
27 | #define CONFIG_SYS_MX6_CLK32 32768 | |
bc5833c4 JL |
28 | #define CONFIG_DISPLAY_CPUINFO |
29 | #define CONFIG_DISPLAY_BOARDINFO | |
30 | ||
c338f0b5 EN |
31 | #define CONFIG_MACH_TYPE 3769 |
32 | ||
bc5833c4 JL |
33 | #include <asm/arch/imx-regs.h> |
34 | ||
35 | #define CONFIG_CMDLINE_TAG | |
36 | #define CONFIG_SETUP_MEMORY_TAGS | |
37 | #define CONFIG_INITRD_TAG | |
1c9ceff8 | 38 | #define CONFIG_REVISION_TAG |
bc5833c4 JL |
39 | |
40 | /* Size of malloc() pool */ | |
f5cdc117 | 41 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) |
bc5833c4 JL |
42 | |
43 | #define CONFIG_ARCH_CPU_INIT | |
44 | #define CONFIG_BOARD_EARLY_INIT_F | |
28fdbddc | 45 | #define CONFIG_MISC_INIT_R |
bc5833c4 JL |
46 | #define CONFIG_MXC_GPIO |
47 | ||
48 | #define CONFIG_MXC_UART | |
f5cdc117 | 49 | #define CONFIG_MXC_UART_BASE UART2_BASE |
bc5833c4 | 50 | |
373a1d8c EN |
51 | #define CONFIG_CMD_SF |
52 | #ifdef CONFIG_CMD_SF | |
53 | #define CONFIG_SPI_FLASH | |
54 | #define CONFIG_SPI_FLASH_SST | |
55 | #define CONFIG_MXC_SPI | |
ba54b927 EN |
56 | #define CONFIG_SF_DEFAULT_BUS 0 |
57 | #define CONFIG_SF_DEFAULT_CS (0|(GPIO_NUMBER(3, 19)<<8)) | |
373a1d8c EN |
58 | #define CONFIG_SF_DEFAULT_SPEED 25000000 |
59 | #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) | |
60 | #endif | |
61 | ||
bc5833c4 JL |
62 | /* MMC Configs */ |
63 | #define CONFIG_FSL_ESDHC | |
64 | #define CONFIG_FSL_USDHC | |
65 | #define CONFIG_SYS_FSL_ESDHC_ADDR 0 | |
66 | #define CONFIG_SYS_FSL_USDHC_NUM 2 | |
67 | ||
68 | #define CONFIG_MMC | |
69 | #define CONFIG_CMD_MMC | |
70 | #define CONFIG_GENERIC_MMC | |
9ff323df | 71 | #define CONFIG_CMD_EXT2 |
bc5833c4 JL |
72 | #define CONFIG_CMD_FAT |
73 | #define CONFIG_DOS_PARTITION | |
74 | ||
3996a96c EN |
75 | #define CONFIG_CMD_SATA |
76 | /* | |
77 | * SATA Configs | |
78 | */ | |
79 | #ifdef CONFIG_CMD_SATA | |
80 | #define CONFIG_DWC_AHSATA | |
81 | #define CONFIG_SYS_SATA_MAX_DEVICE 1 | |
82 | #define CONFIG_DWC_AHSATA_PORT_ID 0 | |
83 | #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR | |
84 | #define CONFIG_LBA48 | |
85 | #define CONFIG_LIBATA | |
86 | #endif | |
87 | ||
2af81e27 JL |
88 | #define CONFIG_CMD_PING |
89 | #define CONFIG_CMD_DHCP | |
90 | #define CONFIG_CMD_MII | |
91 | #define CONFIG_CMD_NET | |
f5cdc117 WD |
92 | #define CONFIG_FEC_MXC |
93 | #define CONFIG_MII | |
2af81e27 | 94 | #define IMX_FEC_BASE ENET_BASE_ADDR |
f5cdc117 | 95 | #define CONFIG_FEC_XCV_TYPE RGMII |
2af81e27 JL |
96 | #define CONFIG_ETHPRIME "FEC" |
97 | #define CONFIG_FEC_MXC_PHYADDR 6 | |
2bf3359e TK |
98 | #define CONFIG_PHYLIB |
99 | #define CONFIG_PHY_MICREL | |
2af81e27 | 100 | |
2ea73e9e WG |
101 | /* USB Configs */ |
102 | #define CONFIG_CMD_USB | |
103 | #define CONFIG_CMD_FAT | |
104 | #define CONFIG_USB_EHCI | |
105 | #define CONFIG_USB_EHCI_MX6 | |
106 | #define CONFIG_USB_STORAGE | |
107 | #define CONFIG_USB_HOST_ETHER | |
108 | #define CONFIG_USB_ETHER_ASIX | |
109 | #define CONFIG_USB_ETHER_SMSC95XX | |
110 | #define CONFIG_MXC_USB_PORT 1 | |
111 | #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) | |
112 | #define CONFIG_MXC_USB_FLAGS 0 | |
113 | ||
bc5833c4 JL |
114 | /* allow to overwrite serial and ethaddr */ |
115 | #define CONFIG_ENV_OVERWRITE | |
f5cdc117 WD |
116 | #define CONFIG_CONS_INDEX 1 |
117 | #define CONFIG_BAUDRATE 115200 | |
bc5833c4 JL |
118 | |
119 | /* Command definition */ | |
120 | #include <config_cmd_default.h> | |
121 | ||
122 | #undef CONFIG_CMD_IMLS | |
bc5833c4 | 123 | |
f5cdc117 | 124 | #define CONFIG_BOOTDELAY 3 |
bc5833c4 | 125 | |
28fdbddc EN |
126 | #define CONFIG_PREBOOT "" |
127 | ||
f5cdc117 WD |
128 | #define CONFIG_LOADADDR 0x10800000 |
129 | #define CONFIG_SYS_TEXT_BASE 0x17800000 | |
bc5833c4 JL |
130 | |
131 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
132 | "script=boot.scr\0" \ | |
133 | "uimage=uImage\0" \ | |
f4ac6cb6 | 134 | "console=ttymxc1\0" \ |
7e9603e7 DB |
135 | "fdt_high=0xffffffff\0" \ |
136 | "initrd_high=0xffffffff\0" \ | |
bc5833c4 JL |
137 | "mmcdev=0\0" \ |
138 | "mmcpart=2\0" \ | |
139 | "mmcroot=/dev/mmcblk0p3 rootwait rw\0" \ | |
140 | "mmcargs=setenv bootargs console=${console},${baudrate} " \ | |
f5cdc117 | 141 | "root=${mmcroot}\0" \ |
bc5833c4 | 142 | "loadbootscript=" \ |
f5cdc117 | 143 | "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ |
bc5833c4 | 144 | "bootscript=echo Running bootscript from mmc ...; " \ |
f5cdc117 | 145 | "source\0" \ |
bc5833c4 JL |
146 | "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ |
147 | "mmcboot=echo Booting from mmc ...; " \ | |
f5cdc117 WD |
148 | "run mmcargs; " \ |
149 | "bootm\0" \ | |
bc5833c4 | 150 | "netargs=setenv bootargs console=${console},${baudrate} " \ |
f5cdc117 WD |
151 | "root=/dev/nfs " \ |
152 | "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ | |
bc5833c4 | 153 | "netboot=echo Booting from net ...; " \ |
f5cdc117 WD |
154 | "run netargs; " \ |
155 | "dhcp ${uimage}; bootm\0" \ | |
bc5833c4 JL |
156 | |
157 | #define CONFIG_BOOTCOMMAND \ | |
158 | "mmc dev ${mmcdev};" \ | |
159 | "if mmc rescan ${mmcdev}; then " \ | |
f5cdc117 WD |
160 | "if run loadbootscript; then " \ |
161 | "run bootscript; " \ | |
162 | "else " \ | |
163 | "if run loaduimage; then " \ | |
164 | "run mmcboot; " \ | |
165 | "else run netboot; " \ | |
166 | "fi; " \ | |
167 | "fi; " \ | |
bc5833c4 JL |
168 | "else run netboot; fi" |
169 | ||
170 | #define CONFIG_ARP_TIMEOUT 200UL | |
171 | ||
172 | /* Miscellaneous configurable options */ | |
173 | #define CONFIG_SYS_LONGHELP | |
174 | #define CONFIG_SYS_HUSH_PARSER | |
f5cdc117 | 175 | #define CONFIG_SYS_PROMPT "MX6QSABRELITE U-Boot > " |
bc5833c4 | 176 | #define CONFIG_AUTO_COMPLETE |
f5cdc117 | 177 | #define CONFIG_SYS_CBSIZE 256 |
bc5833c4 JL |
178 | |
179 | /* Print Buffer Size */ | |
180 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
f5cdc117 | 181 | #define CONFIG_SYS_MAXARGS 16 |
bc5833c4 JL |
182 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
183 | ||
184 | #define CONFIG_SYS_MEMTEST_START 0x10000000 | |
f5cdc117 | 185 | #define CONFIG_SYS_MEMTEST_END 0x10010000 |
bc5833c4 | 186 | |
f5cdc117 WD |
187 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
188 | #define CONFIG_SYS_HZ 1000 | |
bc5833c4 JL |
189 | |
190 | #define CONFIG_CMDLINE_EDITING | |
f5cdc117 | 191 | #define CONFIG_STACKSIZE (128 * 1024) |
bc5833c4 JL |
192 | |
193 | /* Physical Memory Map */ | |
f5cdc117 WD |
194 | #define CONFIG_NR_DRAM_BANKS 1 |
195 | #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR | |
196 | #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) | |
bc5833c4 | 197 | |
f5cdc117 | 198 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM |
bc5833c4 JL |
199 | #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR |
200 | #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE | |
201 | ||
202 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
203 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
204 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
205 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
206 | ||
207 | /* FLASH and environment organization */ | |
208 | #define CONFIG_SYS_NO_FLASH | |
209 | ||
913b321a EN |
210 | #define CONFIG_ENV_SIZE (8 * 1024) |
211 | ||
bc5833c4 | 212 | #define CONFIG_ENV_IS_IN_MMC |
913b321a EN |
213 | /* #define CONFIG_ENV_IS_IN_SPI_FLASH */ |
214 | ||
215 | #if defined(CONFIG_ENV_IS_IN_MMC) | |
216 | #define CONFIG_ENV_OFFSET (6 * 64 * 1024) | |
217 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
218 | #elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) | |
219 | #define CONFIG_ENV_OFFSET (768 * 1024) | |
220 | #define CONFIG_ENV_SECT_SIZE (8 * 1024) | |
221 | #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS | |
222 | #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS | |
223 | #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE | |
224 | #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED | |
225 | #endif | |
bc5833c4 JL |
226 | |
227 | #define CONFIG_OF_LIBFDT | |
5fbfd1c2 | 228 | #define CONFIG_CMD_BOOTZ |
bc5833c4 | 229 | |
4d422fe2 EN |
230 | #define CONFIG_SYS_DCACHE_OFF |
231 | ||
66b4170b EN |
232 | #ifndef CONFIG_SYS_DCACHE_OFF |
233 | #define CONFIG_CMD_CACHE | |
234 | #endif | |
235 | ||
f5cdc117 | 236 | #endif /* __CONFIG_H */ |