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57ca432f FE |
1 | /* |
2 | * Copyright 2013 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * Configuration settings for the Freescale i.MX6SL EVK board. | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
57ca432f FE |
7 | */ |
8 | ||
9 | #ifndef __CONFIG_H | |
10 | #define __CONFIG_H | |
11 | ||
a6bbee66 | 12 | #include "mx6_common.h" |
57ca432f | 13 | |
e7d3b21b PF |
14 | #ifdef CONFIG_SPL |
15 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
16 | #define CONFIG_SPL_MMC_SUPPORT | |
e7d3b21b PF |
17 | #include "imx6_spl.h" |
18 | #endif | |
19 | ||
57ca432f FE |
20 | #define MACH_TYPE_MX6SLEVK 4307 |
21 | #define CONFIG_MACH_TYPE MACH_TYPE_MX6SLEVK | |
22 | ||
57ca432f FE |
23 | /* Size of malloc() pool */ |
24 | #define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) | |
25 | ||
26 | #define CONFIG_BOARD_EARLY_INIT_F | |
57ca432f FE |
27 | |
28 | #define CONFIG_MXC_UART | |
29 | #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR | |
30 | ||
31 | /* MMC Configs */ | |
08129d61 | 32 | #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR |
57ca432f | 33 | |
c8200905 | 34 | /* I2C Configs */ |
c8200905 PF |
35 | #define CONFIG_SYS_I2C |
36 | #define CONFIG_SYS_I2C_MXC | |
03544c66 AA |
37 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ |
38 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ | |
f8cb101e | 39 | #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ |
c8200905 PF |
40 | #define CONFIG_SYS_I2C_SPEED 100000 |
41 | ||
42 | /* PMIC */ | |
43 | #define CONFIG_POWER | |
44 | #define CONFIG_POWER_I2C | |
45 | #define CONFIG_POWER_PFUZE100 | |
46 | #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 | |
47 | ||
31f07964 | 48 | #define CONFIG_CMD_MII |
31f07964 FE |
49 | #define CONFIG_FEC_MXC |
50 | #define CONFIG_MII | |
51 | #define IMX_FEC_BASE ENET_BASE_ADDR | |
52 | #define CONFIG_FEC_XCV_TYPE RMII | |
31f07964 FE |
53 | #define CONFIG_FEC_MXC_PHYADDR 0 |
54 | ||
55 | #define CONFIG_PHYLIB | |
56 | #define CONFIG_PHY_SMSC | |
57 | ||
57ca432f FE |
58 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
59 | "script=boot.scr\0" \ | |
8e184a53 | 60 | "image=zImage\0" \ |
57ca432f FE |
61 | "console=ttymxc0\0" \ |
62 | "fdt_high=0xffffffff\0" \ | |
63 | "initrd_high=0xffffffff\0" \ | |
64 | "fdt_file=imx6sl-evk.dtb\0" \ | |
6fc049be | 65 | "fdt_addr=0x88000000\0" \ |
57ca432f FE |
66 | "boot_fdt=try\0" \ |
67 | "ip_dyn=yes\0" \ | |
adc5a667 | 68 | "mmcdev=1\0" \ |
94aeb8a6 OS |
69 | "mmcpart=1\0" \ |
70 | "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ | |
57ca432f FE |
71 | "mmcargs=setenv bootargs console=${console},${baudrate} " \ |
72 | "root=${mmcroot}\0" \ | |
73 | "loadbootscript=" \ | |
74 | "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ | |
75 | "bootscript=echo Running bootscript from mmc ...; " \ | |
76 | "source\0" \ | |
8e184a53 | 77 | "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ |
57ca432f FE |
78 | "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ |
79 | "mmcboot=echo Booting from mmc ...; " \ | |
80 | "run mmcargs; " \ | |
81 | "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ | |
82 | "if run loadfdt; then " \ | |
8e184a53 | 83 | "bootz ${loadaddr} - ${fdt_addr}; " \ |
57ca432f FE |
84 | "else " \ |
85 | "if test ${boot_fdt} = try; then " \ | |
8e184a53 | 86 | "bootz; " \ |
57ca432f FE |
87 | "else " \ |
88 | "echo WARN: Cannot load the DT; " \ | |
89 | "fi; " \ | |
90 | "fi; " \ | |
91 | "else " \ | |
8e184a53 | 92 | "bootz; " \ |
57ca432f FE |
93 | "fi;\0" \ |
94 | "netargs=setenv bootargs console=${console},${baudrate} " \ | |
95 | "root=/dev/nfs " \ | |
96 | "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ | |
97 | "netboot=echo Booting from net ...; " \ | |
98 | "run netargs; " \ | |
99 | "if test ${ip_dyn} = yes; then " \ | |
100 | "setenv get_cmd dhcp; " \ | |
101 | "else " \ | |
102 | "setenv get_cmd tftp; " \ | |
103 | "fi; " \ | |
8e184a53 | 104 | "${get_cmd} ${image}; " \ |
57ca432f FE |
105 | "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ |
106 | "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ | |
8e184a53 | 107 | "bootz ${loadaddr} - ${fdt_addr}; " \ |
57ca432f FE |
108 | "else " \ |
109 | "if test ${boot_fdt} = try; then " \ | |
8e184a53 | 110 | "bootz; " \ |
57ca432f FE |
111 | "else " \ |
112 | "echo WARN: Cannot load the DT; " \ | |
113 | "fi; " \ | |
114 | "fi; " \ | |
115 | "else " \ | |
8e184a53 | 116 | "bootz; " \ |
57ca432f FE |
117 | "fi;\0" |
118 | ||
119 | #define CONFIG_BOOTCOMMAND \ | |
120 | "mmc dev ${mmcdev};" \ | |
121 | "mmc dev ${mmcdev}; if mmc rescan; then " \ | |
122 | "if run loadbootscript; then " \ | |
123 | "run bootscript; " \ | |
124 | "else " \ | |
8e184a53 | 125 | "if run loadimage; then " \ |
57ca432f FE |
126 | "run mmcboot; " \ |
127 | "else run netboot; " \ | |
128 | "fi; " \ | |
129 | "fi; " \ | |
130 | "else run netboot; fi" | |
131 | ||
132 | /* Miscellaneous configurable options */ | |
57ca432f FE |
133 | #define CONFIG_SYS_MEMTEST_START 0x80000000 |
134 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_512M) | |
135 | ||
57ca432f FE |
136 | #define CONFIG_STACKSIZE SZ_128K |
137 | ||
138 | /* Physical Memory Map */ | |
139 | #define CONFIG_NR_DRAM_BANKS 1 | |
140 | #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR | |
141 | #define PHYS_SDRAM_SIZE SZ_1G | |
142 | ||
143 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM | |
144 | #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR | |
145 | #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE | |
146 | ||
147 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
148 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
149 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
150 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
151 | ||
056845c2 | 152 | /* Environment organization */ |
57ca432f | 153 | #define CONFIG_ENV_SIZE SZ_8K |
be2fde60 PF |
154 | |
155 | #if defined CONFIG_SYS_BOOT_SPINOR | |
156 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
157 | #define CONFIG_ENV_OFFSET (768 * 1024) | |
158 | #define CONFIG_ENV_SECT_SIZE (64 * 1024) | |
159 | #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS | |
160 | #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS | |
161 | #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE | |
162 | #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED | |
163 | #else | |
0da040bf | 164 | #define CONFIG_ENV_OFFSET (8 * SZ_64K) |
57ca432f | 165 | #define CONFIG_ENV_IS_IN_MMC |
be2fde60 | 166 | #endif |
57ca432f | 167 | |
694c3bc1 | 168 | #ifdef CONFIG_CMD_SF |
694c3bc1 FE |
169 | #define CONFIG_MXC_SPI |
170 | #define CONFIG_SF_DEFAULT_BUS 0 | |
155fa9af | 171 | #define CONFIG_SF_DEFAULT_CS 0 |
694c3bc1 FE |
172 | #define CONFIG_SF_DEFAULT_SPEED 20000000 |
173 | #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 | |
174 | #endif | |
175 | ||
3b9c1a5d | 176 | /* USB Configs */ |
3b9c1a5d PF |
177 | #ifdef CONFIG_CMD_USB |
178 | #define CONFIG_USB_EHCI | |
179 | #define CONFIG_USB_EHCI_MX6 | |
180 | #define CONFIG_USB_STORAGE | |
181 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
182 | #define CONFIG_USB_HOST_ETHER | |
183 | #define CONFIG_USB_ETHER_ASIX | |
184 | #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) | |
185 | #define CONFIG_MXC_USB_FLAGS 0 | |
186 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 | |
187 | #endif | |
188 | ||
36255d67 YL |
189 | #define CONFIG_SYS_FSL_USDHC_NUM 3 |
190 | #if defined(CONFIG_ENV_IS_IN_MMC) | |
191 | #define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC2*/ | |
192 | #endif | |
193 | ||
1368f993 | 194 | #define CONFIG_IMX_THERMAL |
27d36080 | 195 | |
57ca432f | 196 | #endif /* __CONFIG_H */ |