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d7b26d58 DE |
1 | /* |
2 | * (C) Copyright 2007-2008 | |
3 | * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de | |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
d7b26d58 DE |
6 | */ |
7 | ||
8 | #ifndef __CONFIG_H | |
9 | #define __CONFIG_H | |
10 | ||
d7b26d58 | 11 | #define CONFIG_405EP 1 /* this is a PPC405 CPU */ |
d7b26d58 DE |
12 | #define CONFIG_NEO 1 /* on a Neo board */ |
13 | ||
2ae18241 WD |
14 | #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 |
15 | ||
d7b26d58 DE |
16 | /* |
17 | * Include common defines/options for all AMCC eval boards | |
18 | */ | |
19 | #define CONFIG_HOSTNAME neo | |
20 | #include "amcc-common.h" | |
21 | ||
6e9e6c36 DE |
22 | #define CONFIG_BOARD_EARLY_INIT_R |
23 | #define CONFIG_MISC_INIT_R | |
24 | #define CONFIG_LAST_STAGE_INIT | |
d7b26d58 DE |
25 | |
26 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ | |
27 | ||
28 | /* | |
29 | * Configure PLL | |
30 | */ | |
31 | #define PLLMR0_DEFAULT PLLMR0_266_133_66_33 | |
32 | #define PLLMR1_DEFAULT PLLMR1_266_133_66_33 | |
33 | ||
d7b26d58 DE |
34 | #define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */ |
35 | ||
36 | /* | |
37 | * Default environment variables | |
38 | */ | |
39 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
40 | CONFIG_AMCC_DEF_ENV \ | |
41 | CONFIG_AMCC_DEF_ENV_POWERPC \ | |
42 | CONFIG_AMCC_DEF_ENV_NOR_UPD \ | |
43 | "kernel_addr=fc000000\0" \ | |
44 | "fdt_addr=fc1e0000\0" \ | |
45 | "ramdisk_addr=fc200000\0" \ | |
46 | "" | |
47 | ||
48 | #define CONFIG_PHY_ADDR 4 /* PHY address */ | |
49 | #define CONFIG_HAS_ETH0 | |
50 | #define CONFIG_HAS_ETH1 | |
51 | #define CONFIG_PHY1_ADDR 0xc /* EMAC1 PHY address */ | |
52 | #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ | |
53 | ||
54 | /* | |
55 | * Commands additional to the ones defined in amcc-common.h | |
56 | */ | |
4fb9b41b | 57 | #undef CONFIG_CMD_IRQ |
d7b26d58 DE |
58 | |
59 | /* | |
60 | * SDRAM configuration (please see cpu/ppc/sdram.[ch]) | |
61 | */ | |
62 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ | |
63 | ||
64 | /* SDRAM timings used in datasheet */ | |
65 | #define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */ | |
66 | #define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */ | |
67 | #define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */ | |
68 | #define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */ | |
69 | #define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */ | |
70 | ||
71 | /* | |
72 | * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1. | |
73 | * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31. | |
74 | * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value. | |
75 | * The Linux BASE_BAUD define should match this configuration. | |
76 | * baseBaud = cpuClock/(uartDivisor*16) | |
77 | * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, | |
78 | * set Linux BASE_BAUD to 403200. | |
79 | */ | |
550650dd | 80 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
550650dd SR |
81 | #define CONFIG_SYS_NS16550_SERIAL |
82 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
83 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
84 | ||
d7b26d58 DE |
85 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ |
86 | #undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ | |
87 | #define CONFIG_SYS_BASE_BAUD 691200 | |
88 | ||
89 | /* | |
90 | * I2C stuff | |
91 | */ | |
880540de | 92 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 |
d7b26d58 DE |
93 | |
94 | /* RTC */ | |
95 | #define CONFIG_RTC_DS1337 | |
96 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
97 | ||
d7b26d58 DE |
98 | /* |
99 | * FLASH organization | |
100 | */ | |
101 | #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ | |
102 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ | |
103 | ||
104 | #define CONFIG_SYS_FLASH_BASE 0xFC000000 | |
105 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
106 | ||
107 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
108 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ | |
109 | ||
110 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
111 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
112 | ||
113 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ | |
d7b26d58 DE |
114 | |
115 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ | |
116 | #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ | |
117 | ||
118 | #ifdef CONFIG_ENV_IS_IN_FLASH | |
119 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ | |
6e9e6c36 | 120 | #define CONFIG_ENV_ADDR 0xFFF00000 |
00251261 | 121 | #define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ |
d7b26d58 DE |
122 | |
123 | /* Address and size of Redundant Environment Sector */ | |
6e9e6c36 | 124 | #define CONFIG_ENV_ADDR_REDUND 0xFFF20000 |
d7b26d58 DE |
125 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
126 | #endif | |
127 | ||
128 | /* | |
129 | * PPC405 GPIO Configuration | |
130 | */ | |
6e9e6c36 DE |
131 | #define CONFIG_SYS_4xx_GPIO_TABLE { \ |
132 | { \ | |
133 | /* GPIO Core 0 */ \ | |
134 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \ | |
135 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \ | |
136 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \ | |
137 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \ | |
138 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \ | |
139 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \ | |
140 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \ | |
141 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \ | |
142 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \ | |
143 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \ | |
144 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \ | |
145 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \ | |
146 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \ | |
147 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \ | |
148 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \ | |
149 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \ | |
150 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \ | |
151 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \ | |
152 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \ | |
153 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \ | |
154 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \ | |
155 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \ | |
156 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \ | |
157 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \ | |
158 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \ | |
159 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \ | |
160 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \ | |
161 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \ | |
162 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \ | |
163 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \ | |
164 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \ | |
165 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \ | |
166 | } \ | |
d7b26d58 DE |
167 | } |
168 | ||
169 | /* | |
170 | * Definitions for initial stack pointer and data area (in data cache) | |
171 | */ | |
172 | /* use on chip memory (OCM) for temperary stack until sdram is tested */ | |
173 | #define CONFIG_SYS_TEMP_STACK_OCM 1 | |
174 | ||
175 | /* On Chip Memory location */ | |
176 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 | |
177 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 | |
178 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ | |
553f0982 | 179 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ |
d7b26d58 | 180 | |
25ddd1fb | 181 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
d7b26d58 DE |
182 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
183 | ||
184 | /* | |
185 | * External Bus Controller (EBC) Setup | |
186 | */ | |
187 | ||
188 | /* Memory Bank 0 (NOR-FLASH) initialization */ | |
189 | #define CONFIG_SYS_EBC_PB0AP 0x92015480 | |
190 | #define CONFIG_SYS_EBC_PB0CR 0xFC0DA000 /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */ | |
191 | ||
192 | /* Memory Bank 1 (NVRAM) initialization */ | |
193 | #define CONFIG_SYS_EBC_PB1AP 0x92015480 | |
194 | #define CONFIG_SYS_EBC_PB1CR 0xFB85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */ | |
195 | ||
196 | /* Memory Bank 2 (FPGA) initialization */ | |
6e9e6c36 | 197 | #define CONFIG_SYS_FPGA0_BASE 0x7f100000 |
d7b26d58 DE |
198 | #define CONFIG_SYS_EBC_PB2AP 0x92015480 |
199 | #define CONFIG_SYS_EBC_PB2CR 0x7f11a000 /* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */ | |
200 | ||
6e9e6c36 DE |
201 | #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE |
202 | ||
203 | #define CONFIG_SYS_FPGA_COUNT 1 | |
204 | ||
aba27acf DE |
205 | #define CONFIG_SYS_FPGA_PTR \ |
206 | { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE } | |
207 | ||
208 | #define CONFIG_SYS_FPGA_COMMON | |
209 | ||
d7b26d58 | 210 | /* Memory Bank 3 (Latches) initialization */ |
6e9e6c36 | 211 | #define CONFIG_SYS_LATCH_BASE 0x7f200000 |
d7b26d58 DE |
212 | #define CONFIG_SYS_EBC_PB3AP 0x92015480 |
213 | #define CONFIG_SYS_EBC_PB3CR 0x7f21a000 /* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */ | |
214 | ||
6e9e6c36 DE |
215 | #define CONFIG_SYS_LATCH0_RESET 0xffff |
216 | #define CONFIG_SYS_LATCH0_BOOT 0xffff | |
217 | #define CONFIG_SYS_LATCH1_RESET 0xffbf | |
218 | #define CONFIG_SYS_LATCH1_BOOT 0xffff | |
219 | ||
d7b26d58 | 220 | #endif /* __CONFIG_H */ |