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d7b26d58 DE |
1 | /* |
2 | * (C) Copyright 2007-2008 | |
3 | * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de | |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
d7b26d58 DE |
6 | */ |
7 | ||
8 | #ifndef __CONFIG_H | |
9 | #define __CONFIG_H | |
10 | ||
11 | ||
12 | #define CONFIG_405EP 1 /* this is a PPC405 CPU */ | |
d7b26d58 DE |
13 | #define CONFIG_NEO 1 /* on a Neo board */ |
14 | ||
2ae18241 WD |
15 | #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 |
16 | ||
d7b26d58 DE |
17 | /* |
18 | * Include common defines/options for all AMCC eval boards | |
19 | */ | |
20 | #define CONFIG_HOSTNAME neo | |
28437154 | 21 | #define CONFIG_IDENT_STRING " neo 0.02" |
d7b26d58 DE |
22 | #include "amcc-common.h" |
23 | ||
6e9e6c36 DE |
24 | #define CONFIG_BOARD_EARLY_INIT_F |
25 | #define CONFIG_BOARD_EARLY_INIT_R | |
26 | #define CONFIG_MISC_INIT_R | |
27 | #define CONFIG_LAST_STAGE_INIT | |
d9f923ff | 28 | #define CONFIG_SYS_GENERIC_BOARD |
d7b26d58 DE |
29 | |
30 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ | |
31 | ||
32 | /* | |
33 | * Configure PLL | |
34 | */ | |
35 | #define PLLMR0_DEFAULT PLLMR0_266_133_66_33 | |
36 | #define PLLMR1_DEFAULT PLLMR1_266_133_66_33 | |
37 | ||
38 | /* new uImage format support */ | |
39 | #define CONFIG_FIT | |
40 | #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ | |
9a4f479b | 41 | #define CONFIG_FIT_DISABLE_SHA256 |
d7b26d58 DE |
42 | |
43 | #define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */ | |
44 | ||
45 | /* | |
46 | * Default environment variables | |
47 | */ | |
48 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
49 | CONFIG_AMCC_DEF_ENV \ | |
50 | CONFIG_AMCC_DEF_ENV_POWERPC \ | |
51 | CONFIG_AMCC_DEF_ENV_NOR_UPD \ | |
52 | "kernel_addr=fc000000\0" \ | |
53 | "fdt_addr=fc1e0000\0" \ | |
54 | "ramdisk_addr=fc200000\0" \ | |
55 | "" | |
56 | ||
57 | #define CONFIG_PHY_ADDR 4 /* PHY address */ | |
58 | #define CONFIG_HAS_ETH0 | |
59 | #define CONFIG_HAS_ETH1 | |
60 | #define CONFIG_PHY1_ADDR 0xc /* EMAC1 PHY address */ | |
61 | #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ | |
62 | ||
63 | /* | |
64 | * Commands additional to the ones defined in amcc-common.h | |
65 | */ | |
d7b26d58 | 66 | #define CONFIG_CMD_DTT |
4fb9b41b DE |
67 | #undef CONFIG_CMD_DHCP |
68 | #undef CONFIG_CMD_DIAG | |
d7b26d58 | 69 | #undef CONFIG_CMD_EEPROM |
4fb9b41b DE |
70 | #undef CONFIG_CMD_ELF |
71 | #undef CONFIG_CMD_I2C | |
72 | #undef CONFIG_CMD_IRQ | |
d7b26d58 DE |
73 | |
74 | /* | |
75 | * SDRAM configuration (please see cpu/ppc/sdram.[ch]) | |
76 | */ | |
77 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ | |
78 | ||
79 | /* SDRAM timings used in datasheet */ | |
80 | #define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */ | |
81 | #define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */ | |
82 | #define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */ | |
83 | #define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */ | |
84 | #define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */ | |
85 | ||
86 | /* | |
87 | * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1. | |
88 | * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31. | |
89 | * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value. | |
90 | * The Linux BASE_BAUD define should match this configuration. | |
91 | * baseBaud = cpuClock/(uartDivisor*16) | |
92 | * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, | |
93 | * set Linux BASE_BAUD to 403200. | |
94 | */ | |
550650dd SR |
95 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
96 | #define CONFIG_SYS_NS16550 | |
97 | #define CONFIG_SYS_NS16550_SERIAL | |
98 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
99 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
100 | ||
d7b26d58 DE |
101 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ |
102 | #undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ | |
103 | #define CONFIG_SYS_BASE_BAUD 691200 | |
104 | ||
105 | /* | |
106 | * I2C stuff | |
107 | */ | |
880540de | 108 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 |
d7b26d58 DE |
109 | |
110 | /* RTC */ | |
111 | #define CONFIG_RTC_DS1337 | |
112 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
113 | ||
114 | /* Temp sensor/hwmon/dtt */ | |
115 | #define CONFIG_DTT_LM63 1 /* National LM63 */ | |
116 | #define CONFIG_DTT_SENSORS { 0 } /* Sensor addresses */ | |
117 | #define CONFIG_DTT_PWM_LOOKUPTABLE \ | |
118 | { { 40, 10 }, { 50, 20 }, { 60, 40 } } | |
119 | #define CONFIG_DTT_TACH_LIMIT 0xa10 | |
120 | ||
121 | /* | |
122 | * FLASH organization | |
123 | */ | |
124 | #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ | |
125 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ | |
126 | ||
127 | #define CONFIG_SYS_FLASH_BASE 0xFC000000 | |
128 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
129 | ||
130 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
131 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ | |
132 | ||
133 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
134 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
135 | ||
136 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ | |
d7b26d58 DE |
137 | |
138 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ | |
139 | #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ | |
140 | ||
141 | #ifdef CONFIG_ENV_IS_IN_FLASH | |
142 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ | |
6e9e6c36 | 143 | #define CONFIG_ENV_ADDR 0xFFF00000 |
00251261 | 144 | #define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ |
d7b26d58 DE |
145 | |
146 | /* Address and size of Redundant Environment Sector */ | |
6e9e6c36 | 147 | #define CONFIG_ENV_ADDR_REDUND 0xFFF20000 |
d7b26d58 DE |
148 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
149 | #endif | |
150 | ||
151 | /* | |
152 | * PPC405 GPIO Configuration | |
153 | */ | |
6e9e6c36 DE |
154 | #define CONFIG_SYS_4xx_GPIO_TABLE { \ |
155 | { \ | |
156 | /* GPIO Core 0 */ \ | |
157 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \ | |
158 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \ | |
159 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \ | |
160 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \ | |
161 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \ | |
162 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \ | |
163 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \ | |
164 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \ | |
165 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \ | |
166 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \ | |
167 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \ | |
168 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \ | |
169 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \ | |
170 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \ | |
171 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \ | |
172 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \ | |
173 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \ | |
174 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \ | |
175 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \ | |
176 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \ | |
177 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \ | |
178 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \ | |
179 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \ | |
180 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \ | |
181 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \ | |
182 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \ | |
183 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \ | |
184 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \ | |
185 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \ | |
186 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \ | |
187 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \ | |
188 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \ | |
189 | } \ | |
d7b26d58 DE |
190 | } |
191 | ||
192 | /* | |
193 | * Definitions for initial stack pointer and data area (in data cache) | |
194 | */ | |
195 | /* use on chip memory (OCM) for temperary stack until sdram is tested */ | |
196 | #define CONFIG_SYS_TEMP_STACK_OCM 1 | |
197 | ||
198 | /* On Chip Memory location */ | |
199 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 | |
200 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 | |
201 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ | |
553f0982 | 202 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ |
d7b26d58 | 203 | |
25ddd1fb | 204 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
d7b26d58 DE |
205 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
206 | ||
207 | /* | |
208 | * External Bus Controller (EBC) Setup | |
209 | */ | |
210 | ||
211 | /* Memory Bank 0 (NOR-FLASH) initialization */ | |
212 | #define CONFIG_SYS_EBC_PB0AP 0x92015480 | |
213 | #define CONFIG_SYS_EBC_PB0CR 0xFC0DA000 /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */ | |
214 | ||
215 | /* Memory Bank 1 (NVRAM) initialization */ | |
216 | #define CONFIG_SYS_EBC_PB1AP 0x92015480 | |
217 | #define CONFIG_SYS_EBC_PB1CR 0xFB85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */ | |
218 | ||
219 | /* Memory Bank 2 (FPGA) initialization */ | |
6e9e6c36 | 220 | #define CONFIG_SYS_FPGA0_BASE 0x7f100000 |
d7b26d58 DE |
221 | #define CONFIG_SYS_EBC_PB2AP 0x92015480 |
222 | #define CONFIG_SYS_EBC_PB2CR 0x7f11a000 /* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */ | |
223 | ||
6e9e6c36 DE |
224 | #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE |
225 | ||
226 | #define CONFIG_SYS_FPGA_COUNT 1 | |
227 | ||
aba27acf DE |
228 | #define CONFIG_SYS_FPGA_PTR \ |
229 | { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE } | |
230 | ||
231 | #define CONFIG_SYS_FPGA_COMMON | |
232 | ||
d7b26d58 | 233 | /* Memory Bank 3 (Latches) initialization */ |
6e9e6c36 | 234 | #define CONFIG_SYS_LATCH_BASE 0x7f200000 |
d7b26d58 DE |
235 | #define CONFIG_SYS_EBC_PB3AP 0x92015480 |
236 | #define CONFIG_SYS_EBC_PB3CR 0x7f21a000 /* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */ | |
237 | ||
6e9e6c36 DE |
238 | #define CONFIG_SYS_LATCH0_RESET 0xffff |
239 | #define CONFIG_SYS_LATCH0_BOOT 0xffff | |
240 | #define CONFIG_SYS_LATCH1_RESET 0xffbf | |
241 | #define CONFIG_SYS_LATCH1_BOOT 0xffff | |
242 | ||
d7b26d58 | 243 | #endif /* __CONFIG_H */ |