[people/ms/u-boot.git] / include / configs / netstar.h

/*
 * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl
 *
 * Configuation settings for the TI OMAP NetStar board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <configs/omap1510.h>

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_ARM925T	1		/* This is an arm925t CPU */
#define CONFIG_OMAP	1		/* in a TI OMAP core */
#define CONFIG_OMAP1510 1		/* which is in a 5910 */

/* Input clock of PLL */
#define CONFIG_SYS_CLK_FREQ	150000000	/* 150MHz input clock */
#define CONFIG_XTAL_FREQ	12000000

#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */

#define CONFIG_MISC_INIT_R		/* There is nothing to really init */
#define BOARD_LATE_INIT			/* but we flash the LEDs here */

#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_INITRD_TAG		1

#define CFG_DEVICE_NULLDEV		1	/* enable null device */
#define CONFIG_SILENT_CONSOLE		1	/* enable silent startup */

/*
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
#define PHYS_SDRAM_1		0x10000000	/* SDRAM Bank #1 */
#define PHYS_FLASH_1		0x00000000	/* Flash Bank #1 */

/*
 * FLASH organization
 */
#define CFG_FLASH_BASE		PHYS_FLASH_1
#define CFG_MAX_FLASH_BANKS	1
#if (PHYS_SDRAM_1_SIZE == SZ_32M)
/*#if 1*/
#define CFG_FLASH_CFI			/* Flash is CFI conformant */
#define CFG_FLASH_CFI_DRIVER		/* Use the common driver */
#define CFG_FLASH_EMPTY_INFO
#define CFG_MAX_FLASH_SECT	128
#else
#define PHYS_FLASH_1_SIZE	SZ_1M
#define CFG_MAX_FLASH_SECT	19
#define CFG_FLASH_ERASE_TOUT	(5*CFG_HZ) /* in ticks */
#define CFG_FLASH_WRITE_TOUT	(5*CFG_HZ)
#endif

#define CFG_MONITOR_BASE	PHYS_FLASH_1
#define CFG_MONITOR_LEN		SZ_256K

/*
 * Environment settings
 */
#define CFG_ENV_IS_IN_FLASH
#define ENV_IS_SOLITARY
#define CFG_ENV_ADDR		0x4000
#define CFG_ENV_SIZE		SZ_8K
#define CFG_ENV_SECT_SIZE	SZ_8K
#define CFG_ENV_ADDR_REDUND	0x6000
#define CFG_ENV_SIZE_REDUND	CFG_ENV_SIZE
#define CONFIG_ENV_OVERWRITE

/*
 * Size of malloc() pool
 */
#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
/* XXX #define CFG_MALLOC_LEN		(SZ_64K - CFG_GBL_DATA_SIZE)*/
#define CFG_MALLOC_LEN		SZ_4M

/*
 * The stack size is set up in start.S using the settings below
 */
/* XXX #define CONFIG_STACKSIZE	SZ_8K	/XXX* regular stack */
#define CONFIG_STACKSIZE	SZ_1M	/* regular stack */

/*
 * Hardware drivers
 */
#define CONFIG_DRIVER_SMC91111
#define CONFIG_SMC91111_BASE	0x04000300

/*
 * NS16550 Configuration
 */
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE	(-4)
#define CFG_NS16550_CLK		(CONFIG_XTAL_FREQ)	/* can be 12M/32Khz or 48Mhz  */
#define CFG_NS16550_COM1	OMAP1510_UART1_BASE	/* uart1 */

#define CONFIG_CONS_INDEX	1
#define CONFIG_BAUDRATE		115200
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*#define CONFIG_SKIP_RELOCATE_UBOOT*/
/*#define CONFIG_SKIP_LOWLEVEL_INIT */

/*
 * NAND flash
 */
#define CFG_MAX_NAND_DEVICE	1
#define NAND_MAX_CHIPS		1
#define CFG_NAND_BASE	0x04000000 + (2 << 23)

/*
 * JFFS2 partitions (mtdparts command line support)
 */
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT		"nor0=omapflash.0,nand0=omapnand.0"
#define MTDPARTS_DEFAULT	"mtdparts=omapflash.0:8k@16k(env),8k(r_env),448k@576k(u-boot);omapnand.0:48M(rootfs0),48M(rootfs1),-(data)"


/*
 * Command line configuration.
 */

#define CONFIG_CMD_BDI
#define CONFIG_CMD_BOOTD
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_RUN


#define CONFIG_JFFS2_NAND	1	/* jffs2 on nand support */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH

#define CONFIG_LOOPW

#define CONFIG_BOOTDELAY	3
#define CONFIG_ZERO_BOOTDELAY_CHECK	/* allow to break in always */
#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs*/
#define CFG_AUTOLOAD		"n"		/* No autoload */
#define CONFIG_BOOTCOMMAND	"run nboot"
#define CONFIG_PREBOOT		"run setup"
#define	CONFIG_EXTRA_ENV_SETTINGS				\
	"setup=setenv bootargs console=ttyS0,$baudrate "	\
		"$mtdparts\0"					\
	"ospart=0\0"						\
	"setpart="						\
	"if test -n $swapos; then "				\
		"if test $ospart -eq 0; then chpart nand0,1; else chpart nand0,0; fi; "\
		"setenv swapos; saveenv; "			\
	"else "							\
		"chpart nand0,$ospart; "			\
	"fi\0"							\
	"nfsargs=setenv bootargs $bootargs "			\
		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \
		"nfsroot=$rootpath root=/dev/nfs\0"		\
	"flashargs=run setpart;setenv bootargs $bootargs "	\
		"root=/dev/mtdblock$partition ro "		\
		"rootfstype=jffs2\0"				\
	"initrdargs=setenv bootargs $bootargs "			\
		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \
	"iboot=bootp;run initrdargs;tftp;bootm\0"		\
	"fboot=run flashargs;fsload /boot/uImage;bootm\0"	\
	"nboot=bootp;run nfsargs;tftp;bootm\0"

#if 0	/* feel free to disable for development */
#define	CONFIG_AUTOBOOT_KEYED		/* Enable password protection	*/
#define CONFIG_AUTOBOOT_PROMPT	"\nNetStar PBX - boot in %d sec...\n"
#define CONFIG_AUTOBOOT_DELAY_STR	"R"	/* 1st "password"	*/
#define CONFIG_BOOT_RETRY_TIME	30
#endif

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP				/* undef to save memory		*/
#define CFG_PROMPT		"# "		/* Monitor Command Prompt	*/
#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS		16		/* max number of command args	*/
#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2	"> "
#define CONFIG_AUTO_COMPLETE

#define CFG_MEMTEST_START	PHYS_SDRAM_1
#define CFG_MEMTEST_END		PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE

#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */

#define CFG_LOAD_ADDR		PHYS_SDRAM_1 + 0x400000	/* default load address */

/* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1.
 * This time is further subdivided by a local divisor.
 */
#define CFG_TIMERBASE		OMAP1510_TIMER1_BASE
#define CFG_PVT			7		/* 2^(pvt+1), divide by 256 */
#define CFG_HZ			((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))

#define OMAP5910_DPLL_DIV	1
#define OMAP5910_DPLL_MUL	((CONFIG_SYS_CLK_FREQ * \
				 (1 << OMAP5910_DPLL_DIV)) / CONFIG_XTAL_FREQ)

#define OMAP5910_ARM_PER_DIV	2	/* CKL/4 */
#define OMAP5910_LCD_DIV	2	/* CKL/4 */
#define OMAP5910_ARM_DIV	0	/* CKL/1 */
#define OMAP5910_DSP_DIV	0	/* CKL/1 */
#define OMAP5910_TC_DIV		1	/* CKL/2 */
#define OMAP5910_DSP_MMU_DIV	1	/* CKL/2 */
#define OMAP5910_ARM_TIM_SEL	1	/* CKL used for MPU timers */

#define OMAP5910_ARM_EN_CLK	0x03d6	/* 0000 0011 1101 0110b  Clock Enable */
#define OMAP5910_ARM_CKCTL	((OMAP5910_ARM_PER_DIV)  |	\
				 (OMAP5910_LCD_DIV << 2) |	\
				 (OMAP5910_ARM_DIV << 4) |	\
				 (OMAP5910_DSP_DIV << 6) |	\
				 (OMAP5910_TC_DIV << 8) |	\
				 (OMAP5910_DSP_MMU_DIV << 10) |	\
				 (OMAP5910_ARM_TIM_SEL << 12))

#endif	/* __CONFIG_H */
Commit	Line	Data
ac7eb8a3 WD	1	/*
	2	* (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl
	3	*
	4	* Configuation settings for the TI OMAP NetStar board.
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#ifndef __CONFIG_H
	26	#define __CONFIG_H
	27
	28	#include <configs/omap1510.h>
	29
	30	/*
	31	* High Level Configuration Options
	32	* (easy to change)
	33	*/
	34	#define CONFIG_ARM925T 1 /* This is an arm925t CPU */
	35	#define CONFIG_OMAP 1 /* in a TI OMAP core */
	36	#define CONFIG_OMAP1510 1 /* which is in a 5910 */
	37
	38	/* Input clock of PLL */
	39	#define CONFIG_SYS_CLK_FREQ 150000000 /* 150MHz input clock */
	40	#define CONFIG_XTAL_FREQ 12000000
	41
	42	#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
	43
	44	#define CONFIG_MISC_INIT_R /* There is nothing to really init */
	45	#define BOARD_LATE_INIT /* but we flash the LEDs here */
	46
	47	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	48	#define CONFIG_SETUP_MEMORY_TAGS 1
	49	#define CONFIG_INITRD_TAG 1
	50
	51	#define CFG_DEVICE_NULLDEV 1 /* enable null device */
	52	#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */
	53
	54	/*
	55	* Physical Memory Map
	56	*/
	57	#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
	58	#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
	59	#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
	60
	61	/*
	62	* FLASH organization
	63	*/
	64	#define CFG_FLASH_BASE PHYS_FLASH_1
65	#define CFG_MAX_FLASH_BANKS 1
66	#if (PHYS_SDRAM_1_SIZE == SZ_32M)
67	/#if 1/
68	#define CFG_FLASH_CFI /* Flash is CFI conformant */
69	#define CFG_FLASH_CFI_DRIVER /* Use the common driver */
70	#define CFG_FLASH_EMPTY_INFO
71	#define CFG_MAX_FLASH_SECT 128
72	#else
73	#define PHYS_FLASH_1_SIZE SZ_1M
74	#define CFG_MAX_FLASH_SECT 19
75	#define CFG_FLASH_ERASE_TOUT (5CFG_HZ) / in ticks */
76	#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ)
77	#endif
78
79	#define CFG_MONITOR_BASE PHYS_FLASH_1
80	#define CFG_MONITOR_LEN SZ_256K
81
82	/*
83	* Environment settings
84	*/
85	#define CFG_ENV_IS_IN_FLASH
86	#define ENV_IS_SOLITARY
87	#define CFG_ENV_ADDR 0x4000
88	#define CFG_ENV_SIZE SZ_8K
89	#define CFG_ENV_SECT_SIZE SZ_8K
90	#define CFG_ENV_ADDR_REDUND 0x6000
91	#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
92	#define CONFIG_ENV_OVERWRITE
93
94	/*
95	* Size of malloc() pool
96	*/
97	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
98	/* XXX #define CFG_MALLOC_LEN (SZ_64K - CFG_GBL_DATA_SIZE)*/
99	#define CFG_MALLOC_LEN SZ_4M
100
101	/*
102	* The stack size is set up in start.S using the settings below
103	*/
104	/* XXX #define CONFIG_STACKSIZE SZ_8K /XXX* regular stack */
105	#define CONFIG_STACKSIZE SZ_1M /* regular stack */
106
107	/*
108	* Hardware drivers
109	*/
110	#define CONFIG_DRIVER_SMC91111
111	#define CONFIG_SMC91111_BASE 0x04000300
112
113	/*
114	* NS16550 Configuration
115	*/
116	#define CFG_NS16550
117	#define CFG_NS16550_SERIAL
118	#define CFG_NS16550_REG_SIZE (-4)
119	#define CFG_NS16550_CLK (CONFIG_XTAL_FREQ) /* can be 12M/32Khz or 48Mhz */
120	#define CFG_NS16550_COM1 OMAP1510_UART1_BASE /* uart1 */
121
122	#define CONFIG_CONS_INDEX 1
123	#define CONFIG_BAUDRATE 115200
124	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
125
126	/#define CONFIG_SKIP_RELOCATE_UBOOT/
127	/#define CONFIG_SKIP_LOWLEVEL_INIT /
128
129	/*
130	* NAND flash
131	*/
132	#define CFG_MAX_NAND_DEVICE 1
addb2e16	133	#define NAND_MAX_CHIPS 1
ac7eb8a3	134	#define CFG_NAND_BASE 0x04000000 + (2 << 23)
ac7eb8a3 WD	135
	136	/*
	137	* JFFS2 partitions (mtdparts command line support)
	138	*/
	139	#define CONFIG_JFFS2_CMDLINE
	140	#define MTDIDS_DEFAULT "nor0=omapflash.0,nand0=omapnand.0"
	141	#define MTDPARTS_DEFAULT "mtdparts=omapflash.0:8k@16k(env),8k(r_env),448k@576k(u-boot);omapnand.0:48M(rootfs0),48M(rootfs1),-(data)"
	142
ac7eb8a3	143
929a2bfd JL	144	/*
	145	* Command line configuration.
	146	*/
	147
	148	#define CONFIG_CMD_BDI
	149	#define CONFIG_CMD_BOOTD
	150	#define CONFIG_CMD_DHCP
	151	#define CONFIG_CMD_ENV
	152	#define CONFIG_CMD_FLASH
	153	#define CONFIG_CMD_IMI
	154	#define CONFIG_CMD_JFFS2
	155	#define CONFIG_CMD_LOADB
	156	#define CONFIG_CMD_MEMORY
	157	#define CONFIG_CMD_NAND
	158	#define CONFIG_CMD_NET
	159	#define CONFIG_CMD_PING
	160	#define CONFIG_CMD_RUN
	161
ac7eb8a3 WD	162
ac7eb8a3 WD	163	#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
ac7eb8a3	164
d3b8c1a7 JL	165	/*
	166	* BOOTP options
	167	*/
	168	#define CONFIG_BOOTP_SUBNETMASK
	169	#define CONFIG_BOOTP_GATEWAY
	170	#define CONFIG_BOOTP_HOSTNAME
	171	#define CONFIG_BOOTP_BOOTPATH
	172
ac7eb8a3 WD	173	#define CONFIG_LOOPW
ac7eb8a3 WD	174
ac7eb8a3 WD	175	#define CONFIG_BOOTDELAY 3
	176	#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow to break in always */
	177	#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
	178	#define CFG_AUTOLOAD "n" /* No autoload */
	179	#define CONFIG_BOOTCOMMAND "run nboot"
	180	#define CONFIG_PREBOOT "run setup"
	181	#define CONFIG_EXTRA_ENV_SETTINGS \
	182	"setup=setenv bootargs console=ttyS0,$baudrate " \
	183	"$mtdparts\0" \
	184	"ospart=0\0" \
	185	"setpart=" \
	186	"if test -n $swapos; then " \
	187	"if test $ospart -eq 0; then chpart nand0,1; else chpart nand0,0; fi; "\
	188	"setenv swapos; saveenv; " \
	189	"else " \
	190	"chpart nand0,$ospart; " \
	191	"fi\0" \
	192	"nfsargs=setenv bootargs $bootargs " \
	193	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \
	194	"nfsroot=$rootpath root=/dev/nfs\0" \
	195	"flashargs=run setpart;setenv bootargs $bootargs " \
	196	"root=/dev/mtdblock$partition ro " \
	197	"rootfstype=jffs2\0" \
	198	"initrdargs=setenv bootargs $bootargs " \
	199	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \
	200	"iboot=bootp;run initrdargs;tftp;bootm\0" \
	201	"fboot=run flashargs;fsload /boot/uImage;bootm\0" \
	202	"nboot=bootp;run nfsargs;tftp;bootm\0"
	203
	204	#if 0 /* feel free to disable for development */
	205	#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */
	206	#define CONFIG_AUTOBOOT_PROMPT "\nNetStar PBX - boot in %d sec...\n"
	207	#define CONFIG_AUTOBOOT_DELAY_STR "R" /* 1st "password" */
	208	#define CONFIG_BOOT_RETRY_TIME 30
	209	#endif
	210
	211	/*
	212	* Miscellaneous configurable options
	213	*/
	214	#define CFG_LONGHELP /* undef to save memory */
	215	#define CFG_PROMPT "# " /* Monitor Command Prompt */
	216	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	217	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	218	#define CFG_MAXARGS 16 /* max number of command args */
	219	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	220
	221	#define CFG_HUSH_PARSER
	222	#define CFG_PROMPT_HUSH_PS2 "> "
	223	#define CONFIG_AUTO_COMPLETE
	224
	225	#define CFG_MEMTEST_START PHYS_SDRAM_1
	226	#define CFG_MEMTEST_END PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE
	227
	228	#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
	229
	230	#define CFG_LOAD_ADDR PHYS_SDRAM_1 + 0x400000 /* default load address */
	231
	232	/* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1.
	233	* This time is further subdivided by a local divisor.
	234	*/
	235	#define CFG_TIMERBASE OMAP1510_TIMER1_BASE
	236	#define CFG_PVT 7 /* 2^(pvt+1), divide by 256 */
	237	#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
	238
239	#define OMAP5910_DPLL_DIV 1
240	#define OMAP5910_DPLL_MUL ((CONFIG_SYS_CLK_FREQ * \
241	(1 << OMAP5910_DPLL_DIV)) / CONFIG_XTAL_FREQ)
242
243	#define OMAP5910_ARM_PER_DIV 2 /* CKL/4 */
244	#define OMAP5910_LCD_DIV 2 /* CKL/4 */
245	#define OMAP5910_ARM_DIV 0 /* CKL/1 */
246	#define OMAP5910_DSP_DIV 0 /* CKL/1 */
247	#define OMAP5910_TC_DIV 1 /* CKL/2 */
248	#define OMAP5910_DSP_MMU_DIV 1 /* CKL/2 */
249	#define OMAP5910_ARM_TIM_SEL 1 /* CKL used for MPU timers */
250
251	#define OMAP5910_ARM_EN_CLK 0x03d6 /* 0000 0011 1101 0110b Clock Enable */
252	#define OMAP5910_ARM_CKCTL ((OMAP5910_ARM_PER_DIV) \| \
253	(OMAP5910_LCD_DIV << 2) \| \
254	(OMAP5910_ARM_DIV << 4) \| \
255	(OMAP5910_DSP_DIV << 6) \| \
256	(OMAP5910_TC_DIV << 8) \| \
257	(OMAP5910_DSP_MMU_DIV << 10) \| \
258	(OMAP5910_ARM_TIM_SEL << 12))
259
260	#endif /* __CONFIG_H */