[people/ms/u-boot.git] / include / configs / ns9750dev.h

/*
 * Copyright (C) 2004 by FS Forth-Systeme GmbH.
 * All rights reserved.
 * Markus Pietrek <mpietrek@fsforth.de>
 *
 * Configuation settings for the NetSilicon NS9750 DevBoard
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
#define	CONFIG_NS9750		1	/* in an NetSilicon NS9750 SoC     */
#define CONFIG_NS9750DEV	1	/* on an NetSilicon NS9750 DevBoard  */

/* input clock of PLL */
#define CONFIG_SYS_CLK_FREQ	324403200 /* Don't use PLL. SW11-4 off */

#define CPU_CLK_FREQ		(CONFIG_SYS_CLK_FREQ/2)
#define AHB_CLK_FREQ		(CONFIG_SYS_CLK_FREQ/4)
#define BBUS_CLK_FREQ		(CONFIG_SYS_CLK_FREQ/8)

#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
/*@TODO #define CONFIG_STATUS_LED*/
#define CONFIG_USE_IRQ

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)

/*
 * Hardware drivers
 */
#define CONFIG_NS9750_UART		1	/* use on-chip UART */

/*
 * select serial console configuration
 */
#define CONFIG_CONS_INDEX          1		/* Port B */

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_BAUDRATE		38400


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */

#define CONFIG_CMD_BDI
#define CONFIG_CMD_CONSOLE
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_LOADS
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_PING


#define CONFIG_BOOTDELAY	3
/*#define CONFIG_BOOTARGS	"root=ramfs devfs=mount console=ttySA0,9600" */

#define CONFIG_ETHADDR		00:04:f3:ff:ff:fb /*@TODO unset */
#define CONFIG_NETMASK          255.255.255.0
#define CONFIG_IPADDR		192.168.42.30
#define CONFIG_SERVERIP		192.168.42.1

/*#define CONFIG_BOOTFILE	"elinos-lart" */
/*#define CONFIG_BOOTCOMMAND	"tftp; bootm" */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port */
/* what's this ? it's not used anywhere */
#define CONFIG_KGDB_SER_INDEX	1		/* which serial port to use */
#endif

/*
 * Miscellaneous configurable options
 */
#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
#define	CONFIG_SYS_PROMPT		"NS9750DEV # "	/* Monitor Command Prompt	*/
#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x00780000	/* 7,5 MB in DRAM	*/ /* @TODO */

#define	CONFIG_SYS_LOAD_ADDR		0x00600000	/* default load address	*/ /* @TODO */

#define	CONFIG_SYS_HZ			(CPU_CLK_FREQ/64)

#define NS9750_ETH_PHY_ADDRESS	(0x0000)

/*-----------------------------------------------------------------------
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
#endif

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
/* TODO */
#define CONFIG_NR_DRAM_BANKS	2	   /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1		0x00000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE	0x00800000 /* 8 MB */
#define PHYS_SDRAM_2		0x10000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_2_SIZE	0x00800000 /* 8 MB */

#define PHYS_FLASH_1		0x50000000 /* Flash Bank #1 */

#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */

/* @TODO*/
#define CONFIG_AMD_LV400	1	/* uncomment this if you have a LV400 flash */
#if 0
#define CONFIG_AMD_LV800	1	/* uncomment this if you have a LV800 flash */
#endif

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#ifdef CONFIG_AMD_LV800
#define PHYS_FLASH_SIZE		0x00100000 /* 1MB */
#define CONFIG_SYS_MAX_FLASH_SECT	(19)	/* max number of sectors on one chip */
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x0F0000) /* addr of environment */
#endif
#ifdef CONFIG_AMD_LV400
#define PHYS_FLASH_SIZE		0x00080000 /* 512KB */
#define CONFIG_SYS_MAX_FLASH_SECT	(11)	/* max number of sectors on one chip */
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x070000) /* addr of environment */
#endif

/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
#define CONFIG_SYS_FLASH_WRITE_TOUT	(5*CONFIG_SYS_HZ) /* Timeout for Flash Write */

/* @TODO */
/*#define	CONFIG_ENV_IS_IN_FLASH	1*/
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE		0x10000	/* Total Size of Environment Sector */

#ifdef CONFIG_STATUS_LED

extern void __led_init(led_id_t mask, int state);
extern void __led_toggle(led_id_t mask);
extern void __led_set(led_id_t mask, int state);

#endif /* CONFIG_STATUS_LED */

#endif	/* __CONFIG_H */
Commit	Line	Data
80885a9d WD	1	/*
	2	* Copyright (C) 2004 by FS Forth-Systeme GmbH.
	3	* All rights reserved.
	4	* Markus Pietrek <mpietrek@fsforth.de>
	5	*
	6	* Configuation settings for the NetSilicon NS9750 DevBoard
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	#ifndef __CONFIG_H
	28	#define __CONFIG_H
	29
80885a9d WD	30	/*
	31	* High Level Configuration Options
	32	* (easy to change)
	33	*/
	34	#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
	35	#define CONFIG_NS9750 1 /* in an NetSilicon NS9750 SoC */
	36	#define CONFIG_NS9750DEV 1 /* on an NetSilicon NS9750 DevBoard */
	37
	38	/* input clock of PLL */
	39	#define CONFIG_SYS_CLK_FREQ 324403200 /* Don't use PLL. SW11-4 off */
	40
	41	#define CPU_CLK_FREQ (CONFIG_SYS_CLK_FREQ/2)
	42	#define AHB_CLK_FREQ (CONFIG_SYS_CLK_FREQ/4)
	43	#define BBUS_CLK_FREQ (CONFIG_SYS_CLK_FREQ/8)
	44
	45	#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
	46	/@TODO #define CONFIG_STATUS_LED/
	47	#define CONFIG_USE_IRQ
	48
	49	/*
	50	* Size of malloc() pool
	51	*/
6d0f6bcf	52	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
80885a9d WD	53
	54	/*
	55	* Hardware drivers
	56	*/
1a6ffbfa	57	#define CONFIG_NS9750_UART 1 /* use on-chip UART */
80885a9d WD	58
	59	/*
	60	* select serial console configuration
	61	*/
53677ef1	62	#define CONFIG_CONS_INDEX 1 /* Port B */
80885a9d WD	63
	64	/* allow to overwrite serial and ethaddr */
	65	#define CONFIG_ENV_OVERWRITE
	66
	67	#define CONFIG_BAUDRATE 38400
	68
929a2bfd	69
7f5c0157 JL	70	/*
	71	* BOOTP options
	72	*/
	73	#define CONFIG_BOOTP_BOOTFILESIZE
	74	#define CONFIG_BOOTP_BOOTPATH
	75	#define CONFIG_BOOTP_GATEWAY
	76	#define CONFIG_BOOTP_HOSTNAME
	77
	78
929a2bfd JL	79	/*
	80	* Command line configuration.
	81	*/
	82
	83	#define CONFIG_CMD_BDI
	84	#define CONFIG_CMD_CONSOLE
	85	#define CONFIG_CMD_LOADB
	86	#define CONFIG_CMD_LOADS
	87	#define CONFIG_CMD_MEMORY
929a2bfd JL	88	#define CONFIG_CMD_PING
929a2bfd JL	89
80885a9d WD	90
80885a9d WD	91	#define CONFIG_BOOTDELAY 3
53677ef1	92	/#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" /
80885a9d WD	93
	94	#define CONFIG_ETHADDR 00:04:f3:ff:ff:fb /@TODO unset /
	95	#define CONFIG_NETMASK 255.255.255.0
	96	#define CONFIG_IPADDR 192.168.42.30
	97	#define CONFIG_SERVERIP 192.168.42.1
	98
	99	/#define CONFIG_BOOTFILE "elinos-lart" /
	100	/#define CONFIG_BOOTCOMMAND "tftp; bootm" /
	101
929a2bfd	102	#if defined(CONFIG_CMD_KGDB)
80885a9d WD	103	#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
	104	/* what's this ? it's not used anywhere */
	105	#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
	106	#endif
	107
	108	/*
	109	* Miscellaneous configurable options
	110	*/
6d0f6bcf JCPV	111	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	112	#define CONFIG_SYS_PROMPT "NS9750DEV # " /* Monitor Command Prompt */
	113	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	114	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	115	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	116	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
80885a9d	117
6d0f6bcf JCPV	118	#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
6d0f6bcf JCPV	119	#define CONFIG_SYS_MEMTEST_END 0x00780000 /* 7,5 MB in DRAM / / @TODO */
80885a9d	120
6d0f6bcf	121	#define CONFIG_SYS_LOAD_ADDR 0x00600000 /* default load address / / @TODO */
80885a9d	122
6d0f6bcf	123	#define CONFIG_SYS_HZ (CPU_CLK_FREQ/64)
80885a9d	124
80885a9d WD	125	#define NS9750_ETH_PHY_ADDRESS (0x0000)
	126
	127	/*-----------------------------------------------------------------------
	128	* Stack sizes
	129	*
	130	* The stack sizes are set up in start.S using the settings below
	131	*/
	132	#define CONFIG_STACKSIZE (1281024) / regular stack */
	133	#ifdef CONFIG_USE_IRQ
	134	#define CONFIG_STACKSIZE_IRQ (41024) / IRQ stack */
	135	#define CONFIG_STACKSIZE_FIQ (41024) / FIQ stack */
	136	#endif
	137
	138	/*-----------------------------------------------------------------------
	139	* Physical Memory Map
	140	*/
	141	/* TODO */
	142	#define CONFIG_NR_DRAM_BANKS 2 /* we have 1 bank of DRAM */
	143	#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
	144	#define PHYS_SDRAM_1_SIZE 0x00800000 /* 8 MB */
	145	#define PHYS_SDRAM_2 0x10000000 /* SDRAM Bank #1 */
	146	#define PHYS_SDRAM_2_SIZE 0x00800000 /* 8 MB */
	147
	148	#define PHYS_FLASH_1 0x50000000 /* Flash Bank #1 */
	149
6d0f6bcf	150	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
80885a9d WD	151
	152	/*-----------------------------------------------------------------------
	153	* FLASH and environment organization
	154	*/
	155
	156	/* @TODO*/
	157	#define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */
	158	#if 0
	159	#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */
	160	#endif
	161
6d0f6bcf	162	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
80885a9d WD	163	#ifdef CONFIG_AMD_LV800
80885a9d WD	164	#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */
6d0f6bcf JCPV	165	#define CONFIG_SYS_MAX_FLASH_SECT (19) /* max number of sectors on one chip */
6d0f6bcf JCPV	166	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x0F0000) /* addr of environment */
80885a9d WD	167	#endif
	168	#ifdef CONFIG_AMD_LV400
	169	#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */
6d0f6bcf JCPV	170	#define CONFIG_SYS_MAX_FLASH_SECT (11) /* max number of sectors on one chip */
6d0f6bcf JCPV	171	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x070000) /* addr of environment */
80885a9d WD	172	#endif
	173
	174	/* timeout values are in ticks */
6d0f6bcf JCPV	175	#define CONFIG_SYS_FLASH_ERASE_TOUT (5CONFIG_SYS_HZ) / Timeout for Flash Erase */
6d0f6bcf JCPV	176	#define CONFIG_SYS_FLASH_WRITE_TOUT (5CONFIG_SYS_HZ) / Timeout for Flash Write */
80885a9d WD	177
80885a9d WD	178	/* @TODO */
5a1aceb0	179	/#define CONFIG_ENV_IS_IN_FLASH 1/
93f6d725	180	#define CONFIG_ENV_IS_NOWHERE
0e8d1586	181	#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
80885a9d WD	182
	183	#ifdef CONFIG_STATUS_LED
	184
	185	extern void __led_init(led_id_t mask, int state);
	186	extern void __led_toggle(led_id_t mask);
	187	extern void __led_set(led_id_t mask, int state);
	188
	189	#endif /* CONFIG_STATUS_LED */
	190
	191	#endif /* __CONFIG_H */