[people/ms/u-boot.git] / include / configs / o2dnt.h

/*
 * (C) Copyright 2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
#define CONFIG_MPC5200
#define CONFIG_O2DNT		1	/* ... on O2DNT board */

#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */

#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
#define BOOTFLAG_WARM		0x02	/* Software reboot	     */

#define CONFIG_HIGH_BATS	1	/* High BATs supported */

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	5	/* console is on PSC5 */
#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

/*
 * PCI Mapping:
 * 0x40000000 - 0x4fffffff - PCI Memory
 * 0x50000000 - 0x50ffffff - PCI IO Space
 */
#define CONFIG_PCI		1
#define CONFIG_PCI_PNP		1
/* #define CONFIG_PCI_SCAN_SHOW	1 */
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1

#define CONFIG_PCI_MEM_BUS	0x40000000
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x10000000

#define CONFIG_PCI_IO_BUS	0x50000000
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x01000000

#define CFG_XLB_PIPELINING	1

#define CONFIG_NET_MULTI	1
#define CONFIG_EEPRO100
#define CFG_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
#define CONFIG_NS8382X		1

/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION

#define CONFIG_TIMESTAMP	/* Print image info with timestamp */


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_NFS
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_PCI


#if (TEXT_BASE == 0xFF000000)		/* Boot low with 16 MB Flash */
#   define CFG_LOWBOOT		1
#else
#   error "TEXT_BASE must be 0xFF000000"
#endif

/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"flash_nfs=run nfsargs addip;"					\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip;"					\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
	"rootpath=/opt/eldk/ppc_82xx\0"					\
	"bootfile=/tftpboot/MPC5200/uImage\0"				\
	""

#define CONFIG_BOOTCOMMAND	"run flash_self"

#if defined(CONFIG_MPC5200)
/*
 * IPB Bus clocking configuration.
 */
#define CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */

#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
/*
 * PCI Bus clocking configuration
 *
 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
 * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
 *  of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
 */
#define CFG_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */
#endif
#endif

/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#define CFG_I2C_MODULE		1	/* Select I2C module #1 or #2 */

#define CFG_I2C_SPEED		100000 /* 100 kHz */
#define CFG_I2C_SLAVE		0x7F

/*
 * EEPROM configuration:
 *
 * O2DNT board is equiped with Ramtron FRAM device FM24CL16
 * 16 Kib Ferroelectric Nonvolatile serial RAM memory
 * organized as 2048 x 8 bits and addressable as eight I2C devices
 * 0x50 ... 0x57 each 256 bytes in size
 *
 */
#define CFG_I2C_FRAM
#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
#define CFG_I2C_EEPROM_ADDR_LEN		1
#define CFG_EEPROM_PAGE_WRITE_BITS	3
/*
 * There is no write delay with FRAM, write operations are performed at bus
 * speed. Thus, no status polling or write delay is needed.
 */
/*#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	70*/


/*
 * Flash configuration
 */
#define CFG_FLASH_BASE		0xFF000000
#define CFG_FLASH_SIZE		0x01000000
#define CONFIG_ENV_ADDR		(CFG_FLASH_BASE + 0x00040000)

#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */

#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
#define CFG_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
#define CFG_FLASH_PROTECTION		/* "Real" (hardware) sectors protection */

/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_SIZE		0x20000
#define CONFIG_ENV_SECT_SIZE	0x20000
#define CONFIG_ENV_OVERWRITE	1

/*
 * Memory map
 */
#define CFG_MBAR		0xF0000000
#define CFG_SDRAM_BASE		0x00000000
#define CFG_DEFAULT_MBAR	0x80000000

/* Use SRAM until RAM will be available */
#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */


#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

#define CFG_MONITOR_BASE	TEXT_BASE
#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
/*
 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
 */
/* #define CONFIG_FEC_10MBIT 1 */
#define CONFIG_PHY_ADDR		0x00

/*
 * GPIO configuration
 */
/*#define CFG_GPS_PORT_CONFIG	0x10002004 */
#define CFG_GPS_PORT_CONFIG	0x00002006	/* no CAN */

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory	    */
#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */

#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
#define CFG_MAXARGS		16		/* max number of command args	*/
#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x100000	/* default load address */

#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */

#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*
 * Various low-level settings
 */
#if defined(CONFIG_MPC5200)
#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
#define CFG_HID0_FINAL		HID0_ICE
#else
#define CFG_HID0_INIT		0
#define CFG_HID0_FINAL		0
#endif

#define CFG_BOOTCS_START	CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE

#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
/*
 * For 66 MHz PCI clock additional Wait State is needed for CS0 (flash).
 */
#define CFG_BOOTCS_CFG		0x00057801 /* for pci_clk = 66 MHz */
#else
#define CFG_BOOTCS_CFG		0x00047801 /* for pci_clk = 33 MHz */
#endif

#define CFG_CS0_START		CFG_FLASH_BASE
#define CFG_CS0_SIZE		CFG_FLASH_SIZE

#define CFG_CS_BURST		0x00000000
#define CFG_CS_DEADCYCLE	0x33333333

#define CFG_RESET_ADDRESS	0xff000000

#endif /* __CONFIG_H */
Commit	Line	Data
0841565c	1	/*
	2	* (C) Copyright 2005
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#ifndef __CONFIG_H
	25	#define __CONFIG_H
	26
	27	/*
	28	* High Level Configuration Options
	29	* (easy to change)
	30	*/
	31	#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
	32	#define CONFIG_MPC5200
	33	#define CONFIG_O2DNT 1 /* ... on O2DNT board */
	34
	35	#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
	36
	37	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	38	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	39
31d82672 BB	40	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
31d82672 BB	41
0841565c	42	/*
	43	* Serial console configuration
	44	*/
	45	#define CONFIG_PSC_CONSOLE 5 /* console is on PSC5 */
	46	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
	47	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
	48
	49	/*
	50	* PCI Mapping:
	51	* 0x40000000 - 0x4fffffff - PCI Memory
	52	* 0x50000000 - 0x50ffffff - PCI IO Space
	53	*/
	54	#define CONFIG_PCI 1
	55	#define CONFIG_PCI_PNP 1
30eb1770	56	/* #define CONFIG_PCI_SCAN_SHOW 1 */
f33fca22	57	#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
0841565c	58
	59	#define CONFIG_PCI_MEM_BUS 0x40000000
	60	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	61	#define CONFIG_PCI_MEM_SIZE 0x10000000
	62
	63	#define CONFIG_PCI_IO_BUS 0x50000000
	64	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	65	#define CONFIG_PCI_IO_SIZE 0x01000000
	66
	67	#define CFG_XLB_PIPELINING 1
	68
	69	#define CONFIG_NET_MULTI 1
63ff004c	70	#define CONFIG_EEPRO100
0841565c	71	#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
	72	#define CONFIG_NS8382X 1
	73
0841565c	74	/* Partitions */
	75	#define CONFIG_MAC_PARTITION
	76	#define CONFIG_DOS_PARTITION
	77	#define CONFIG_ISO_PARTITION
	78
	79	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
	80
a5cb2309	81
7f5c0157 JL	82	/*
	83	* BOOTP options
	84	*/
	85	#define CONFIG_BOOTP_BOOTFILESIZE
	86	#define CONFIG_BOOTP_BOOTPATH
	87	#define CONFIG_BOOTP_GATEWAY
	88	#define CONFIG_BOOTP_HOSTNAME
	89
	90
0841565c	91	/*
a5cb2309	92	* Command line configuration.
0841565c	93	*/
a5cb2309 JL	94	#include <config_cmd_default.h>
	95
	96	#define CONFIG_CMD_EEPROM
	97	#define CONFIG_CMD_FAT
	98	#define CONFIG_CMD_I2C
	99	#define CONFIG_CMD_NFS
	100	#define CONFIG_CMD_MII
	101	#define CONFIG_CMD_PING
7f5c0157	102	#define CONFIG_CMD_PCI
a5cb2309	103
0841565c	104
	105	#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
	106	# define CFG_LOWBOOT 1
	107	#else
	108	# error "TEXT_BASE must be 0xFF000000"
	109	#endif
	110
	111	/*
	112	* Autobooting
	113	*/
	114	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	115
	116	#define CONFIG_PREBOOT "echo;" \
32bf3d14	117	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
0841565c	118	"echo"
	119
	120	#undef CONFIG_BOOTARGS
	121
	122	#define CONFIG_EXTRA_ENV_SETTINGS \
	123	"netdev=eth0\0" \
	124	"nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b	125	"nfsroot=${serverip}:${rootpath}\0" \
0841565c	126	"ramargs=setenv bootargs root=/dev/ram rw\0" \
fe126d8b WD	127	"addip=setenv bootargs ${bootargs} " \
	128	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	129	":${hostname}:${netdev}:off panic=1\0" \
0841565c	130	"flash_nfs=run nfsargs addip;" \
fe126d8b	131	"bootm ${kernel_addr}\0" \
0841565c	132	"flash_self=run ramargs addip;" \
fe126d8b WD	133	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
fe126d8b WD	134	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
0841565c	135	"rootpath=/opt/eldk/ppc_82xx\0" \
	136	"bootfile=/tftpboot/MPC5200/uImage\0" \
	137	""
	138
	139	#define CONFIG_BOOTCOMMAND "run flash_self"
	140
	141	#if defined(CONFIG_MPC5200)
	142	/*
	143	* IPB Bus clocking configuration.
	144	*/
c99512d6	145	#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
0a69b26e	146
c99512d6	147	#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
0a69b26e MB	148	/*
	149	* PCI Bus clocking configuration
	150	*
	151	* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
c99512d6 BS	152	* CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
c99512d6 BS	153	* of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
0a69b26e	154	*/
c99512d6	155	#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
0a69b26e	156	#endif
0841565c	157	#endif
0a69b26e	158
0841565c	159	/*
	160	* I2C configuration
	161	*/
	162	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
	163	#define CFG_I2C_MODULE 1 /* Select I2C module #1 or #2 */
	164
	165	#define CFG_I2C_SPEED 100000 /* 100 kHz */
	166	#define CFG_I2C_SLAVE 0x7F
	167
	168	/*
5a27f848	169	* EEPROM configuration:
	170	*
	171	* O2DNT board is equiped with Ramtron FRAM device FM24CL16
	172	* 16 Kib Ferroelectric Nonvolatile serial RAM memory
	173	* organized as 2048 x 8 bits and addressable as eight I2C devices
	174	* 0x50 ... 0x57 each 256 bytes in size
	175	*
0841565c	176	*/
d4f5c728	177	#define CFG_I2C_FRAM
0841565c	178	#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
	179	#define CFG_I2C_EEPROM_ADDR_LEN 1
	180	#define CFG_EEPROM_PAGE_WRITE_BITS 3
5a27f848	181	/*
	182	* There is no write delay with FRAM, write operations are performed at bus
	183	* speed. Thus, no status polling or write delay is needed.
	184	*/
	185	/#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70/
	186
0841565c	187
	188	/*
	189	* Flash configuration
	190	*/
	191	#define CFG_FLASH_BASE 0xFF000000
	192	#define CFG_FLASH_SIZE 0x01000000
0e8d1586	193	#define CONFIG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000)
0841565c	194
	195	#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
	196	#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
	197
	198	#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
	199	#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
adac376e	200	#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
adac376e	201	#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
0841565c	202
	203	/*
	204	* Environment settings
	205	*/
5a1aceb0	206	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	207	#define CONFIG_ENV_SIZE 0x20000
0e8d1586 JCPV	208	#define CONFIG_ENV_SECT_SIZE 0x20000
0841565c	209	#define CONFIG_ENV_OVERWRITE 1
	210
	211	/*
	212	* Memory map
	213	*/
	214	#define CFG_MBAR 0xF0000000
	215	#define CFG_SDRAM_BASE 0x00000000
	216	#define CFG_DEFAULT_MBAR 0x80000000
	217
	218	/* Use SRAM until RAM will be available */
	219	#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
	220	#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
	221
	222
	223	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	224	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	225	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	226
	227	#define CFG_MONITOR_BASE TEXT_BASE
	228	#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
	229	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	230	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	231
	232	/*
	233	* Ethernet configuration
	234	*/
	235	#define CONFIG_MPC5xxx_FEC 1
	236	/*
	237	* Define CONFIG_FEC_10MBIT to force FEC at 10Mb
	238	*/
	239	/* #define CONFIG_FEC_10MBIT 1 */
	240	#define CONFIG_PHY_ADDR 0x00
	241
	242	/*
	243	* GPIO configuration
	244	*/
6617aae9	245	/#define CFG_GPS_PORT_CONFIG 0x10002004 /
3a7b142b	246	#define CFG_GPS_PORT_CONFIG 0x00002006 /* no CAN */
0841565c	247
	248	/*
	249	* Miscellaneous configurable options
	250	*/
	251	#define CFG_LONGHELP /* undef to save memory */
	252	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	253
a5cb2309	254	#if defined(CONFIG_CMD_KGDB)
0841565c	255	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	256	#else
	257	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	258	#endif
	259	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	260	#define CFG_MAXARGS 16 /* max number of command args */
	261	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	262
	263	#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
	264	#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
	265
	266	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	267
	268	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	269
a5cb2309 JL	270	#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
	271	#if defined(CONFIG_CMD_KGDB)
	272	# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	273	#endif
	274
0841565c	275	/*
	276	* Various low-level settings
	277	*/
	278	#if defined(CONFIG_MPC5200)
	279	#define CFG_HID0_INIT HID0_ICE \| HID0_ICFI
	280	#define CFG_HID0_FINAL HID0_ICE
	281	#else
	282	#define CFG_HID0_INIT 0
	283	#define CFG_HID0_FINAL 0
	284	#endif
	285
	286	#define CFG_BOOTCS_START CFG_FLASH_BASE
	287	#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
0a69b26e	288
c99512d6	289	#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
f013dacf	290	/*
0a69b26e MB	291	* For 66 MHz PCI clock additional Wait State is needed for CS0 (flash).
	292	*/
	293	#define CFG_BOOTCS_CFG 0x00057801 /* for pci_clk = 66 MHz */
	294	#else
	295	#define CFG_BOOTCS_CFG 0x00047801 /* for pci_clk = 33 MHz */
	296	#endif
	297
0841565c	298	#define CFG_CS0_START CFG_FLASH_BASE
	299	#define CFG_CS0_SIZE CFG_FLASH_SIZE
	300
	301	#define CFG_CS_BURST 0x00000000
	302	#define CFG_CS_DEADCYCLE 0x33333333
	303
	304	#define CFG_RESET_ADDRESS 0xff000000
	305
	306	#endif /* __CONFIG_H */