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0841565c | 1 | /* |
2 | * (C) Copyright 2005 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #ifndef __CONFIG_H | |
25 | #define __CONFIG_H | |
26 | ||
27 | /* | |
28 | * High Level Configuration Options | |
29 | * (easy to change) | |
30 | */ | |
31 | #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ | |
32 | #define CONFIG_MPC5200 | |
33 | #define CONFIG_O2DNT 1 /* ... on O2DNT board */ | |
34 | ||
2ae18241 WD |
35 | #define CONFIG_SYS_TEXT_BASE 0xFF000000 /* boot low for 16 MiB boards */ |
36 | ||
6d0f6bcf | 37 | #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ |
0841565c | 38 | |
31d82672 BB |
39 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
40 | ||
0841565c | 41 | /* |
42 | * Serial console configuration | |
43 | */ | |
44 | #define CONFIG_PSC_CONSOLE 5 /* console is on PSC5 */ | |
45 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
6d0f6bcf | 46 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
0841565c | 47 | |
48 | /* | |
49 | * PCI Mapping: | |
50 | * 0x40000000 - 0x4fffffff - PCI Memory | |
51 | * 0x50000000 - 0x50ffffff - PCI IO Space | |
52 | */ | |
53 | #define CONFIG_PCI 1 | |
54 | #define CONFIG_PCI_PNP 1 | |
30eb1770 | 55 | /* #define CONFIG_PCI_SCAN_SHOW 1 */ |
f33fca22 | 56 | #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 |
0841565c | 57 | |
58 | #define CONFIG_PCI_MEM_BUS 0x40000000 | |
59 | #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS | |
60 | #define CONFIG_PCI_MEM_SIZE 0x10000000 | |
61 | ||
62 | #define CONFIG_PCI_IO_BUS 0x50000000 | |
63 | #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS | |
64 | #define CONFIG_PCI_IO_SIZE 0x01000000 | |
65 | ||
6d0f6bcf | 66 | #define CONFIG_SYS_XLB_PIPELINING 1 |
0841565c | 67 | |
68 | #define CONFIG_NET_MULTI 1 | |
63ff004c | 69 | #define CONFIG_EEPRO100 |
6d0f6bcf | 70 | #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
0841565c | 71 | #define CONFIG_NS8382X 1 |
72 | ||
0841565c | 73 | /* Partitions */ |
74 | #define CONFIG_MAC_PARTITION | |
75 | #define CONFIG_DOS_PARTITION | |
76 | #define CONFIG_ISO_PARTITION | |
77 | ||
78 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ | |
79 | ||
a5cb2309 | 80 | |
7f5c0157 JL |
81 | /* |
82 | * BOOTP options | |
83 | */ | |
84 | #define CONFIG_BOOTP_BOOTFILESIZE | |
85 | #define CONFIG_BOOTP_BOOTPATH | |
86 | #define CONFIG_BOOTP_GATEWAY | |
87 | #define CONFIG_BOOTP_HOSTNAME | |
88 | ||
89 | ||
0841565c | 90 | /* |
a5cb2309 | 91 | * Command line configuration. |
0841565c | 92 | */ |
a5cb2309 JL |
93 | #include <config_cmd_default.h> |
94 | ||
95 | #define CONFIG_CMD_EEPROM | |
96 | #define CONFIG_CMD_FAT | |
97 | #define CONFIG_CMD_I2C | |
98 | #define CONFIG_CMD_NFS | |
99 | #define CONFIG_CMD_MII | |
100 | #define CONFIG_CMD_PING | |
7f5c0157 | 101 | #define CONFIG_CMD_PCI |
a5cb2309 | 102 | |
0841565c | 103 | |
14d0a02a | 104 | #if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ |
6d0f6bcf | 105 | # define CONFIG_SYS_LOWBOOT 1 |
0841565c | 106 | #else |
14d0a02a | 107 | # error "CONFIG_SYS_TEXT_BASE must be 0xFF000000" |
0841565c | 108 | #endif |
109 | ||
110 | /* | |
111 | * Autobooting | |
112 | */ | |
113 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
114 | ||
115 | #define CONFIG_PREBOOT "echo;" \ | |
32bf3d14 | 116 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
0841565c | 117 | "echo" |
118 | ||
119 | #undef CONFIG_BOOTARGS | |
120 | ||
121 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
122 | "netdev=eth0\0" \ | |
123 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
fe126d8b | 124 | "nfsroot=${serverip}:${rootpath}\0" \ |
0841565c | 125 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
fe126d8b WD |
126 | "addip=setenv bootargs ${bootargs} " \ |
127 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
128 | ":${hostname}:${netdev}:off panic=1\0" \ | |
0841565c | 129 | "flash_nfs=run nfsargs addip;" \ |
fe126d8b | 130 | "bootm ${kernel_addr}\0" \ |
0841565c | 131 | "flash_self=run ramargs addip;" \ |
fe126d8b WD |
132 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
133 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ | |
0841565c | 134 | "rootpath=/opt/eldk/ppc_82xx\0" \ |
135 | "bootfile=/tftpboot/MPC5200/uImage\0" \ | |
136 | "" | |
137 | ||
138 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
139 | ||
0841565c | 140 | /* |
141 | * IPB Bus clocking configuration. | |
142 | */ | |
6d0f6bcf | 143 | #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ |
0a69b26e | 144 | |
6d0f6bcf | 145 | #if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) |
0a69b26e MB |
146 | /* |
147 | * PCI Bus clocking configuration | |
148 | * | |
149 | * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if | |
6d0f6bcf | 150 | * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock |
c99512d6 | 151 | * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz. |
0a69b26e | 152 | */ |
6d0f6bcf | 153 | #define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ |
0a69b26e | 154 | #endif |
0a69b26e | 155 | |
0841565c | 156 | /* |
157 | * I2C configuration | |
158 | */ | |
159 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
6d0f6bcf | 160 | #define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 or #2 */ |
0841565c | 161 | |
6d0f6bcf JCPV |
162 | #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ |
163 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
0841565c | 164 | |
165 | /* | |
5a27f848 | 166 | * EEPROM configuration: |
167 | * | |
168 | * O2DNT board is equiped with Ramtron FRAM device FM24CL16 | |
169 | * 16 Kib Ferroelectric Nonvolatile serial RAM memory | |
170 | * organized as 2048 x 8 bits and addressable as eight I2C devices | |
171 | * 0x50 ... 0x57 each 256 bytes in size | |
172 | * | |
0841565c | 173 | */ |
6d0f6bcf JCPV |
174 | #define CONFIG_SYS_I2C_FRAM |
175 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ | |
176 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
177 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
5a27f848 | 178 | /* |
179 | * There is no write delay with FRAM, write operations are performed at bus | |
180 | * speed. Thus, no status polling or write delay is needed. | |
181 | */ | |
6d0f6bcf | 182 | /*#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70*/ |
5a27f848 | 183 | |
0841565c | 184 | |
185 | /* | |
186 | * Flash configuration | |
187 | */ | |
6d0f6bcf JCPV |
188 | #define CONFIG_SYS_FLASH_BASE 0xFF000000 |
189 | #define CONFIG_SYS_FLASH_SIZE 0x01000000 | |
190 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000) | |
0841565c | 191 | |
6d0f6bcf JCPV |
192 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ |
193 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ | |
0841565c | 194 | |
6d0f6bcf JCPV |
195 | #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ |
196 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ | |
197 | #define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */ | |
198 | #define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ | |
0841565c | 199 | |
200 | /* | |
201 | * Environment settings | |
202 | */ | |
5a1aceb0 | 203 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
204 | #define CONFIG_ENV_SIZE 0x20000 |
205 | #define CONFIG_ENV_SECT_SIZE 0x20000 | |
0841565c | 206 | #define CONFIG_ENV_OVERWRITE 1 |
207 | ||
208 | /* | |
209 | * Memory map | |
210 | */ | |
6d0f6bcf JCPV |
211 | #define CONFIG_SYS_MBAR 0xF0000000 |
212 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
213 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 | |
0841565c | 214 | |
215 | /* Use SRAM until RAM will be available */ | |
6d0f6bcf | 216 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM |
553f0982 | 217 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ |
0841565c | 218 | |
219 | ||
6d0f6bcf | 220 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
553f0982 | 221 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE) |
6d0f6bcf | 222 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
0841565c | 223 | |
14d0a02a | 224 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
225 | #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
226 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
227 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
0841565c | 228 | |
229 | /* | |
230 | * Ethernet configuration | |
231 | */ | |
232 | #define CONFIG_MPC5xxx_FEC 1 | |
86321fc1 | 233 | #define CONFIG_MPC5xxx_FEC_MII100 |
0841565c | 234 | /* |
86321fc1 | 235 | * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb |
0841565c | 236 | */ |
86321fc1 | 237 | /* #define CONFIG_MPC5xxx_FEC_MII10 */ |
0841565c | 238 | #define CONFIG_PHY_ADDR 0x00 |
239 | ||
240 | /* | |
241 | * GPIO configuration | |
242 | */ | |
6d0f6bcf JCPV |
243 | /*#define CONFIG_SYS_GPS_PORT_CONFIG 0x10002004 */ |
244 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x00002006 /* no CAN */ | |
0841565c | 245 | |
246 | /* | |
247 | * Miscellaneous configurable options | |
248 | */ | |
6d0f6bcf JCPV |
249 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
250 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
0841565c | 251 | |
a5cb2309 | 252 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 253 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
0841565c | 254 | #else |
6d0f6bcf | 255 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
0841565c | 256 | #endif |
6d0f6bcf JCPV |
257 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
258 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
259 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
0841565c | 260 | |
6d0f6bcf JCPV |
261 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
262 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
0841565c | 263 | |
6d0f6bcf | 264 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
0841565c | 265 | |
6d0f6bcf | 266 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
0841565c | 267 | |
6d0f6bcf | 268 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
a5cb2309 | 269 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 270 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
a5cb2309 JL |
271 | #endif |
272 | ||
0841565c | 273 | /* |
274 | * Various low-level settings | |
275 | */ | |
6d0f6bcf JCPV |
276 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI |
277 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
0841565c | 278 | |
6d0f6bcf JCPV |
279 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE |
280 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
0a69b26e | 281 | |
6d0f6bcf | 282 | #ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 |
f013dacf | 283 | /* |
0a69b26e MB |
284 | * For 66 MHz PCI clock additional Wait State is needed for CS0 (flash). |
285 | */ | |
6d0f6bcf | 286 | #define CONFIG_SYS_BOOTCS_CFG 0x00057801 /* for pci_clk = 66 MHz */ |
0a69b26e | 287 | #else |
6d0f6bcf | 288 | #define CONFIG_SYS_BOOTCS_CFG 0x00047801 /* for pci_clk = 33 MHz */ |
0a69b26e MB |
289 | #endif |
290 | ||
6d0f6bcf JCPV |
291 | #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE |
292 | #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE | |
0841565c | 293 | |
6d0f6bcf JCPV |
294 | #define CONFIG_SYS_CS_BURST 0x00000000 |
295 | #define CONFIG_SYS_CS_DEADCYCLE 0x33333333 | |
0841565c | 296 | |
6d0f6bcf | 297 | #define CONFIG_SYS_RESET_ADDRESS 0xff000000 |
0841565c | 298 | |
299 | #endif /* __CONFIG_H */ |