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0e6d798c WD |
1 | /* |
2 | * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com> | |
3 | * | |
8a316c9b SR |
4 | * (C) Copyright 2005 |
5 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
6 | * | |
0e6d798c WD |
7 | * See file CREDITS for list of people who contributed to this |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
25 | ||
26 | /************************************************************************ | |
42dfe7a1 | 27 | * 1 March 2004 Travis B. Sawyer <tsawyer@sandburst.com> |
0e6d798c WD |
28 | * Adapted to current Das U-Boot source |
29 | ***********************************************************************/ | |
30 | ||
31 | ||
32 | /************************************************************************ | |
0c8721a4 | 33 | * OCOTEA.h - configuration for AMCC 440GX Ref (Ocotea) |
0e6d798c WD |
34 | ***********************************************************************/ |
35 | ||
36 | #ifndef __CONFIG_H | |
37 | #define __CONFIG_H | |
38 | ||
39 | /*----------------------------------------------------------------------- | |
40 | * High Level Configuration Options | |
41 | *----------------------------------------------------------------------*/ | |
42 | #define CONFIG_OCOTEA 1 /* Board is ebony */ | |
846b0dd2 | 43 | #define CONFIG_440GX 1 /* Specifc GX support */ |
efa35cf1 | 44 | #define CONFIG_440 1 /* ... PPC440 family */ |
0e6d798c WD |
45 | #define CONFIG_4xx 1 /* ... PPC4xx family */ |
46 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ | |
0e6d798c WD |
47 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ |
48 | ||
2ae18241 WD |
49 | #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 |
50 | ||
72675dc6 SR |
51 | /* |
52 | * Include common defines/options for all AMCC eval boards | |
53 | */ | |
54 | #define CONFIG_HOSTNAME ocotea | |
55 | #include "amcc-common.h" | |
56 | ||
0e6d798c WD |
57 | /*----------------------------------------------------------------------- |
58 | * Base addresses -- Note these are effective addresses where the | |
59 | * actual resources get mapped (not physical addresses) | |
60 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
61 | #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH */ |
62 | #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ | |
6d0f6bcf JCPV |
63 | #define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */ |
64 | #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ | |
0e6d798c | 65 | |
6d0f6bcf JCPV |
66 | #define CONFIG_SYS_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08300000) |
67 | #define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000) | |
0e6d798c WD |
68 | |
69 | /*----------------------------------------------------------------------- | |
70 | * Initial RAM & stack pointer (placed in internal SRAM) | |
71 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
72 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
73 | #define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE | |
74 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */ | |
553f0982 | 75 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ |
0e6d798c | 76 | |
25ddd1fb | 77 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
800eb096 | 78 | #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) |
0e6d798c | 79 | |
0e6d798c WD |
80 | /*----------------------------------------------------------------------- |
81 | * Serial Port | |
82 | *----------------------------------------------------------------------*/ | |
550650dd | 83 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
6d0f6bcf | 84 | #define CONFIG_SYS_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */ |
0e6d798c | 85 | |
8a316c9b SR |
86 | /*----------------------------------------------------------------------- |
87 | * Environment | |
88 | *----------------------------------------------------------------------*/ | |
89 | /* | |
90 | * Define here the location of the environment variables (FLASH or NVRAM). | |
91 | * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only | |
92 | * supported for backward compatibility. | |
93 | */ | |
94 | #if 1 | |
5a1aceb0 | 95 | #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
8a316c9b | 96 | #else |
9314cee6 | 97 | #define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ |
8a316c9b SR |
98 | #endif |
99 | ||
100 | ||
0e6d798c WD |
101 | /*----------------------------------------------------------------------- |
102 | * NVRAM/RTC | |
103 | * | |
104 | * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located. | |
105 | * The DS1743 code assumes this condition (i.e. -- it assumes the base | |
106 | * address for the RTC registers is: | |
107 | * | |
6d0f6bcf | 108 | * CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE |
0e6d798c WD |
109 | * |
110 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 111 | #define CONFIG_SYS_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */ |
0e6d798c WD |
112 | #define CONFIG_RTC_DS174x 1 /* DS1743 RTC */ |
113 | ||
9314cee6 | 114 | #ifdef CONFIG_ENV_IS_IN_NVRAM |
0e8d1586 JCPV |
115 | #define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */ |
116 | #define CONFIG_ENV_ADDR \ | |
6d0f6bcf | 117 | (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) |
9314cee6 | 118 | #endif /* CONFIG_ENV_IS_IN_NVRAM */ |
8a316c9b | 119 | |
0e6d798c WD |
120 | /*----------------------------------------------------------------------- |
121 | * FLASH related | |
122 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
123 | #define CONFIG_SYS_MAX_FLASH_BANKS 3 /* number of banks */ |
124 | #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ | |
0e6d798c | 125 | |
6d0f6bcf JCPV |
126 | #undef CONFIG_SYS_FLASH_CHECKSUM |
127 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
128 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
0e6d798c | 129 | |
6d0f6bcf JCPV |
130 | #define CONFIG_SYS_FLASH_ADDR0 0x5555 |
131 | #define CONFIG_SYS_FLASH_ADDR1 0x2aaa | |
132 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned char | |
8a316c9b | 133 | |
5a1aceb0 | 134 | #ifdef CONFIG_ENV_IS_IN_FLASH |
0e8d1586 | 135 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ |
6d0f6bcf | 136 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) |
0e8d1586 | 137 | #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
8a316c9b SR |
138 | |
139 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
140 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) |
141 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
5a1aceb0 | 142 | #endif /* CONFIG_ENV_IS_IN_FLASH */ |
8a316c9b | 143 | |
0e6d798c WD |
144 | /*----------------------------------------------------------------------- |
145 | * DDR SDRAM | |
146 | *----------------------------------------------------------------------*/ | |
fa1aef15 | 147 | #define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ |
42dfe7a1 | 148 | #define SPD_EEPROM_ADDRESS {0x53,0x52} /* SPD i2c spd addresses */ |
fa1aef15 | 149 | #define CONFIG_PROG_SDRAM_TLB 1 /* setup SDRAM TLB's dynamically*/ |
0e6d798c WD |
150 | |
151 | /*----------------------------------------------------------------------- | |
152 | * I2C | |
153 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 154 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
4f92ed5f | 155 | |
6d0f6bcf JCPV |
156 | #define CONFIG_SYS_I2C_MULTI_EEPROMS |
157 | #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) | |
158 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
159 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
160 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
0e6d798c | 161 | |
72675dc6 SR |
162 | /* |
163 | * Default environment variables | |
164 | */ | |
8a316c9b | 165 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
72675dc6 SR |
166 | CONFIG_AMCC_DEF_ENV \ |
167 | CONFIG_AMCC_DEF_ENV_PPC \ | |
168 | CONFIG_AMCC_DEF_ENV_NOR_UPD \ | |
8a316c9b SR |
169 | "kernel_addr=fff00000\0" \ |
170 | "ramdisk_addr=fff10000\0" \ | |
8a316c9b | 171 | "" |
8a316c9b | 172 | |
0e6d798c | 173 | #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ |
42dfe7a1 WD |
174 | #define CONFIG_PHY1_ADDR 2 |
175 | #define CONFIG_PHY2_ADDR 0x10 | |
176 | #define CONFIG_PHY3_ADDR 0x18 | |
d6c61aab SR |
177 | #define CONFIG_HAS_ETH0 |
178 | #define CONFIG_HAS_ETH1 | |
179 | #define CONFIG_HAS_ETH2 | |
180 | #define CONFIG_HAS_ETH3 | |
42dfe7a1 | 181 | #define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */ |
6fb6af6d | 182 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ |
d6c61aab SR |
183 | #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ |
184 | #define CONFIG_PHY_RESET_DELAY 1000 | |
a5cb2309 | 185 | |
7f5c0157 | 186 | /* |
72675dc6 | 187 | * Commands additional to the ones defined in amcc-common.h |
7f5c0157 | 188 | */ |
a5cb2309 | 189 | #define CONFIG_CMD_DATE |
a5cb2309 | 190 | #define CONFIG_CMD_PCI |
a5cb2309 JL |
191 | #define CONFIG_CMD_SDRAM |
192 | #define CONFIG_CMD_SNTP | |
193 | ||
0e6d798c WD |
194 | /*----------------------------------------------------------------------- |
195 | * PCI stuff | |
196 | *----------------------------------------------------------------------- | |
197 | */ | |
198 | /* General PCI */ | |
8a316c9b SR |
199 | #define CONFIG_PCI /* include pci support */ |
200 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
42dfe7a1 | 201 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
6d0f6bcf | 202 | #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */ |
0e6d798c WD |
203 | |
204 | /* Board-specific PCI */ | |
6d0f6bcf | 205 | #define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */ |
0e6d798c | 206 | |
6d0f6bcf JCPV |
207 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ |
208 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ | |
0e6d798c | 209 | |
0e6d798c | 210 | #endif /* __CONFIG_H */ |