[people/ms/u-boot.git] / include / configs / ocotea.h

/*
 * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
 *
 * (C) Copyright 2005
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/************************************************************************
 * 1 March 2004	 Travis B. Sawyer <tsawyer@sandburst.com>
 * Adapted to current Das U-Boot source
 ***********************************************************************/


/************************************************************************
 * OCOTEA.h - configuration for AMCC 440GX Ref (Ocotea)
 ***********************************************************************/

#ifndef __CONFIG_H
#define __CONFIG_H

/*-----------------------------------------------------------------------
 * High Level Configuration Options
 *----------------------------------------------------------------------*/
#define CONFIG_OCOTEA		1	    /* Board is ebony		*/
#define CONFIG_440GX		1	    /* Specifc GX support	*/
#define CONFIG_440		1	    /* ... PPC440 family	*/
#define CONFIG_4xx		1	    /* ... PPC4xx family	*/
#define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_pre_init	*/
#define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/

/*-----------------------------------------------------------------------
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 *----------------------------------------------------------------------*/
#define CFG_SDRAM_BASE	    0x00000000	    /* _must_ be 0		*/
#define CFG_FLASH_BASE	    0xff800000	    /* start of FLASH		*/
#define CFG_MONITOR_BASE    0xfffc0000	    /* start of monitor		*/
#define CFG_PCI_MEMBASE	    0x80000000	    /* mapped pci memory	*/
#define CFG_PERIPHERAL_BASE 0xe0000000	    /* internal peripherals	*/
#define CFG_ISRAM_BASE	    0xc0000000	    /* internal SRAM		*/
#define CFG_PCI_BASE	    0xd0000000	    /* internal PCI regs	*/

#define CFG_FPGA_BASE	    (CFG_PERIPHERAL_BASE + 0x08300000)
#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)

/*-----------------------------------------------------------------------
 * Initial RAM & stack pointer (placed in internal SRAM)
 *----------------------------------------------------------------------*/
#define CFG_TEMP_STACK_OCM  1
#define CFG_OCM_DATA_ADDR   CFG_ISRAM_BASE
#define CFG_INIT_RAM_ADDR   CFG_ISRAM_BASE  /* Initial RAM address	*/
#define CFG_INIT_RAM_END    0x2000	    /* End of used area in RAM	*/
#define CFG_GBL_DATA_SIZE   128		    /* num bytes initial data	*/

#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_POST_WORD_ADDR	(CFG_GBL_DATA_OFFSET - 0x4)
#define CFG_INIT_SP_OFFSET	CFG_POST_WORD_ADDR

#define CFG_MONITOR_LEN	    (256 * 1024)    /* Reserve 256 kB for Mon	*/
#define CFG_MALLOC_LEN	    (128 * 1024)    /* Reserve 128 kB for malloc*/

/*-----------------------------------------------------------------------
 * Serial Port
 *----------------------------------------------------------------------*/
#undef	CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_EXT_SERIAL_CLOCK	(1843200 * 6)	/* Ext clk @ 11.059 MHz */
#define CONFIG_BAUDRATE		115200

#define CFG_BAUDRATE_TABLE  \
    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

/*-----------------------------------------------------------------------
 * Environment
 *----------------------------------------------------------------------*/
/*
 * Define here the location of the environment variables (FLASH or NVRAM).
 * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
 *       supported for backward compatibility.
 */
#if 1
#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
#else
#define CFG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
#endif


/*-----------------------------------------------------------------------
 * NVRAM/RTC
 *
 * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
 * The DS1743 code assumes this condition (i.e. -- it assumes the base
 * address for the RTC registers is:
 *
 *	CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
 *
 *----------------------------------------------------------------------*/
#define CFG_NVRAM_SIZE	    (0x2000 - 8)    /* NVRAM size(8k)- RTC regs */
#define CONFIG_RTC_DS174x	1		    /* DS1743 RTC		*/

#ifdef CFG_ENV_IS_IN_NVRAM
#define CFG_ENV_SIZE		0x1000	    /* Size of Environment vars */
#define CFG_ENV_ADDR		\
	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)
#endif /* CFG_ENV_IS_IN_NVRAM */

/*-----------------------------------------------------------------------
 * FLASH related
 *----------------------------------------------------------------------*/
#define CFG_MAX_FLASH_BANKS	3		    /* number of banks	    */
#define CFG_MAX_FLASH_SECT	64		    /* sectors per device   */

#undef	CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CFG_FLASH_ADDR0         0x5555
#define CFG_FLASH_ADDR1         0x2aaa
#define CFG_FLASH_WORD_SIZE     unsigned char

#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE	0x10000		/* size of one complete sector	*/
#define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
#endif /* CFG_ENV_IS_IN_FLASH */

/*-----------------------------------------------------------------------
 * DDR SDRAM
 *----------------------------------------------------------------------*/
#define CONFIG_SPD_EEPROM	1	/* Use SPD EEPROM for setup	*/
#define SPD_EEPROM_ADDRESS {0x53,0x52}	/* SPD i2c spd addresses	*/
#define CONFIG_PROG_SDRAM_TLB	1	/* setup SDRAM TLB's dynamically*/

/*-----------------------------------------------------------------------
 * I2C
 *----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C		1	    /* I2C with hardware support	*/
#undef	CONFIG_SOFT_I2C			    /* I2C bit-banged		*/
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
#define CFG_I2C_SLAVE		0x7F

#define CFG_I2C_MULTI_EEPROMS
#define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_EEPROM_PAGE_WRITE_ENABLE
#define CFG_EEPROM_PAGE_WRITE_BITS 3
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"hostname=ocotea\0"						\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
	"flash_nfs=run nfsargs addip addtty;"				\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip addtty;"				\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
	        "bootm\0"						\
	"rootpath=/opt/eldk/ppc_4xx\0"					\
	"bootfile=/tftpboot/ocotea/uImage\0"				\
	"kernel_addr=fff00000\0"					\
	"ramdisk_addr=fff10000\0"					\
	"initrd_high=30000000\0"					\
	"load=tftp 100000 /tftpboot/ocotea/u-boot.bin\0"		\
	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
		"cp.b 100000 fffc0000 40000;"			        \
		"setenv filesize;saveenv\0"				\
	"upd=run load update\0"						\
	""
#define CONFIG_BOOTCOMMAND	"run flash_self"

#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif

#define CONFIG_BAUDRATE		115200

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_NET_MULTI	1
#define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/
#define CONFIG_PHY1_ADDR	2
#define CONFIG_PHY2_ADDR	0x10
#define CONFIG_PHY3_ADDR	0x18
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#define CONFIG_HAS_ETH3
#define CONFIG_CIS8201_PHY	1	/* Enable 'special' RGMII mode for Cicada phy */
#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
#define CONFIG_PHY_RESET        1       /* reset phy upon startup         */
#define CONFIG_PHY_RESET_DELAY	1000
#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */

#define CONFIG_NETCONSOLE		/* include NetConsole support	*/


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_ELF
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_SNTP


#undef CONFIG_WATCHDOG			/* watchdog disabled		*/

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x100000	/* default load address */
#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */

#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */

#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
#define CONFIG_LOOPW            1       /* enable loopw command         */
#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
/* General PCI */
#define CONFIG_PCI			/* include pci support		*/
#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
#define CFG_PCI_TARGBASE    0x80000000	/* PCIaddr mapped to CFG_PCI_MEMBASE */

/* Board-specific PCI */
#define CFG_PCI_TARGET_INIT		/* let board init pci target    */

#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
#define CFG_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif

/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT	1
#define CONFIG_OF_BOARD_SETUP	1

#endif	/* __CONFIG_H */
Commit	Line	Data
0e6d798c WD	1	/*
	2	* (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
	3	*
8a316c9b SR	4	* (C) Copyright 2005
	5	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	6	*
0e6d798c WD	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	/************************************************************************
42dfe7a1	27	* 1 March 2004 Travis B. Sawyer <tsawyer@sandburst.com>
0e6d798c WD	28	* Adapted to current Das U-Boot source
	29	***********************************************************************/
	30
	31
	32	/************************************************************************
0c8721a4	33	* OCOTEA.h - configuration for AMCC 440GX Ref (Ocotea)
0e6d798c WD	34	***********************************************************************/
	35
	36	#ifndef __CONFIG_H
	37	#define __CONFIG_H
	38
	39	/*-----------------------------------------------------------------------
	40	* High Level Configuration Options
	41	----------------------------------------------------------------------/
	42	#define CONFIG_OCOTEA 1 /* Board is ebony */
846b0dd2	43	#define CONFIG_440GX 1 /* Specifc GX support */
efa35cf1	44	#define CONFIG_440 1 /* ... PPC440 family */
0e6d798c WD	45	#define CONFIG_4xx 1 /* ... PPC4xx family */
0e6d798c WD	46	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
0e6d798c WD	47	#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
	48
	49	/*-----------------------------------------------------------------------
	50	* Base addresses -- Note these are effective addresses where the
	51	* actual resources get mapped (not physical addresses)
	52	----------------------------------------------------------------------/
	53	#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
	54	#define CFG_FLASH_BASE 0xff800000 /* start of FLASH */
7ec25502	55	#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */
0e6d798c WD	56	#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
	57	#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
	58	#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
	59	#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
	60
	61	#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000)
	62	#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
	63
	64	/*-----------------------------------------------------------------------
	65	* Initial RAM & stack pointer (placed in internal SRAM)
	66	----------------------------------------------------------------------/
	67	#define CFG_TEMP_STACK_OCM 1
	68	#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE
	69	#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
	70	#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
	71	#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
	72
	73	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
42dfe7a1 WD	74	#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
42dfe7a1 WD	75	#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
0e6d798c WD	76
	77	#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
	78	#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
	79
	80	/*-----------------------------------------------------------------------
	81	* Serial Port
	82	----------------------------------------------------------------------/
	83	#undef CONFIG_SERIAL_SOFTWARE_FIFO
	84	#define CFG_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */
	85	#define CONFIG_BAUDRATE 115200
	86
	87	#define CFG_BAUDRATE_TABLE \
	88	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
	89
8a316c9b SR	90	/*-----------------------------------------------------------------------
	91	* Environment
	92	----------------------------------------------------------------------/
	93	/*
	94	* Define here the location of the environment variables (FLASH or NVRAM).
	95	* Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
	96	* supported for backward compatibility.
	97	*/
	98	#if 1
	99	#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
	100	#else
	101	#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
	102	#endif
	103
	104
0e6d798c WD	105	/*-----------------------------------------------------------------------
	106	* NVRAM/RTC
	107	*
	108	* NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
	109	* The DS1743 code assumes this condition (i.e. -- it assumes the base
	110	* address for the RTC registers is:
	111	*
	112	* CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
	113	*
	114	----------------------------------------------------------------------/
	115	#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */
	116	#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
	117
8a316c9b SR	118	#ifdef CFG_ENV_IS_IN_NVRAM
	119	#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
	120	#define CFG_ENV_ADDR \
	121	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)
	122	#endif /* CFG_ENV_IS_IN_NVRAM */
	123
0e6d798c WD	124	/*-----------------------------------------------------------------------
	125	* FLASH related
	126	----------------------------------------------------------------------/
	127	#define CFG_MAX_FLASH_BANKS 3 /* number of banks */
	128	#define CFG_MAX_FLASH_SECT 64 /* sectors per device */
	129
	130	#undef CFG_FLASH_CHECKSUM
	131	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	132	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
	133
8a316c9b SR	134	#define CFG_FLASH_ADDR0 0x5555
	135	#define CFG_FLASH_ADDR1 0x2aaa
	136	#define CFG_FLASH_WORD_SIZE unsigned char
	137
	138	#ifdef CFG_ENV_IS_IN_FLASH
1636d1c8	139	#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
8a316c9b SR	140	#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
	141	#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
	142
	143	/* Address and size of Redundant Environment Sector */
	144	#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
	145	#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
	146	#endif /* CFG_ENV_IS_IN_FLASH */
	147
0e6d798c WD	148	/*-----------------------------------------------------------------------
	149	* DDR SDRAM
	150	----------------------------------------------------------------------/
fa1aef15	151	#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
42dfe7a1	152	#define SPD_EEPROM_ADDRESS {0x53,0x52} /* SPD i2c spd addresses */
fa1aef15	153	#define CONFIG_PROG_SDRAM_TLB 1 /* setup SDRAM TLB's dynamically*/
0e6d798c WD	154
	155	/*-----------------------------------------------------------------------
	156	* I2C
	157	----------------------------------------------------------------------/
	158	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
	159	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
	160	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
	161	#define CFG_I2C_SLAVE 0x7F
4f92ed5f SR	162
	163	#define CFG_I2C_MULTI_EEPROMS
	164	#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
	165	#define CFG_I2C_EEPROM_ADDR_LEN 1
	166	#define CFG_EEPROM_PAGE_WRITE_ENABLE
	167	#define CFG_EEPROM_PAGE_WRITE_BITS 3
	168	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
0e6d798c	169
8a316c9b	170	#define CONFIG_PREBOOT "echo;" \
32bf3d14	171	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
8a316c9b SR	172	"echo"
	173
	174	#undef CONFIG_BOOTARGS
	175
	176	#define CONFIG_EXTRA_ENV_SETTINGS \
	177	"netdev=eth0\0" \
	178	"hostname=ocotea\0" \
	179	"nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b	180	"nfsroot=${serverip}:${rootpath}\0" \
8a316c9b	181	"ramargs=setenv bootargs root=/dev/ram rw\0" \
fe126d8b WD	182	"addip=setenv bootargs ${bootargs} " \
	183	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	184	":${hostname}:${netdev}:off panic=1\0" \
	185	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
8a316c9b	186	"flash_nfs=run nfsargs addip addtty;" \
fe126d8b	187	"bootm ${kernel_addr}\0" \
8a316c9b	188	"flash_self=run ramargs addip addtty;" \
fe126d8b WD	189	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
fe126d8b WD	190	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
8a316c9b SR	191	"bootm\0" \
	192	"rootpath=/opt/eldk/ppc_4xx\0" \
	193	"bootfile=/tftpboot/ocotea/uImage\0" \
	194	"kernel_addr=fff00000\0" \
	195	"ramdisk_addr=fff10000\0" \
5a753f98	196	"initrd_high=30000000\0" \
8a316c9b SR	197	"load=tftp 100000 /tftpboot/ocotea/u-boot.bin\0" \
	198	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
	199	"cp.b 100000 fffc0000 40000;" \
	200	"setenv filesize;saveenv\0" \
d8ab58b2	201	"upd=run load update\0" \
8a316c9b SR	202	""
	203	#define CONFIG_BOOTCOMMAND "run flash_self"
	204
	205	#if 0
	206	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	207	#else
	208	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	209	#endif
0e6d798c	210
0e6d798c WD	211	#define CONFIG_BAUDRATE 115200
	212
	213	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	214	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	215
	216	#define CONFIG_MII 1 /* MII PHY management */
	217	#define CONFIG_NET_MULTI 1
	218	#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
42dfe7a1 WD	219	#define CONFIG_PHY1_ADDR 2
	220	#define CONFIG_PHY2_ADDR 0x10
	221	#define CONFIG_PHY3_ADDR 0x18
d6c61aab SR	222	#define CONFIG_HAS_ETH0
	223	#define CONFIG_HAS_ETH1
	224	#define CONFIG_HAS_ETH2
	225	#define CONFIG_HAS_ETH3
42dfe7a1	226	#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
6fb6af6d	227	#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
d6c61aab SR	228	#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
d6c61aab SR	229	#define CONFIG_PHY_RESET_DELAY 1000
4f92ed5f SR	230	#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
	231
	232	#define CONFIG_NETCONSOLE /* include NetConsole support */
0e6d798c	233
a5cb2309	234
7f5c0157 JL	235	/*
	236	* BOOTP options
	237	*/
	238	#define CONFIG_BOOTP_BOOTFILESIZE
	239	#define CONFIG_BOOTP_BOOTPATH
	240	#define CONFIG_BOOTP_GATEWAY
	241	#define CONFIG_BOOTP_HOSTNAME
	242
	243
a5cb2309 JL	244	/*
	245	* Command line configuration.
	246	*/
	247	#include <config_cmd_default.h>
	248
	249	#define CONFIG_CMD_ASKENV
	250	#define CONFIG_CMD_DATE
	251	#define CONFIG_CMD_DHCP
	252	#define CONFIG_CMD_DIAG
	253	#define CONFIG_CMD_ELF
	254	#define CONFIG_CMD_EEPROM
	255	#define CONFIG_CMD_I2C
	256	#define CONFIG_CMD_IRQ
	257	#define CONFIG_CMD_MII
	258	#define CONFIG_CMD_NET
	259	#define CONFIG_CMD_NFS
	260	#define CONFIG_CMD_PCI
	261	#define CONFIG_CMD_PING
	262	#define CONFIG_CMD_REGINFO
	263	#define CONFIG_CMD_SDRAM
	264	#define CONFIG_CMD_SNTP
	265
0e6d798c WD	266
	267	#undef CONFIG_WATCHDOG /* watchdog disabled */
	268
	269	/*
	270	* Miscellaneous configurable options
	271	*/
	272	#define CFG_LONGHELP /* undef to save memory */
	273	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
a5cb2309	274	#if defined(CONFIG_CMD_KGDB)
0e6d798c WD	275	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	276	#else
	277	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	278	#endif
	279	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	280	#define CFG_MAXARGS 16 /* max number of command args */
	281	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	282
	283	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
	284	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
	285
	286	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	287	#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
	288
d6c61aab	289	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
0e6d798c	290
4f92ed5f	291	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
8a316c9b	292	#define CONFIG_LOOPW 1 /* enable loopw command */
4f92ed5f	293	#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
8a316c9b SR	294	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
	295	#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
	296
0e6d798c WD	297	/*-----------------------------------------------------------------------
	298	* PCI stuff
	299	*-----------------------------------------------------------------------
	300	*/
	301	/* General PCI */
8a316c9b SR	302	#define CONFIG_PCI /* include pci support */
8a316c9b SR	303	#define CONFIG_PCI_PNP /* do pci plug-and-play */
42dfe7a1 WD	304	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
42dfe7a1 WD	305	#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
0e6d798c WD	306
0e6d798c WD	307	/* Board-specific PCI */
8a316c9b	308	#define CFG_PCI_TARGET_INIT /* let board init pci target */
0e6d798c	309
8a316c9b	310	#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
42dfe7a1	311	#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
0e6d798c WD	312
	313	/*
	314	* For booting Linux, the board info and command line data
	315	* have to be in the first 8 MB of memory, since this is
	316	* the maximum mapped by the Linux kernel during initialization.
	317	*/
	318	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
0e6d798c WD	319
	320	/*
	321	* Internal Definitions
	322	*
	323	* Boot Flags
	324	*/
	325	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	326	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	327
a5cb2309	328	#if defined(CONFIG_CMD_KGDB)
0e6d798c WD	329	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	330	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	331	#endif
a00eccfe SR	332
	333	/* pass open firmware flat tree */
	334	#define CONFIG_OF_LIBFDT 1
	335	#define CONFIG_OF_BOARD_SETUP 1
	336
0e6d798c	337	#endif /* __CONFIG_H */