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0e6d798c WD |
1 | /* |
2 | * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com> | |
3 | * | |
8a316c9b SR |
4 | * (C) Copyright 2005 |
5 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
6 | * | |
0e6d798c WD |
7 | * See file CREDITS for list of people who contributed to this |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
25 | ||
26 | /************************************************************************ | |
42dfe7a1 | 27 | * 1 March 2004 Travis B. Sawyer <tsawyer@sandburst.com> |
0e6d798c WD |
28 | * Adapted to current Das U-Boot source |
29 | ***********************************************************************/ | |
30 | ||
31 | ||
32 | /************************************************************************ | |
0c8721a4 | 33 | * OCOTEA.h - configuration for AMCC 440GX Ref (Ocotea) |
0e6d798c WD |
34 | ***********************************************************************/ |
35 | ||
36 | #ifndef __CONFIG_H | |
37 | #define __CONFIG_H | |
38 | ||
39 | /*----------------------------------------------------------------------- | |
40 | * High Level Configuration Options | |
41 | *----------------------------------------------------------------------*/ | |
42 | #define CONFIG_OCOTEA 1 /* Board is ebony */ | |
846b0dd2 | 43 | #define CONFIG_440GX 1 /* Specifc GX support */ |
efa35cf1 | 44 | #define CONFIG_440 1 /* ... PPC440 family */ |
0e6d798c WD |
45 | #define CONFIG_4xx 1 /* ... PPC4xx family */ |
46 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ | |
0e6d798c WD |
47 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ |
48 | ||
72675dc6 SR |
49 | /* |
50 | * Include common defines/options for all AMCC eval boards | |
51 | */ | |
52 | #define CONFIG_HOSTNAME ocotea | |
53 | #include "amcc-common.h" | |
54 | ||
0e6d798c WD |
55 | /*----------------------------------------------------------------------- |
56 | * Base addresses -- Note these are effective addresses where the | |
57 | * actual resources get mapped (not physical addresses) | |
58 | *----------------------------------------------------------------------*/ | |
0e6d798c | 59 | #define CFG_FLASH_BASE 0xff800000 /* start of FLASH */ |
0e6d798c WD |
60 | #define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ |
61 | #define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ | |
62 | #define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ | |
63 | #define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ | |
64 | ||
65 | #define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000) | |
66 | #define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000) | |
67 | ||
68 | /*----------------------------------------------------------------------- | |
69 | * Initial RAM & stack pointer (placed in internal SRAM) | |
70 | *----------------------------------------------------------------------*/ | |
71 | #define CFG_TEMP_STACK_OCM 1 | |
72 | #define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE | |
73 | #define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ | |
74 | #define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ | |
75 | #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ | |
76 | ||
77 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
42dfe7a1 WD |
78 | #define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) |
79 | #define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR | |
0e6d798c | 80 | |
0e6d798c WD |
81 | /*----------------------------------------------------------------------- |
82 | * Serial Port | |
83 | *----------------------------------------------------------------------*/ | |
84 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
85 | #define CFG_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */ | |
0e6d798c | 86 | |
8a316c9b SR |
87 | /*----------------------------------------------------------------------- |
88 | * Environment | |
89 | *----------------------------------------------------------------------*/ | |
90 | /* | |
91 | * Define here the location of the environment variables (FLASH or NVRAM). | |
92 | * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only | |
93 | * supported for backward compatibility. | |
94 | */ | |
95 | #if 1 | |
5a1aceb0 | 96 | #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
8a316c9b | 97 | #else |
9314cee6 | 98 | #define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ |
8a316c9b SR |
99 | #endif |
100 | ||
101 | ||
0e6d798c WD |
102 | /*----------------------------------------------------------------------- |
103 | * NVRAM/RTC | |
104 | * | |
105 | * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located. | |
106 | * The DS1743 code assumes this condition (i.e. -- it assumes the base | |
107 | * address for the RTC registers is: | |
108 | * | |
109 | * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE | |
110 | * | |
111 | *----------------------------------------------------------------------*/ | |
112 | #define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */ | |
113 | #define CONFIG_RTC_DS174x 1 /* DS1743 RTC */ | |
114 | ||
9314cee6 | 115 | #ifdef CONFIG_ENV_IS_IN_NVRAM |
0e8d1586 JCPV |
116 | #define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */ |
117 | #define CONFIG_ENV_ADDR \ | |
118 | (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CONFIG_ENV_SIZE) | |
9314cee6 | 119 | #endif /* CONFIG_ENV_IS_IN_NVRAM */ |
8a316c9b | 120 | |
0e6d798c WD |
121 | /*----------------------------------------------------------------------- |
122 | * FLASH related | |
123 | *----------------------------------------------------------------------*/ | |
124 | #define CFG_MAX_FLASH_BANKS 3 /* number of banks */ | |
125 | #define CFG_MAX_FLASH_SECT 64 /* sectors per device */ | |
126 | ||
127 | #undef CFG_FLASH_CHECKSUM | |
128 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
129 | #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
130 | ||
8a316c9b SR |
131 | #define CFG_FLASH_ADDR0 0x5555 |
132 | #define CFG_FLASH_ADDR1 0x2aaa | |
133 | #define CFG_FLASH_WORD_SIZE unsigned char | |
134 | ||
5a1aceb0 | 135 | #ifdef CONFIG_ENV_IS_IN_FLASH |
0e8d1586 JCPV |
136 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ |
137 | #define CONFIG_ENV_ADDR (CFG_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) | |
138 | #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ | |
8a316c9b SR |
139 | |
140 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
141 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) |
142 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
5a1aceb0 | 143 | #endif /* CONFIG_ENV_IS_IN_FLASH */ |
8a316c9b | 144 | |
0e6d798c WD |
145 | /*----------------------------------------------------------------------- |
146 | * DDR SDRAM | |
147 | *----------------------------------------------------------------------*/ | |
fa1aef15 | 148 | #define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ |
42dfe7a1 | 149 | #define SPD_EEPROM_ADDRESS {0x53,0x52} /* SPD i2c spd addresses */ |
fa1aef15 | 150 | #define CONFIG_PROG_SDRAM_TLB 1 /* setup SDRAM TLB's dynamically*/ |
0e6d798c WD |
151 | |
152 | /*----------------------------------------------------------------------- | |
153 | * I2C | |
154 | *----------------------------------------------------------------------*/ | |
0e6d798c | 155 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
4f92ed5f SR |
156 | |
157 | #define CFG_I2C_MULTI_EEPROMS | |
158 | #define CFG_I2C_EEPROM_ADDR (0xa8>>1) | |
159 | #define CFG_I2C_EEPROM_ADDR_LEN 1 | |
160 | #define CFG_EEPROM_PAGE_WRITE_ENABLE | |
161 | #define CFG_EEPROM_PAGE_WRITE_BITS 3 | |
162 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
0e6d798c | 163 | |
72675dc6 SR |
164 | /* |
165 | * Default environment variables | |
166 | */ | |
8a316c9b | 167 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
72675dc6 SR |
168 | CONFIG_AMCC_DEF_ENV \ |
169 | CONFIG_AMCC_DEF_ENV_PPC \ | |
170 | CONFIG_AMCC_DEF_ENV_NOR_UPD \ | |
8a316c9b SR |
171 | "kernel_addr=fff00000\0" \ |
172 | "ramdisk_addr=fff10000\0" \ | |
8a316c9b | 173 | "" |
8a316c9b | 174 | |
0e6d798c | 175 | #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ |
42dfe7a1 WD |
176 | #define CONFIG_PHY1_ADDR 2 |
177 | #define CONFIG_PHY2_ADDR 0x10 | |
178 | #define CONFIG_PHY3_ADDR 0x18 | |
d6c61aab SR |
179 | #define CONFIG_HAS_ETH0 |
180 | #define CONFIG_HAS_ETH1 | |
181 | #define CONFIG_HAS_ETH2 | |
182 | #define CONFIG_HAS_ETH3 | |
42dfe7a1 | 183 | #define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */ |
6fb6af6d | 184 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ |
d6c61aab SR |
185 | #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ |
186 | #define CONFIG_PHY_RESET_DELAY 1000 | |
a5cb2309 | 187 | |
7f5c0157 | 188 | /* |
72675dc6 | 189 | * Commands additional to the ones defined in amcc-common.h |
7f5c0157 | 190 | */ |
a5cb2309 | 191 | #define CONFIG_CMD_DATE |
a5cb2309 | 192 | #define CONFIG_CMD_PCI |
a5cb2309 JL |
193 | #define CONFIG_CMD_SDRAM |
194 | #define CONFIG_CMD_SNTP | |
195 | ||
0e6d798c WD |
196 | /*----------------------------------------------------------------------- |
197 | * PCI stuff | |
198 | *----------------------------------------------------------------------- | |
199 | */ | |
200 | /* General PCI */ | |
8a316c9b SR |
201 | #define CONFIG_PCI /* include pci support */ |
202 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
42dfe7a1 WD |
203 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
204 | #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ | |
0e6d798c WD |
205 | |
206 | /* Board-specific PCI */ | |
8a316c9b | 207 | #define CFG_PCI_TARGET_INIT /* let board init pci target */ |
0e6d798c | 208 | |
8a316c9b | 209 | #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ |
42dfe7a1 | 210 | #define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ |
0e6d798c | 211 | |
0e6d798c | 212 | #endif /* __CONFIG_H */ |