[people/ms/u-boot.git] / include / configs / ocotea.h

/*
 * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
 *
 * (C) Copyright 2005
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/************************************************************************
 * 1 March 2004	 Travis B. Sawyer <tsawyer@sandburst.com>
 * Adapted to current Das U-Boot source
 ***********************************************************************/


/************************************************************************
 * OCOTEA.h - configuration for AMCC 440GX Ref (Ocotea)
 ***********************************************************************/

#ifndef __CONFIG_H
#define __CONFIG_H

/*-----------------------------------------------------------------------
 * High Level Configuration Options
 *----------------------------------------------------------------------*/
#define CONFIG_OCOTEA		1	    /* Board is ebony		*/
#define CONFIG_440GX		1	    /* Specifc GX support	*/
#define CONFIG_440		1	    /* ... PPC440 family	*/
#define CONFIG_4xx		1	    /* ... PPC4xx family	*/
#define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_pre_init	*/
#define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/

#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000

/*
 * Include common defines/options for all AMCC eval boards
 */
#define CONFIG_HOSTNAME		ocotea
#include "amcc-common.h"

/*-----------------------------------------------------------------------
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_FLASH_BASE	    0xff800000	    /* start of FLASH		*/
#define CONFIG_SYS_PCI_MEMBASE	    0x80000000	    /* mapped pci memory	*/
#define CONFIG_SYS_ISRAM_BASE	    0xc0000000	    /* internal SRAM		*/
#define CONFIG_SYS_PCI_BASE	    0xd0000000	    /* internal PCI regs	*/

#define CONFIG_SYS_FPGA_BASE	    (CONFIG_SYS_PERIPHERAL_BASE + 0x08300000)
#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)

/*-----------------------------------------------------------------------
 * Initial RAM & stack pointer (placed in internal SRAM)
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_TEMP_STACK_OCM  1
#define CONFIG_SYS_OCM_DATA_ADDR   CONFIG_SYS_ISRAM_BASE
#define CONFIG_SYS_INIT_RAM_ADDR   CONFIG_SYS_ISRAM_BASE  /* Initial RAM address	*/
#define CONFIG_SYS_INIT_RAM_SIZE    0x2000	    /* Size of used area in RAM	*/
#define CONFIG_SYS_GBL_DATA_SIZE   128		    /* num bytes initial data	*/

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)

/*-----------------------------------------------------------------------
 * Serial Port
 *----------------------------------------------------------------------*/
#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
#define CONFIG_SYS_EXT_SERIAL_CLOCK	(1843200 * 6)	/* Ext clk @ 11.059 MHz */

/*-----------------------------------------------------------------------
 * Environment
 *----------------------------------------------------------------------*/
/*
 * Define here the location of the environment variables (FLASH or NVRAM).
 * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
 *       supported for backward compatibility.
 */
#if 1
#define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
#else
#define CONFIG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
#endif


/*-----------------------------------------------------------------------
 * NVRAM/RTC
 *
 * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
 * The DS1743 code assumes this condition (i.e. -- it assumes the base
 * address for the RTC registers is:
 *
 *	CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE
 *
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_NVRAM_SIZE	    (0x2000 - 8)    /* NVRAM size(8k)- RTC regs */
#define CONFIG_RTC_DS174x	1		    /* DS1743 RTC		*/

#ifdef CONFIG_ENV_IS_IN_NVRAM
#define CONFIG_ENV_SIZE		0x1000	    /* Size of Environment vars */
#define CONFIG_ENV_ADDR		\
	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)
#endif /* CONFIG_ENV_IS_IN_NVRAM */

/*-----------------------------------------------------------------------
 * FLASH related
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_MAX_FLASH_BANKS	3		    /* number of banks	    */
#define CONFIG_SYS_MAX_FLASH_SECT	64		    /* sectors per device   */

#undef	CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CONFIG_SYS_FLASH_ADDR0         0x5555
#define CONFIG_SYS_FLASH_ADDR1         0x2aaa
#define CONFIG_SYS_FLASH_WORD_SIZE     unsigned char

#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE	0x10000		/* size of one complete sector	*/
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
#endif /* CONFIG_ENV_IS_IN_FLASH */

/*-----------------------------------------------------------------------
 * DDR SDRAM
 *----------------------------------------------------------------------*/
#define CONFIG_SPD_EEPROM	1	/* Use SPD EEPROM for setup	*/
#define SPD_EEPROM_ADDRESS {0x53,0x52}	/* SPD i2c spd addresses	*/
#define CONFIG_PROG_SDRAM_TLB	1	/* setup SDRAM TLB's dynamically*/

/*-----------------------------------------------------------------------
 * I2C
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/

#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR	(0xa8>>1)
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10

/*
 * Default environment variables
 */
#define	CONFIG_EXTRA_ENV_SETTINGS					\
	CONFIG_AMCC_DEF_ENV						\
	CONFIG_AMCC_DEF_ENV_PPC						\
	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
	"kernel_addr=fff00000\0"					\
	"ramdisk_addr=fff10000\0"					\
	""

#define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/
#define CONFIG_PHY1_ADDR	2
#define CONFIG_PHY2_ADDR	0x10
#define CONFIG_PHY3_ADDR	0x18
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#define CONFIG_HAS_ETH3
#define CONFIG_CIS8201_PHY	1	/* Enable 'special' RGMII mode for Cicada phy */
#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
#define CONFIG_PHY_RESET        1       /* reset phy upon startup         */
#define CONFIG_PHY_RESET_DELAY	1000

/*
 * Commands additional to the ones defined in amcc-common.h
 */
#define CONFIG_CMD_DATE
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_SNTP

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
/* General PCI */
#define CONFIG_PCI			/* include pci support		*/
#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
#define CONFIG_SYS_PCI_TARGBASE    0x80000000	/* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */

/* Board-specific PCI */
#define CONFIG_SYS_PCI_TARGET_INIT		/* let board init pci target    */

#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */

#endif	/* __CONFIG_H */
Commit	Line	Data
0e6d798c WD	1	/*
	2	* (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
	3	*
8a316c9b SR	4	* (C) Copyright 2005
	5	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	6	*
0e6d798c WD	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	/************************************************************************
42dfe7a1	27	* 1 March 2004 Travis B. Sawyer <tsawyer@sandburst.com>
0e6d798c WD	28	* Adapted to current Das U-Boot source
	29	***********************************************************************/
	30
	31
	32	/************************************************************************
0c8721a4	33	* OCOTEA.h - configuration for AMCC 440GX Ref (Ocotea)
0e6d798c WD	34	***********************************************************************/
	35
	36	#ifndef __CONFIG_H
	37	#define __CONFIG_H
	38
	39	/*-----------------------------------------------------------------------
	40	* High Level Configuration Options
	41	----------------------------------------------------------------------/
	42	#define CONFIG_OCOTEA 1 /* Board is ebony */
846b0dd2	43	#define CONFIG_440GX 1 /* Specifc GX support */
efa35cf1	44	#define CONFIG_440 1 /* ... PPC440 family */
0e6d798c WD	45	#define CONFIG_4xx 1 /* ... PPC4xx family */
0e6d798c WD	46	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
0e6d798c WD	47	#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
0e6d798c WD	48
2ae18241 WD	49	#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
2ae18241 WD	50
72675dc6 SR	51	/*
	52	* Include common defines/options for all AMCC eval boards
	53	*/
	54	#define CONFIG_HOSTNAME ocotea
	55	#include "amcc-common.h"
	56
0e6d798c WD	57	/*-----------------------------------------------------------------------
	58	* Base addresses -- Note these are effective addresses where the
	59	* actual resources get mapped (not physical addresses)
	60	----------------------------------------------------------------------/
6d0f6bcf JCPV	61	#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH */
6d0f6bcf JCPV	62	#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
6d0f6bcf JCPV	63	#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
6d0f6bcf JCPV	64	#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
0e6d798c	65
6d0f6bcf JCPV	66	#define CONFIG_SYS_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08300000)
6d0f6bcf JCPV	67	#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
0e6d798c WD	68
	69	/*-----------------------------------------------------------------------
	70	* Initial RAM & stack pointer (placed in internal SRAM)
	71	----------------------------------------------------------------------/
6d0f6bcf JCPV	72	#define CONFIG_SYS_TEMP_STACK_OCM 1
	73	#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
	74	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
553f0982	75	#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
6d0f6bcf	76	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
0e6d798c	77
553f0982	78	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
800eb096	79	#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
0e6d798c	80
0e6d798c WD	81	/*-----------------------------------------------------------------------
	82	* Serial Port
	83	----------------------------------------------------------------------/
550650dd	84	#define CONFIG_CONS_INDEX 1 /* Use UART0 */
6d0f6bcf	85	#define CONFIG_SYS_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */
0e6d798c	86
8a316c9b SR	87	/*-----------------------------------------------------------------------
	88	* Environment
	89	----------------------------------------------------------------------/
	90	/*
	91	* Define here the location of the environment variables (FLASH or NVRAM).
	92	* Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
	93	* supported for backward compatibility.
	94	*/
	95	#if 1
5a1aceb0	96	#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
8a316c9b	97	#else
9314cee6	98	#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
8a316c9b SR	99	#endif
	100
	101
0e6d798c WD	102	/*-----------------------------------------------------------------------
	103	* NVRAM/RTC
	104	*
	105	* NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
	106	* The DS1743 code assumes this condition (i.e. -- it assumes the base
	107	* address for the RTC registers is:
	108	*
6d0f6bcf	109	* CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE
0e6d798c WD	110	*
0e6d798c WD	111	----------------------------------------------------------------------/
6d0f6bcf	112	#define CONFIG_SYS_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */
0e6d798c WD	113	#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
0e6d798c WD	114
9314cee6	115	#ifdef CONFIG_ENV_IS_IN_NVRAM
0e8d1586 JCPV	116	#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */
0e8d1586 JCPV	117	#define CONFIG_ENV_ADDR \
6d0f6bcf	118	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)
9314cee6	119	#endif /* CONFIG_ENV_IS_IN_NVRAM */
8a316c9b	120
0e6d798c WD	121	/*-----------------------------------------------------------------------
	122	* FLASH related
	123	----------------------------------------------------------------------/
6d0f6bcf JCPV	124	#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* number of banks */
6d0f6bcf JCPV	125	#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
0e6d798c	126
6d0f6bcf JCPV	127	#undef CONFIG_SYS_FLASH_CHECKSUM
	128	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	129	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
0e6d798c	130
6d0f6bcf JCPV	131	#define CONFIG_SYS_FLASH_ADDR0 0x5555
	132	#define CONFIG_SYS_FLASH_ADDR1 0x2aaa
	133	#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char
8a316c9b	134
5a1aceb0	135	#ifdef CONFIG_ENV_IS_IN_FLASH
0e8d1586	136	#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
6d0f6bcf	137	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
0e8d1586	138	#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
8a316c9b SR	139
8a316c9b SR	140	/* Address and size of Redundant Environment Sector */
0e8d1586 JCPV	141	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
0e8d1586 JCPV	142	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
5a1aceb0	143	#endif /* CONFIG_ENV_IS_IN_FLASH */
8a316c9b	144
0e6d798c WD	145	/*-----------------------------------------------------------------------
	146	* DDR SDRAM
	147	----------------------------------------------------------------------/
fa1aef15	148	#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
42dfe7a1	149	#define SPD_EEPROM_ADDRESS {0x53,0x52} /* SPD i2c spd addresses */
fa1aef15	150	#define CONFIG_PROG_SDRAM_TLB 1 /* setup SDRAM TLB's dynamically*/
0e6d798c WD	151
	152	/*-----------------------------------------------------------------------
	153	* I2C
	154	----------------------------------------------------------------------/
6d0f6bcf	155	#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
4f92ed5f	156
6d0f6bcf JCPV	157	#define CONFIG_SYS_I2C_MULTI_EEPROMS
	158	#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
	159	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	160	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	161	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
0e6d798c	162
72675dc6 SR	163	/*
	164	* Default environment variables
	165	*/
8a316c9b	166	#define CONFIG_EXTRA_ENV_SETTINGS \
72675dc6 SR	167	CONFIG_AMCC_DEF_ENV \
	168	CONFIG_AMCC_DEF_ENV_PPC \
	169	CONFIG_AMCC_DEF_ENV_NOR_UPD \
8a316c9b SR	170	"kernel_addr=fff00000\0" \
8a316c9b SR	171	"ramdisk_addr=fff10000\0" \
8a316c9b	172	""
8a316c9b	173
0e6d798c	174	#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
42dfe7a1 WD	175	#define CONFIG_PHY1_ADDR 2
	176	#define CONFIG_PHY2_ADDR 0x10
	177	#define CONFIG_PHY3_ADDR 0x18
d6c61aab SR	178	#define CONFIG_HAS_ETH0
	179	#define CONFIG_HAS_ETH1
	180	#define CONFIG_HAS_ETH2
	181	#define CONFIG_HAS_ETH3
42dfe7a1	182	#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
6fb6af6d	183	#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
d6c61aab SR	184	#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
d6c61aab SR	185	#define CONFIG_PHY_RESET_DELAY 1000
a5cb2309	186
7f5c0157	187	/*
72675dc6	188	* Commands additional to the ones defined in amcc-common.h
7f5c0157	189	*/
a5cb2309	190	#define CONFIG_CMD_DATE
a5cb2309	191	#define CONFIG_CMD_PCI
a5cb2309 JL	192	#define CONFIG_CMD_SDRAM
	193	#define CONFIG_CMD_SNTP
	194
0e6d798c WD	195	/*-----------------------------------------------------------------------
	196	* PCI stuff
	197	*-----------------------------------------------------------------------
	198	*/
	199	/* General PCI */
8a316c9b SR	200	#define CONFIG_PCI /* include pci support */
8a316c9b SR	201	#define CONFIG_PCI_PNP /* do pci plug-and-play */
42dfe7a1	202	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
6d0f6bcf	203	#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
0e6d798c WD	204
0e6d798c WD	205	/* Board-specific PCI */
6d0f6bcf	206	#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
0e6d798c	207
6d0f6bcf JCPV	208	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
6d0f6bcf JCPV	209	#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
0e6d798c	210
0e6d798c	211	#endif /* __CONFIG_H */