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73eca211 PM |
1 | /* |
2 | * Copyright (C) 2014 Samsung Electronics | |
3 | * Sanghee Kim <sh0130.kim@samsung.com> | |
4 | * Piotr Wilczek <p.wilczek@samsung.com> | |
5 | * Przemyslaw Marczak <p.marczak@samsung.com> | |
6 | * | |
7 | * Configuation settings for the Odroid-U3 (EXYNOS4412) board. | |
8 | * | |
9 | * SPDX-License-Identifier: GPL-2.0+ | |
10 | */ | |
11 | ||
12 | #ifndef __CONFIG_ODROID_U3_H | |
13 | #define __CONFIG_ODROID_U3_H | |
14 | ||
4c7bb1d2 | 15 | #include <configs/exynos4-common.h> |
73eca211 | 16 | |
73eca211 PM |
17 | #define CONFIG_SYS_L2CACHE_OFF |
18 | #ifndef CONFIG_SYS_L2CACHE_OFF | |
19 | #define CONFIG_SYS_L2_PL310 | |
20 | #define CONFIG_SYS_PL310_BASE 0x10502000 | |
21 | #endif | |
22 | ||
23 | #define CONFIG_MACH_TYPE 4289 | |
24 | ||
25 | #define CONFIG_NR_DRAM_BANKS 8 | |
26 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 | |
27 | #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ | |
28 | #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE | |
ddb49f3a PM |
29 | /* Reserve the last 1 MiB for the secure firmware */ |
30 | #define CONFIG_SYS_MEM_TOP_HIDE (1UL << 20UL) | |
31 | #define CONFIG_TZSW_RESERVED_DRAM_SIZE CONFIG_SYS_MEM_TOP_HIDE | |
73eca211 PM |
32 | |
33 | /* memtest works on */ | |
34 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE | |
35 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) | |
36 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) | |
37 | #define CONFIG_SYS_TEXT_BASE 0x43e00000 | |
38 | ||
39 | #include <linux/sizes.h> | |
73eca211 PM |
40 | |
41 | /* select serial console configuration */ | |
42 | #define CONFIG_SERIAL1 | |
43 | #define CONFIG_BAUDRATE 115200 | |
44 | ||
45 | /* Console configuration */ | |
73eca211 | 46 | |
73eca211 PM |
47 | #define CONFIG_BOOTARGS "Please use defined boot" |
48 | #define CONFIG_BOOTCOMMAND "run autoboot" | |
49 | #define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" | |
50 | ||
51 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ | |
52 | - GENERATED_GBL_DATA_SIZE) | |
53 | ||
73eca211 PM |
54 | #define CONFIG_SYS_MONITOR_BASE 0x00000000 |
55 | ||
56 | #define CONFIG_ENV_IS_IN_MMC | |
57 | #define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV | |
58 | #define CONFIG_ENV_SIZE 4096 | |
59 | #define CONFIG_ENV_OFFSET (SZ_1K * 1280) /* 1.25 MiB offset */ | |
60 | #define CONFIG_ENV_OVERWRITE | |
61 | ||
62 | /* Partitions name */ | |
63 | #define PARTS_BOOT "boot" | |
64 | #define PARTS_ROOT "platform" | |
65 | ||
66 | #define CONFIG_DFU_ALT \ | |
67 | "uImage fat 0 1;" \ | |
68 | "zImage fat 0 1;" \ | |
69 | "Image.itb fat 0 1;" \ | |
70 | "uInitrd fat 0 1;" \ | |
71 | "exynos4412-odroidu3.dtb fat 0 1;" \ | |
72 | "exynos4412-odroidx2.dtb fat 0 1;" \ | |
73 | ""PARTS_BOOT" part 0 1;" \ | |
74 | ""PARTS_ROOT" part 0 2\0" \ | |
75 | ||
76 | #define CONFIG_SET_DFU_ALT_INFO | |
77 | #define CONFIG_SET_DFU_ALT_BUF_LEN (SZ_1K) | |
78 | ||
79 | #define CONFIG_DFU_ALT_BOOT_EMMC \ | |
80 | "u-boot raw 0x3e 0x800 mmcpart 1;" \ | |
81 | "bl1 raw 0x0 0x1e mmcpart 1;" \ | |
82 | "bl2 raw 0x1e 0x1d mmcpart 1;" \ | |
83 | "tzsw raw 0x83e 0x138 mmcpart 1\0" | |
84 | ||
85 | #define CONFIG_DFU_ALT_BOOT_SD \ | |
86 | "u-boot raw 0x3f 0x800;" \ | |
87 | "bl1 raw 0x1 0x1e;" \ | |
88 | "bl2 raw 0x1f 0x1d;" \ | |
89 | "tzsw raw 0x83f 0x138\0" | |
90 | ||
91 | /* | |
92 | * Bootable media layout: | |
93 | * dev: SD eMMC(part boot) | |
94 | * BL1 1 0 | |
95 | * BL2 31 30 | |
96 | * UBOOT 63 62 | |
97 | * TZSW 2111 2110 | |
98 | * ENV 2560 2560(part user) | |
99 | * | |
100 | * MBR Primary partiions: | |
101 | * Num Name Size Offset | |
102 | * 1. BOOT: 100MiB 2MiB | |
103 | * 2. ROOT: - | |
104 | */ | |
105 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
8e34a74d GG |
106 | "loadbootscript=load mmc ${mmcbootdev}:${mmcbootpart} ${scriptaddr} " \ |
107 | "boot.scr\0" \ | |
4ed50807 | 108 | "loadkernel=load mmc ${mmcbootdev}:${mmcbootpart} ${kerneladdr} " \ |
73eca211 | 109 | "${kernelname}\0" \ |
4ed50807 | 110 | "loadinitrd=load mmc ${mmcbootdev}:${mmcbootpart} ${initrdaddr} " \ |
73eca211 | 111 | "${initrdname}\0" \ |
4ed50807 | 112 | "loaddtb=load mmc ${mmcbootdev}:${mmcbootpart} ${fdtaddr} " \ |
73eca211 PM |
113 | "${fdtfile}\0" \ |
114 | "check_ramdisk=" \ | |
115 | "if run loadinitrd; then " \ | |
116 | "setenv initrd_addr ${initrdaddr};" \ | |
117 | "else " \ | |
118 | "setenv initrd_addr -;" \ | |
119 | "fi;\0" \ | |
120 | "check_dtb=" \ | |
121 | "if run loaddtb; then " \ | |
122 | "setenv fdt_addr ${fdtaddr};" \ | |
123 | "else " \ | |
124 | "setenv fdt_addr;" \ | |
125 | "fi;\0" \ | |
126 | "kernel_args=" \ | |
127 | "setenv bootargs root=/dev/mmcblk${mmcrootdev}p${mmcrootpart}" \ | |
128 | " rootwait ${console} ${opts}\0" \ | |
8e34a74d GG |
129 | "boot_script=" \ |
130 | "run loadbootscript;" \ | |
131 | "source ${scriptaddr}\0" \ | |
73eca211 PM |
132 | "boot_fit=" \ |
133 | "setenv kerneladdr 0x42000000;" \ | |
134 | "setenv kernelname Image.itb;" \ | |
135 | "run loadkernel;" \ | |
136 | "run kernel_args;" \ | |
137 | "bootm ${kerneladdr}#${boardname}\0" \ | |
138 | "boot_uimg=" \ | |
139 | "setenv kerneladdr 0x40007FC0;" \ | |
140 | "setenv kernelname uImage;" \ | |
141 | "run check_dtb;" \ | |
142 | "run check_ramdisk;" \ | |
143 | "run loadkernel;" \ | |
144 | "run kernel_args;" \ | |
145 | "bootm ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \ | |
146 | "boot_zimg=" \ | |
147 | "setenv kerneladdr 0x40007FC0;" \ | |
148 | "setenv kernelname zImage;" \ | |
149 | "run check_dtb;" \ | |
150 | "run check_ramdisk;" \ | |
151 | "run loadkernel;" \ | |
152 | "run kernel_args;" \ | |
153 | "bootz ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \ | |
154 | "autoboot=" \ | |
8e34a74d GG |
155 | "if test -e mmc 0 boot.scr; then; " \ |
156 | "run boot_script; " \ | |
157 | "elif test -e mmc 0 Image.itb; then; " \ | |
73eca211 PM |
158 | "run boot_fit;" \ |
159 | "elif test -e mmc 0 zImage; then; " \ | |
160 | "run boot_zimg;" \ | |
161 | "elif test -e mmc 0 uImage; then; " \ | |
162 | "run boot_uimg;" \ | |
163 | "fi;\0" \ | |
164 | "console=" CONFIG_DEFAULT_CONSOLE \ | |
165 | "mmcbootdev=0\0" \ | |
166 | "mmcbootpart=1\0" \ | |
167 | "mmcrootdev=0\0" \ | |
168 | "mmcrootpart=2\0" \ | |
169 | "bootdelay=0\0" \ | |
170 | "dfu_alt_system="CONFIG_DFU_ALT \ | |
171 | "dfu_alt_info=Please reset the board\0" \ | |
172 | "consoleon=set console console=ttySAC1,115200n8; save; reset\0" \ | |
173 | "consoleoff=set console console=ram; save; reset\0" \ | |
174 | "initrdname=uInitrd\0" \ | |
175 | "initrdaddr=42000000\0" \ | |
8e34a74d | 176 | "scriptaddr=0x42000000\0" \ |
73eca211 PM |
177 | "fdtaddr=40800000\0" |
178 | ||
179 | /* I2C */ | |
73eca211 PM |
180 | #define CONFIG_SYS_I2C_S3C24X0 |
181 | #define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 | |
182 | #define CONFIG_SYS_I2C_S3C24X0_SLAVE 0 | |
73eca211 | 183 | |
73eca211 PM |
184 | /* GPT */ |
185 | #define CONFIG_RANDOM_UUID | |
186 | ||
187 | /* Security subsystem - enable hw_rand() */ | |
188 | #define CONFIG_EXYNOS_ACE_SHA | |
189 | #define CONFIG_LIB_HW_RAND | |
190 | ||
6a23c653 | 191 | /* USB */ |
6a23c653 SR |
192 | #define CONFIG_USB_EHCI |
193 | #define CONFIG_USB_EHCI_EXYNOS | |
6a23c653 SR |
194 | |
195 | #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 | |
6a23c653 SR |
196 | #define CONFIG_USB_HOST_ETHER |
197 | #define CONFIG_USB_ETHER_SMSC95XX | |
198 | ||
73eca211 PM |
199 | /* |
200 | * Supported Odroid boards: X3, U3 | |
201 | * TODO: Add Odroid X support | |
202 | */ | |
203 | #define CONFIG_MISC_COMMON | |
204 | #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG | |
205 | #define CONFIG_BOARD_TYPES | |
206 | #define CONFIG_MISC_INIT_R | |
207 | ||
208 | #undef CONFIG_REVISION_TAG | |
209 | ||
210 | #endif /* __CONFIG_H */ |