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2e5983d2 WD |
1 | /* |
2 | * | |
3 | * BRIEF MODULE DESCRIPTION | |
4 | * OMAP hardware map | |
5 | * | |
6 | * Copyright (C) 2001 RidgeRun, Inc. (http://www.ridgerun.com) | |
7 | * Author: RidgeRun, Inc. | |
8 | * Greg Lonnon (glonnon@ridgerun.com) or info@ridgerun.com | |
9 | * | |
1a459660 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
2e5983d2 WD |
11 | */ |
12 | ||
1ace4022 | 13 | #include <linux/sizes.h> |
2e5983d2 WD |
14 | |
15 | /* | |
16 | There are 2 sets of general I/O --> | |
17 | 1. GPIO (shared between ARM & DSP, configured by ARM) | |
18 | 2. MPUIO which can be used only by the ARM. | |
19 | ||
20 | Base address FFFB:5000 is where the ARM accesses the MPUIO control registers | |
21 | (see 7.2.2 of the TRM for MPUIO reg definitions). | |
22 | ||
23 | Base address E101:5000 is reserved for ARM access of the same MPUIO control | |
24 | regs, but via the DSP I/O map. This address is unavailable on 1510. | |
25 | ||
26 | Base address FFFC:E000 is where the ARM accesses the GPIO config registers | |
27 | directly via its own peripheral bus. | |
28 | ||
29 | Base address E101:E000 is where the ARM can access the same GPIO config | |
30 | registers, but the access takes place through the ARM port interface (called | |
31 | API or MPUI) via the DSP's peripheral bus (DSP I/O space). | |
32 | ||
33 | Therefore, the ARM should setup the GPIO regs thru the FFFC:E000 addresses | |
34 | instead of the E101:E000 addresses. The DSP has only read access of the pin | |
35 | control register, so this may explain the inability to write to E101:E018. | |
36 | Try accessing pin control reg at FFFC:E018. | |
37 | */ | |
38 | #define OMAP1510_GPIO_BASE 0xfffce000 | |
39 | #define OMAP1510_GPIO_START OMAP1510_GPIO_BASE | |
40 | #define OMAP1510_GPIO_SIZE SZ_4K | |
41 | ||
42 | #define OMAP1510_MCBSP1_BASE 0xE1011000 | |
43 | #define OMAP1510_MCBSP1_SIZE SZ_4K | |
44 | #define OMAP1510_MCBSP1_START 0xE1011000 | |
45 | ||
46 | #define OMAP1510_MCBSP2_BASE 0xFFFB1000 | |
47 | ||
48 | #define OMAP1510_MCBSP3_BASE 0xE1017000 | |
49 | #define OMAP1510_MCBSP3_SIZE SZ_4K | |
50 | #define OMAP1510_MCBSP3_START 0xE1017000 | |
51 | ||
52 | /* | |
53 | * Where's the flush address (for flushing D and I cache?) | |
54 | */ | |
55 | #define FLUSH_BASE 0xdf000000 | |
56 | #define FLUSH_BASE_PHYS 0x00000000 | |
57 | ||
58 | #ifndef __ASSEMBLER__ | |
59 | ||
60 | #define PCIO_BASE 0 | |
61 | ||
62 | /* | |
63 | * RAM definitions | |
64 | */ | |
65 | #define MAPTOPHYS(a) ((unsigned long)(a) - PAGE_OFFSET) | |
66 | #define KERNTOPHYS(a) ((unsigned long)(&a)) | |
67 | #define KERNEL_BASE (0x10008000) | |
68 | #endif | |
69 | ||
70 | /* macro to get at IO space when running virtually */ | |
71 | #define IO_ADDRESS(x) ((x)) | |
72 | ||
73 | /* ---------------------------------------------------------------------------- | |
74 | * OMAP1510 system registers | |
75 | * ---------------------------------------------------------------------------- | |
76 | */ | |
77 | ||
78 | #define OMAP1510_UART1_BASE 0xfffb0000 /* "BLUETOOTH-UART" */ | |
79 | #define OMAP1510_UART2_BASE 0xfffb0800 /* "MODEM-UART" */ | |
80 | #define OMAP1510_RTC_BASE 0xfffb4800 /* RTC */ | |
81 | #define OMAP1510_UART3_BASE 0xfffb9800 /* Shared MPU/DSP UART */ | |
82 | #define OMAP1510_COM_MCBSP2_BASE 0xffff1000 /* Com McBSP2 */ | |
83 | #define OMAP1510_AUDIO_MCBSP_BASE 0xffff1800 /* Audio McBSP2 */ | |
84 | #define OMAP1510_ARMIO_BASE 0xfffb5000 /* keyboard/gpio */ | |
85 | ||
86 | /* | |
87 | * OMAP1510 UART3 Registers | |
88 | */ | |
89 | ||
90 | #define OMAP_MPU_UART3_BASE 0xFFFB9800 /* UART3 through MPU bus */ | |
91 | ||
92 | /* UART3 Registers Maping through MPU bus */ | |
93 | ||
94 | #define UART3_RHR (OMAP_MPU_UART3_BASE + 0) | |
95 | #define UART3_THR (OMAP_MPU_UART3_BASE + 0) | |
96 | #define UART3_DLL (OMAP_MPU_UART3_BASE + 0) | |
97 | #define UART3_IER (OMAP_MPU_UART3_BASE + 4) | |
98 | #define UART3_DLH (OMAP_MPU_UART3_BASE + 4) | |
99 | #define UART3_IIR (OMAP_MPU_UART3_BASE + 8) | |
100 | #define UART3_FCR (OMAP_MPU_UART3_BASE + 8) | |
101 | #define UART3_EFR (OMAP_MPU_UART3_BASE + 8) | |
102 | #define UART3_LCR (OMAP_MPU_UART3_BASE + 0x0C) | |
103 | #define UART3_MCR (OMAP_MPU_UART3_BASE + 0x10) | |
104 | #define UART3_XON1_ADDR1 (OMAP_MPU_UART3_BASE + 0x10) | |
105 | #define UART3_XON2_ADDR2 (OMAP_MPU_UART3_BASE + 0x14) | |
106 | #define UART3_LSR (OMAP_MPU_UART3_BASE + 0x14) | |
107 | #define UART3_TCR (OMAP_MPU_UART3_BASE + 0x18) | |
108 | #define UART3_MSR (OMAP_MPU_UART3_BASE + 0x18) | |
109 | #define UART3_XOFF1 (OMAP_MPU_UART3_BASE + 0x18) | |
110 | #define UART3_XOFF2 (OMAP_MPU_UART3_BASE + 0x1C) | |
111 | #define UART3_SPR (OMAP_MPU_UART3_BASE + 0x1C) | |
112 | #define UART3_TLR (OMAP_MPU_UART3_BASE + 0x1C) | |
113 | #define UART3_MDR1 (OMAP_MPU_UART3_BASE + 0x20) | |
114 | #define UART3_MDR2 (OMAP_MPU_UART3_BASE + 0x24) | |
115 | #define UART3_SFLSR (OMAP_MPU_UART3_BASE + 0x28) | |
116 | #define UART3_TXFLL (OMAP_MPU_UART3_BASE + 0x28) | |
117 | #define UART3_RESUME (OMAP_MPU_UART3_BASE + 0x2C) | |
118 | #define UART3_TXFLH (OMAP_MPU_UART3_BASE + 0x2C) | |
119 | #define UART3_SFREGL (OMAP_MPU_UART3_BASE + 0x30) | |
120 | #define UART3_RXFLL (OMAP_MPU_UART3_BASE + 0x30) | |
121 | #define UART3_SFREGH (OMAP_MPU_UART3_BASE + 0x34) | |
122 | #define UART3_RXFLH (OMAP_MPU_UART3_BASE + 0x34) | |
123 | #define UART3_BLR (OMAP_MPU_UART3_BASE + 0x38) | |
124 | #define UART3_ACREG (OMAP_MPU_UART3_BASE + 0x3C) | |
125 | #define UART3_DIV16 (OMAP_MPU_UART3_BASE + 0x3C) | |
126 | #define UART3_SCR (OMAP_MPU_UART3_BASE + 0x40) | |
127 | #define UART3_SSR (OMAP_MPU_UART3_BASE + 0x44) | |
128 | #define UART3_EBLR (OMAP_MPU_UART3_BASE + 0x48) | |
129 | #define UART3_OSC_12M_SEL (OMAP_MPU_UART3_BASE + 0x4C) | |
130 | #define UART3_MVR (OMAP_MPU_UART3_BASE + 0x50) | |
131 | ||
132 | /* | |
133 | * Configuration Registers | |
134 | */ | |
135 | #define FUNC_MUX_CTRL_0 0xfffe1000 | |
136 | #define FUNC_MUX_CTRL_1 0xfffe1004 | |
137 | #define FUNC_MUX_CTRL_2 0xfffe1008 | |
138 | #define COMP_MODE_CTRL_0 0xfffe100c | |
139 | #define FUNC_MUX_CTRL_3 0xfffe1010 | |
140 | #define FUNC_MUX_CTRL_4 0xfffe1014 | |
141 | #define FUNC_MUX_CTRL_5 0xfffe1018 | |
142 | #define FUNC_MUX_CTRL_6 0xfffe101C | |
143 | #define FUNC_MUX_CTRL_7 0xfffe1020 | |
144 | #define FUNC_MUX_CTRL_8 0xfffe1024 | |
145 | #define FUNC_MUX_CTRL_9 0xfffe1028 | |
146 | #define FUNC_MUX_CTRL_A 0xfffe102C | |
147 | #define FUNC_MUX_CTRL_B 0xfffe1030 | |
148 | #define FUNC_MUX_CTRL_C 0xfffe1034 | |
149 | #define FUNC_MUX_CTRL_D 0xfffe1038 | |
150 | #define PULL_DWN_CTRL_0 0xfffe1040 | |
151 | #define PULL_DWN_CTRL_1 0xfffe1044 | |
152 | #define PULL_DWN_CTRL_2 0xfffe1048 | |
153 | #define PULL_DWN_CTRL_3 0xfffe104c | |
154 | #define GATE_INH_CTRL_0 0xfffe1050 | |
155 | #define VOLTAGE_CTRL_0 0xfffe1060 | |
156 | #define TEST_DBG_CTRL_0 0xfffe1070 | |
157 | ||
158 | #define MOD_CONF_CTRL_0 0xfffe1080 | |
159 | ||
6f21347d WD |
160 | #ifdef CONFIG_OMAP1610 /* 1610 Configuration Register */ |
161 | ||
162 | #define USB_OTG_CTRL 0xFFFB040C | |
163 | #define USB_TRANSCEIVER_CTRL 0xFFFE1064 | |
232c150a | 164 | #define PULL_DWN_CTRL_4 0xFFFE10AC |
6f21347d WD |
165 | #define PU_PD_SEL_0 0xFFFE10B4 |
166 | #define PU_PD_SEL_1 0xFFFE10B8 | |
167 | #define PU_PD_SEL_2 0xFFFE10BC | |
168 | #define PU_PD_SEL_3 0xFFFE10C0 | |
169 | #define PU_PD_SEL_4 0xFFFE10C4 | |
170 | ||
171 | #endif | |
2e5983d2 WD |
172 | /* |
173 | * Traffic Controller Memory Interface Registers | |
174 | */ | |
175 | #define TCMIF_BASE 0xfffecc00 | |
176 | #define IMIF_PRIO (TCMIF_BASE + 0x00) | |
177 | #define EMIFS_PRIO_REG (TCMIF_BASE + 0x04) | |
178 | #define EMIFF_PRIO_REG (TCMIF_BASE + 0x08) | |
179 | #define EMIFS_CONFIG_REG (TCMIF_BASE + 0x0c) | |
180 | #define EMIFS_CS0_CONFIG (TCMIF_BASE + 0x10) | |
181 | #define EMIFS_CS1_CONFIG (TCMIF_BASE + 0x14) | |
182 | #define EMIFS_CS2_CONFIG (TCMIF_BASE + 0x18) | |
183 | #define EMIFS_CS3_CONFIG (TCMIF_BASE + 0x1c) | |
184 | #define EMIFF_SDRAM_CONFIG (TCMIF_BASE + 0x20) | |
185 | #define EMIFF_MRS (TCMIF_BASE + 0x24) | |
186 | #define TC_TIMEOUT1 (TCMIF_BASE + 0x28) | |
187 | #define TC_TIMEOUT2 (TCMIF_BASE + 0x2c) | |
188 | #define TC_TIMEOUT3 (TCMIF_BASE + 0x30) | |
189 | #define TC_ENDIANISM (TCMIF_BASE + 0x34) | |
190 | #define EMIFF_SDRAM_CONFIG_2 (TCMIF_BASE + 0x3c) | |
191 | #define EMIF_CFG_DYNAMIC_WS (TCMIF_BASE + 0x40) | |
192 | ||
193 | /* | |
194 | * LCD Panel | |
195 | */ | |
196 | #define TI925_LCD_BASE 0xFFFEC000 | |
197 | #define TI925_LCD_CONTROL (TI925_LCD_BASE) | |
198 | #define TI925_LCD_TIMING0 (TI925_LCD_BASE+0x4) | |
199 | #define TI925_LCD_TIMING1 (TI925_LCD_BASE+0x8) | |
200 | #define TI925_LCD_TIMING2 (TI925_LCD_BASE+0xc) | |
201 | #define TI925_LCD_STATUS (TI925_LCD_BASE+0x10) | |
202 | #define TI925_LCD_SUBPANEL (TI925_LCD_BASE+0x14) | |
203 | ||
204 | #define OMAP_LCD_CONTROL TI925_LCD_CONTROL | |
205 | ||
232c150a WD |
206 | /* I2C Registers */ |
207 | ||
208 | #define I2C_BASE 0xfffb3800 | |
209 | ||
210 | #define I2C_REV (I2C_BASE + 0x00) | |
211 | #define I2C_IE (I2C_BASE + 0x04) | |
212 | #define I2C_STAT (I2C_BASE + 0x08) | |
213 | #define I2C_IV (I2C_BASE + 0x0c) | |
214 | #define I2C_BUF (I2C_BASE + 0x14) | |
215 | #define I2C_CNT (I2C_BASE + 0x18) | |
216 | #define I2C_DATA (I2C_BASE + 0x1c) | |
217 | #define I2C_CON (I2C_BASE + 0x24) | |
218 | #define I2C_OA (I2C_BASE + 0x28) | |
219 | #define I2C_SA (I2C_BASE + 0x2c) | |
220 | #define I2C_PSC (I2C_BASE + 0x30) | |
221 | #define I2C_SCLL (I2C_BASE + 0x34) | |
222 | #define I2C_SCLH (I2C_BASE + 0x38) | |
223 | #define I2C_SYSTEST (I2C_BASE + 0x3c) | |
224 | ||
225 | /* I2C masks */ | |
226 | ||
227 | /* I2C Interrupt Enable Register (I2C_IE): */ | |
228 | ||
229 | #define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ | |
230 | #define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ | |
231 | #define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ | |
232 | #define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ | |
233 | #define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ | |
234 | ||
235 | /* I2C Status Register (I2C_STAT): */ | |
236 | ||
237 | #define I2C_STAT_SBD (1 << 15) /* Single byte data */ | |
238 | #define I2C_STAT_BB (1 << 12) /* Bus busy */ | |
239 | #define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ | |
240 | #define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ | |
241 | #define I2C_STAT_AAS (1 << 9) /* Address as slave */ | |
242 | #define I2C_STAT_AD0 (1 << 8) /* Address zero */ | |
243 | #define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ | |
244 | #define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ | |
245 | #define I2C_STAT_ARDY (1 << 2) /* Register access ready */ | |
246 | #define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ | |
247 | #define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ | |
248 | ||
249 | /* I2C Interrupt Vector Register (I2C_IV): */ | |
250 | ||
251 | /* I2C Interrupt Code Register (I2C_INTCODE): */ | |
252 | ||
253 | #define I2C_INTCODE_MASK 7 | |
254 | #define I2C_INTCODE_NONE 0 | |
255 | #define I2C_INTCODE_AL 1 /* Arbitration lost */ | |
256 | #define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */ | |
257 | #define I2C_INTCODE_ARDY 3 /* Register access ready */ | |
258 | #define I2C_INTCODE_RRDY 4 /* Rcv data ready */ | |
259 | #define I2C_INTCODE_XRDY 5 /* Xmit data ready */ | |
260 | ||
261 | /* I2C Buffer Configuration Register (I2C_BUF): */ | |
262 | ||
263 | #define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */ | |
264 | #define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */ | |
265 | ||
266 | /* I2C Configuration Register (I2C_CON): */ | |
267 | ||
268 | #define I2C_CON_EN (1 << 15) /* I2C module enable */ | |
269 | #define I2C_CON_BE (1 << 14) /* Big endian mode */ | |
270 | #define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */ | |
271 | #define I2C_CON_MST (1 << 10) /* Master/slave mode */ | |
272 | #define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode (master mode only) */ | |
273 | #define I2C_CON_XA (1 << 8) /* Expand address */ | |
274 | #define I2C_CON_RM (1 << 2) /* Repeat mode (master mode only) */ | |
275 | #define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */ | |
276 | #define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */ | |
277 | ||
278 | /* I2C System Test Register (I2C_SYSTEST): */ | |
279 | ||
280 | #define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ | |
281 | #define I2C_SYSTEST_FREE (1 << 14) /* Free running mode (on breakpoint) */ | |
282 | #define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ | |
283 | #define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ | |
284 | #define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */ | |
285 | #define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */ | |
286 | #define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */ | |
287 | #define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */ | |
288 | ||
2e5983d2 WD |
289 | /* |
290 | * MMC/SD Host Controller Registers | |
291 | */ | |
292 | ||
293 | #define OMAP_MMC_CMD 0xFFFB7800 /* MMC Command */ | |
294 | #define OMAP_MMC_ARGL 0xFFFB7804 /* MMC argument low */ | |
295 | #define OMAP_MMC_ARGH 0xFFFB7808 /* MMC argument high */ | |
296 | #define OMAP_MMC_CON 0xFFFB780C /* MMC system configuration */ | |
297 | #define OMAP_MMC_STAT 0xFFFB7810 /* MMC status */ | |
298 | #define OMAP_MMC_IE 0xFFFB7814 /* MMC system interrupt enable */ | |
299 | #define OMAP_MMC_CTO 0xFFFB7818 /* MMC command time-out */ | |
300 | #define OMAP_MMC_DTO 0xFFFB781C /* MMC data time-out */ | |
301 | #define OMAP_MMC_DATA 0xFFFB7820 /* MMC TX/RX FIFO data */ | |
302 | #define OMAP_MMC_BLEN 0xFFFB7824 /* MMC block length */ | |
303 | #define OMAP_MMC_NBLK 0xFFFB7828 /* MMC number of blocks */ | |
304 | #define OMAP_MMC_BUF 0xFFFB782C /* MMC buffer configuration */ | |
305 | #define OMAP_MMC_SPI 0xFFFB7830 /* MMC serial port interface */ | |
306 | #define OMAP_MMC_SDIO 0xFFFB7834 /* MMC SDIO mode configuration */ | |
307 | #define OMAP_MMC_SYST 0xFFFB7838 /* MMC system test */ | |
308 | #define OMAP_MMC_REV 0xFFFB783C /* MMC module version */ | |
309 | #define OMAP_MMC_RSP0 0xFFFB7840 /* MMC command response 0 */ | |
310 | #define OMAP_MMC_RSP1 0xFFFB7844 /* MMC command response 1 */ | |
311 | #define OMAP_MMC_RSP2 0xFFFB7848 /* MMC command response 2 */ | |
312 | #define OMAP_MMC_RSP3 0xFFFB784C /* MMC command response 3 */ | |
313 | #define OMAP_MMC_RSP4 0xFFFB7850 /* MMC command response 4 */ | |
314 | #define OMAP_MMC_RSP5 0xFFFB7854 /* MMC command response 5 */ | |
315 | #define OMAP_MMC_RSP6 0xFFFB7858 /* MMC command response 6 */ | |
316 | #define OMAP_MMC_RSP7 0xFFFB785C /* MMC command response 4 */ | |
317 | ||
318 | /* MMC masks */ | |
319 | ||
320 | #define OMAP_MMC_END_OF_CMD (1 << 0) /* End of command phase */ | |
321 | #define OMAP_MMC_CARD_BUSY (1 << 2) /* Card enter busy state */ | |
322 | #define OMAP_MMC_BLOCK_RS (1 << 3) /* Block received/sent */ | |
323 | #define OMAP_MMC_EOF_BUSY (1 << 4) /* Card exit busy state */ | |
324 | #define OMAP_MMC_DATA_TIMEOUT (1 << 5) /* Data response time-out */ | |
325 | #define OMAP_MMC_DATA_CRC (1 << 6) /* Date CRC error */ | |
326 | #define OMAP_MMC_CMD_TIMEOUT (1 << 7) /* Command response time-out */ | |
327 | #define OMAP_MMC_CMD_CRC (1 << 8) /* Command CRC error */ | |
328 | #define OMAP_MMC_A_FULL (1 << 10) /* Buffer almost full */ | |
329 | #define OMAP_MMC_A_EMPTY (1 << 11) /* Buffer almost empty */ | |
330 | #define OMAP_MMC_OCR_BUSY (1 << 12) /* OCR busy */ | |
331 | #define OMAP_MMC_CARD_IRQ (1 << 13) /* Card IRQ received */ | |
332 | #define OMAP_MMC_CARD_ERR (1 << 14) /* Card status error in response */ | |
333 | ||
334 | /* 2.9.2 MPUI Interface Registers FFFE:C900 */ | |
335 | ||
336 | #define MPUI_CTRL_REG (volatile __u32 *)(0xfffec900) | |
337 | #define MPUI_DEBUG_ADDR (volatile __u32 *)(0xfffec904) | |
338 | #define MPUI_DEBUG_DATA (volatile __u32 *)(0xfffec908) | |
339 | #define MPUI_DEBUG_FLAG (volatile __u16 *)(0xfffec90c) | |
340 | #define MPUI_STATUS_REG (volatile __u16 *)(0xfffec910) | |
341 | #define MPUI_DSP_STATUS_REG (volatile __u16 *)(0xfffec914) | |
342 | #define MPUI_DSP_BOOT_CONFIG (volatile __u16 *)(0xfffec918) | |
343 | #define MPUI_DSP_API_CONFIG (volatile __u16 *)(0xfffec91c) | |
344 | ||
345 | /* 2.9.6 Traffic Controller Memory Interface Registers: */ | |
346 | #define OMAP_IMIF_PRIO_REG 0xfffecc00 | |
347 | #define OMAP_EMIFS_PRIO_REG 0xfffecc04 | |
348 | #define OMAP_EMIFF_PRIO_REG 0xfffecc08 | |
349 | #define OMAP_EMIFS_CONFIG_REG 0xfffecc0c | |
350 | #define OMAP_EMIFS_CS0_CONFIG 0xfffecc10 | |
351 | #define OMAP_EMIFS_CS1_CONFIG 0xfffecc14 | |
352 | #define OMAP_EMIFS_CS2_CONFIG 0xfffecc18 | |
353 | #define OMAP_EMIFS_CS3_CONFIG 0xfffecc1c | |
354 | #define OMAP_EMIFF_SDRAM_CONFIG 0xfffecc20 | |
355 | #define OMAP_EMIFF_MRS 0xfffecc24 | |
356 | #define OMAP_TIMEOUT1 0xfffecc28 | |
357 | #define OMAP_TIMEOUT2 0xfffecc2c | |
358 | #define OMAP_TIMEOUT3 0xfffecc30 | |
359 | #define OMAP_ENDIANISM 0xfffecc34 | |
360 | ||
361 | /* 2.9.10 EMIF Slow Interface Configuration Register (EMIFS_CONFIG_REG): */ | |
362 | #define OMAP_EMIFS_CONFIG_FR (1 << 4) | |
363 | #define OMAP_EMIFS_CONFIG_PDE (1 << 3) | |
364 | #define OMAP_EMIFS_CONFIG_PWD_EN (1 << 2) | |
365 | #define OMAP_EMIFS_CONFIG_BM (1 << 1) | |
366 | #define OMAP_EMIFS_CONFIG_WP (1 << 0) | |
367 | ||
368 | /* | |
369 | * Memory chunk set aside for the Framebuffer in SRAM | |
370 | */ | |
371 | #define SRAM_FRAMEBUFFER_MEMORY OMAP1510_SRAM_BASE | |
372 | ||
373 | ||
374 | /* | |
375 | * DMA | |
376 | */ | |
377 | ||
378 | #define OMAP1510_DMA_BASE 0xFFFED800 | |
379 | #define OMAP_DMA_BASE OMAP1510_DMA_BASE | |
380 | ||
381 | /* Global Register selection */ | |
382 | #define NO_GLOBAL_DMA_ACCESS 0 | |
383 | ||
384 | /* Channel select field | |
385 | * NOTE: all other channels are linear, chan0 is 0, chan1 is 1, etc... | |
386 | */ | |
387 | #define LCD_CHANNEL 0xc | |
388 | ||
389 | /* Register Select Field (LCD) */ | |
390 | #define DMA_LCD_CTRL 0 | |
391 | #define DMA_LCD_TOP_F1_L 1 | |
392 | #define DMA_LCD_TOP_F1_U 2 | |
393 | #define DMA_LCD_BOT_F1_L 3 | |
394 | #define DMA_LCD_BOT_F1_U 4 | |
395 | ||
396 | #define LCD_FRAME_MODE (1<<0) | |
397 | #define LCD_FRAME_IT_IE (1<<1) | |
398 | #define LCD_BUS_ERROR_IT_IE (1<<2) | |
399 | #define LCD_FRAME_1_IT_COND (1<<3) | |
400 | #define LCD_FRAME_2_IT_COND (1<<4) | |
401 | #define LCD_BUS_ERROR_IT_COND (1<<5) | |
402 | #define LCD_SOURCE_IMIF (1<<6) | |
403 | ||
404 | /* | |
405 | * Real-Time Clock | |
406 | */ | |
407 | ||
408 | #define RTC_SECONDS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x00) | |
409 | #define RTC_MINUTES (volatile __u8 *)(OMAP1510_RTC_BASE + 0x04) | |
410 | #define RTC_HOURS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x08) | |
411 | #define RTC_DAYS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x0C) | |
412 | #define RTC_MONTHS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x10) | |
413 | #define RTC_YEARS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x14) | |
414 | #define RTC_CTRL (volatile __u8 *)(OMAP1510_RTC_BASE + 0x40) | |
415 | ||
416 | ||
417 | /* --------------------------------------------------------------------------- | |
418 | * OMAP1510 Interrupt Handlers | |
419 | * --------------------------------------------------------------------------- | |
420 | * | |
421 | */ | |
422 | #define OMAP_IH1_BASE 0xfffecb00 | |
423 | #define OMAP_IH2_BASE 0xfffe0000 | |
424 | #define OMAP1510_ITR 0x0 | |
425 | #define OMAP1510_MASK 0x4 | |
426 | ||
427 | #define INTERRUPT_HANDLER_BASE OMAP_IH1_BASE | |
428 | #define INTERRUPT_INPUT_REGISTER OMAP1510_ITR | |
429 | #define INTERRUPT_MASK_REGISTER OMAP1510_MASK | |
430 | ||
431 | ||
432 | /* --------------------------------------------------------------------------- | |
433 | * OMAP1510 TIMERS | |
434 | * --------------------------------------------------------------------------- | |
435 | * | |
436 | */ | |
437 | ||
438 | #define OMAP1510_32kHz_TIMER_BASE 0xfffb9000 | |
439 | ||
440 | /* 32k Timer Registers */ | |
441 | #define TIMER32k_CR 0x08 | |
442 | #define TIMER32k_TVR 0x00 | |
443 | #define TIMER32k_TCR 0x04 | |
444 | ||
445 | /* 32k Timer Control Register definition */ | |
446 | #define TIMER32k_TSS (1<<0) | |
447 | #define TIMER32k_TRB (1<<1) | |
448 | #define TIMER32k_INT (1<<2) | |
449 | #define TIMER32k_ARL (1<<3) | |
450 | ||
451 | /* MPU Timer base addresses */ | |
452 | #define OMAP1510_MPUTIMER_BASE 0xfffec500 | |
453 | #define OMAP1510_MPUTIMER_OFF 0x00000100 | |
454 | ||
455 | #define OMAP1510_TIMER1_BASE 0xfffec500 | |
456 | #define OMAP1510_TIMER2_BASE 0xfffec600 | |
457 | #define OMAP1510_TIMER3_BASE 0xfffec700 | |
458 | ||
459 | /* MPU Timer Registers */ | |
460 | #define CNTL_TIMER 0 | |
461 | #define LOAD_TIM 4 | |
462 | #define READ_TIM 8 | |
463 | ||
464 | /* CNTL_TIMER register bits */ | |
465 | #define MPUTIM_FREE (1<<6) | |
466 | #define MPUTIM_CLOCK_ENABLE (1<<5) | |
b2325383 | 467 | #define MPUTIM_PTV_MASK (0x7<<MPUTIM_PTV_BIT) |
2e5983d2 WD |
468 | #define MPUTIM_PTV_BIT 2 |
469 | #define MPUTIM_AR (1<<1) | |
470 | #define MPUTIM_ST (1<<0) | |
471 | ||
472 | /* --------------------------------------------------------------------------- | |
473 | * OMAP1510 GPIO (SHARED) | |
474 | * --------------------------------------------------------------------------- | |
475 | * | |
476 | */ | |
477 | #define GPIO_DATA_INPUT_REG (OMAP1510_GPIO_BASE + 0x0) | |
478 | #define GPIO_DATA_OUTPUT_REG (OMAP1510_GPIO_BASE + 0x4) | |
479 | #define GPIO_DIR_CONTROL_REG (OMAP1510_GPIO_BASE + 0x8) | |
480 | #define GPIO_INT_CONTROL_REG (OMAP1510_GPIO_BASE + 0xc) | |
481 | #define GPIO_INT_MASK_REG (OMAP1510_GPIO_BASE + 0x10) | |
482 | #define GPIO_INT_STATUS_REG (OMAP1510_GPIO_BASE + 0x14) | |
483 | #define GPIO_PIN_CONTROL_REG (OMAP1510_GPIO_BASE + 0x18) | |
484 | ||
485 | ||
486 | /* --------------------------- | |
487 | * OMAP1510 MPUIO (ARM only) | |
488 | *---------------------------- | |
489 | */ | |
490 | #define OMAP1510_MPUIO_BASE 0xFFFB5000 | |
491 | #define MPUIO_DATA_INPUT_REG (OMAP1510_MPUIO_BASE + 0x0) | |
492 | #define MPUIO_DATA_OUTPUT_REG (OMAP1510_MPUIO_BASE + 0x4) | |
493 | #define MPUIO_DIR_CONTROL_REG (OMAP1510_MPUIO_BASE + 0x8) | |
494 | ||
495 | /* --------------------------------------------------------------------------- | |
496 | * OMAP1510 TIPB (only) | |
497 | * --------------------------------------------------------------------------- | |
498 | * | |
499 | */ | |
500 | #define TIPB_PUBLIC_CNTL_BASE 0xfffed300 | |
501 | #define MPU_PUBLIC_TIPB_CNTL_REG (TIPB_PUBLIC_CNTL_BASE + 0x8) | |
502 | #define TIPB_PRIVATE_CNTL_BASE 0xfffeca00 | |
503 | #define MPU_PRIVATE_TIPB_CNTL_REG (TIPB_PRIVATE_CNTL_BASE + 0x8) | |
504 | ||
505 | /* | |
506 | * --------------------------------------------------------------------------- | |
507 | * OMAP1510 Camera Interface | |
508 | * --------------------------------------------------------------------------- | |
509 | */ | |
510 | #define CAMERA_BASE (IO_BASE + 0x6800) | |
511 | #define CAM_CTRLCLOCK_REG (CAMERA_BASE + 0x00) | |
512 | #define CAM_IT_STATUS_REG (CAMERA_BASE + 0x04) | |
513 | #define CAM_MODE_REG (CAMERA_BASE + 0x08) | |
514 | #define CAM_STATUS_REG (CAMERA_BASE + 0x0C) | |
515 | #define CAM_CAMDATA_REG (CAMERA_BASE + 0x10) | |
516 | #define CAM_GPIO_REG (CAMERA_BASE + 0x14) | |
517 | #define CAM_PEAK_CTR_REG (CAMERA_BASE + 0x18) | |
518 | ||
519 | #if 0 | |
520 | #ifndef __ASSEMBLY__ | |
521 | typedef struct { | |
522 | __u32 ctrlclock; | |
523 | __u32 it_status; | |
524 | __u32 mode; | |
525 | __u32 status; | |
526 | __u32 camdata; | |
527 | __u32 gpio; | |
528 | __u32 peak_counter; | |
529 | } camera_regs_t; | |
530 | #endif | |
531 | #endif | |
532 | ||
533 | /* CTRLCLOCK bit shifts */ | |
534 | #define FOSCMOD_BIT 0 | |
535 | #define FOSCMOD_MASK (0x7 << FOSCMOD_BIT) | |
536 | #define FOSCMOD_12MHz 0x0 | |
537 | #define FOSCMOD_6MHz 0x2 | |
538 | #define FOSCMOD_9_6MHz 0x4 | |
539 | #define FOSCMOD_24MHz 0x5 | |
540 | #define FOSCMOD_8MHz 0x6 | |
541 | #define POLCLK (1<<3) | |
542 | #define CAMEXCLK_EN (1<<4) | |
543 | #define MCLK_EN (1<<5) | |
544 | #define DPLL_EN (1<<6) | |
545 | #define LCLK_EN (1<<7) | |
546 | ||
547 | /* IT_STATUS bit shifts */ | |
548 | #define V_UP (1<<0) | |
549 | #define V_DOWN (1<<1) | |
550 | #define H_UP (1<<2) | |
551 | #define H_DOWN (1<<3) | |
552 | #define FIFO_FULL (1<<4) | |
553 | #define DATA_XFER (1<<5) | |
554 | ||
555 | /* MODE bit shifts */ | |
556 | #define CAMOSC (1<<0) | |
557 | #define IMGSIZE_BIT 1 | |
558 | #define IMGSIZE_MASK (0x3 << IMGSIZE_BIT) | |
559 | #define IMGSIZE_CIF (0x0 << IMGSIZE_BIT) /* 352x288 */ | |
560 | #define IMGSIZE_QCIF (0x1 << IMGSIZE_BIT) /* 176x144 */ | |
561 | #define IMGSIZE_VGA (0x2 << IMGSIZE_BIT) /* 640x480 */ | |
562 | #define IMGSIZE_QVGA (0x3 << IMGSIZE_BIT) /* 320x240 */ | |
563 | #define ORDERCAMD (1<<3) | |
564 | #define EN_V_UP (1<<4) | |
565 | #define EN_V_DOWN (1<<5) | |
566 | #define EN_H_UP (1<<6) | |
567 | #define EN_H_DOWN (1<<7) | |
568 | #define EN_DMA (1<<8) | |
569 | #define THRESHOLD (1<<9) | |
570 | #define THRESHOLD_BIT 9 | |
571 | #define THRESHOLD_MASK (0x7f<<9) | |
572 | #define EN_NIRQ (1<<16) | |
573 | #define EN_FIFO_FULL (1<<17) | |
574 | #define RAZ_FIFO (1<<18) | |
575 | ||
576 | /* STATUS bit shifts */ | |
577 | #define VSTATUS (1<<0) | |
578 | #define HSTATUS (1<<1) | |
579 | ||
580 | /* GPIO bit shifts */ | |
581 | #define CAM_RST (1<<0) | |
582 | ||
583 | ||
584 | /********************* | |
585 | * Watchdog timer. | |
586 | *********************/ | |
587 | #define WDTIM_BASE 0xfffec800 | |
588 | #define WDTIM_CONTROL (WDTIM_BASE+0x00) | |
589 | #define WDTIM_LOAD (WDTIM_BASE+0x04) | |
590 | #define WDTIM_READ (WDTIM_BASE+0x04) | |
591 | #define WDTIM_MODE (WDTIM_BASE+0x08) | |
592 | ||
593 | /* Values to write to mode register to disable the watchdog function. */ | |
594 | #define DISABLE_SEQ1 0xF5 | |
595 | #define DISABLE_SEQ2 0xA0 | |
596 | ||
597 | /* WDTIM_CONTROL bit definitions. */ | |
598 | #define WDTIM_CONTROL_ST BIT7 | |
599 | ||
600 | ||
2e5983d2 WD |
601 | /* --------------------------------------------------------------------------- |
602 | * Differentiating processor versions for those who care. | |
603 | * --------------------------------------------------------------------------- | |
604 | * | |
605 | */ | |
606 | #define OMAP1509 0 | |
607 | #define OMAP1510 1 | |
608 | ||
609 | #define OMAP1510_ID_CODE_REG 0xfffed404 | |
610 | ||
611 | #ifndef __ASSEMBLY__ | |
612 | int cpu_type(void); | |
613 | #endif | |
614 | ||
615 | /* | |
616 | * EVM Implementation Specifics. | |
617 | * | |
618 | * *** NOTE *** | |
619 | * Any definitions in these files should be prefixed by an identifier - | |
620 | * eg. OMAP1510P1_FLASH0_BASE . | |
621 | * | |
622 | */ | |
623 | #ifdef CONFIG_OMAP_INNOVATOR | |
624 | #include "innovator.h" | |
625 | #endif | |
626 | ||
627 | #ifdef CONFIG_OMAP_1510P1 | |
628 | #include "omap1510p1.h" | |
629 | #endif | |
630 | ||
631 | /*****************************************************************************/ | |
632 | ||
633 | #define CLKGEN_RESET_BASE (0xfffece00) | |
634 | #define ARM_CKCTL (volatile __u16 *)(CLKGEN_RESET_BASE + 0x0) | |
635 | #define ARM_IDLECT1 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x4) | |
636 | #define ARM_IDLECT2 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x8) | |
637 | #define ARM_EWUPCT (volatile __u16 *)(CLKGEN_RESET_BASE + 0xC) | |
638 | #define ARM_RSTCT1 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x10) | |
639 | #define ARM_RSTCT2 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x14) | |
640 | #define ARM_SYSST (volatile __u16 *)(CLKGEN_RESET_BASE + 0x18) | |
641 | ||
642 | ||
643 | #define CK_CLKIN 12 /* MHz */ | |
644 | #define CK_RATEF 1 | |
645 | #define CK_IDLEF 2 | |
646 | #define CK_ENABLEF 4 | |
647 | #define CK_SELECTF 8 | |
648 | #ifndef __ASSEMBLER__ | |
649 | #define CK_DPLL1 ((volatile __u16 *)0xfffecf00) | |
650 | #else | |
651 | #define CK_DPLL1 (0xfffecf00) | |
652 | #endif | |
653 | #define SETARM_IDLE_SHIFT | |
654 | ||
655 | /* ARM_CKCTL bit shifts */ | |
656 | #define PERDIV 0 | |
657 | #define LCDDIV 2 | |
658 | #define ARMDIV 4 | |
659 | #define DSPDIV 6 | |
660 | #define TCDIV 8 | |
661 | #define DSPMMUDIV 10 | |
662 | #define ARM_TIMXO 12 | |
663 | #define EN_DSPCK 13 | |
664 | #define ARM_INTHCK_SEL 14 /* REVISIT -- where is this used? */ | |
665 | ||
666 | #define ARM_CKCTL_RSRVD_BIT15 (1 << 15) | |
667 | #define ARM_CKCTL_ARM_INTHCK_SEL (1 << 14) | |
668 | #define ARM_CKCTL_EN_DSPCK (1 << 13) | |
669 | #define ARM_CKCTL_ARM_TIMXO (1 << 12) | |
670 | #define ARM_CKCTL_DSPMMU_DIV1 (1 << 11) | |
671 | #define ARM_CKCTL_DSPMMU_DIV2 (1 << 10) | |
672 | #define ARM_CKCTL_TCDIV1 (1 << 9) | |
673 | #define ARM_CKCTL_TCDIV2 (1 << 8) | |
674 | #define ARM_CKCTL_DSPDIV1 (1 << 7) | |
675 | #define ARM_CKCTL_DSPDIV0 (1 << 6) | |
676 | #define ARM_CKCTL_ARMDIV1 (1 << 5) | |
677 | #define ARM_CKCTL_ARMDIV0 (1 << 4) | |
678 | #define ARM_CKCTL_LCDDIV1 (1 << 3) | |
679 | #define ARM_CKCTL_LCDDIV0 (1 << 2) | |
680 | #define ARM_CKCTL_PERDIV1 (1 << 1) | |
681 | #define ARM_CKCTL_PERDIV0 (1 << 0) | |
682 | ||
683 | /* ARM_IDLECT1 bit shifts */ | |
684 | #define IDLWDT_ARM 0 | |
685 | #define IDLXORP_ARM 1 | |
686 | #define IDLPER_ARM 2 | |
687 | #define IDLLCD_ARM 3 | |
688 | #define IDLLB_ARM 4 | |
689 | #define IDLHSAB_ARM 5 | |
690 | #define IDLIF_ARM 6 | |
691 | #define IDLDPLL_ARM 7 | |
692 | #define IDLAPI_ARM 8 | |
693 | #define IDLTIM_ARM 9 | |
694 | #define SETARM_IDLE 11 | |
695 | ||
696 | /* ARM_IDLECT2 bit shifts */ | |
697 | #define EN_WDTCK 0 | |
698 | #define EN_XORPCK 1 | |
699 | #define EN_PERCK 2 | |
700 | #define EN_LCDCK 3 | |
701 | #define EN_LBCK 4 | |
702 | #define EN_HSABCK 5 | |
703 | #define EN_APICK 6 | |
704 | #define EN_TIMCK 7 | |
705 | #define DMACK_REQ 8 | |
706 | #define EN_GPIOCK 9 | |
707 | #define EN_LBFREECK 10 | |
708 | ||
709 | #define ARM_RSTCT1_SW_RST (1 << 3) | |
710 | #define ARM_RSTCT1_DSP_RST (1 << 2) | |
711 | #define ARM_RSTCT1_DSP_EN (1 << 1) | |
712 | #define ARM_RSTCT1_ARM_RST (1 << 0) | |
713 | ||
714 | /* ARM_RSTCT2 bit shifts */ | |
715 | #define EN_PER 0 | |
716 | ||
717 | #define ARM_SYSST_RSRVD_BIT15 (1 << 15) | |
718 | #define ARM_SYSST_RSRVD_BIT14 (1 << 14) | |
719 | #define ARM_SYSST_CLOCK_SELECT2 (1 << 13) | |
720 | #define ARM_SYSST_CLOCK_SELECT1 (1 << 12) | |
721 | #define ARM_SYSST_CLOCK_SELECT0 (1 << 11) | |
722 | #define ARM_SYSST_RSRVD_BIT10 (1 << 10) | |
723 | #define ARM_SYSST_RSRVD_BIT9 (1 << 9) | |
724 | #define ARM_SYSST_RSRVD_BIT8 (1 << 8) | |
725 | #define ARM_SYSST_RSRVD_BIT7 (1 << 7) | |
726 | #define ARM_SYSST_IDLE_DSP (1 << 6) | |
727 | #define ARM_SYSST_POR (1 << 5) | |
728 | #define ARM_SYSST_EXT_RST (1 << 4) | |
729 | #define ARM_SYSST_ARM_MCRST (1 << 3) | |
730 | #define ARM_SYSST_ARM_WDRST (1 << 2) | |
731 | #define ARM_SYSST_GLOB_SWRST (1 << 1) | |
732 | #define ARM_SYSST_DSP_WDRST (1 << 0) | |
733 | ||
734 | /* Table 15-23. DPLL Control Registers: */ | |
735 | #define DPLL_CTL_REG (volatile __u16 *)(0xfffecf00) | |
736 | ||
737 | /* Table 15-24. Control Register (CTL_REG): */ | |
738 | ||
739 | #define DPLL_CTL_REG_IOB (1 << 13) | |
740 | #define DPLL_CTL_REG_PLL_MULT Fld(5,0) | |
741 | ||
742 | /*****************************************************************************/ | |
743 | ||
744 | /* OMAP INTERRUPT REGISTERS */ | |
745 | #define IRQ_ITR 0x00 | |
746 | #define IRQ_MIR 0x04 | |
747 | #define IRQ_SIR_IRQ 0x10 | |
748 | #define IRQ_SIR_FIQ 0x14 | |
749 | #define IRQ_CONTROL_REG 0x18 | |
750 | #define IRQ_ISR 0x9c | |
751 | #define IRQ_ILR0 0x1c | |
752 | ||
753 | #define REG_IHL1_MIR (OMAP_IH1_BASE+IRQ_MIR) | |
754 | #define REG_IHL2_MIR (OMAP_IH2_BASE+IRQ_MIR) | |
755 | ||
756 | /* INTERRUPT LEVEL REGISTER BITS */ | |
757 | #define ILR_PRIORITY_MASK (0x3c) | |
758 | #define ILR_PRIORITY_SHIFT (2) | |
759 | #define ILR_LEVEL_TRIGGER (1<<1) | |
760 | #define ILR_FIQ (1<<0) | |
761 | ||
762 | #define IRQ_LEVEL_INT 1 | |
763 | #define IRQ_EDGE_INT 0 | |
232c150a WD |
764 | |
765 | /* Macros to access registers */ | |
766 | #define outb(v,p) *(volatile u8 *) (p) = v | |
767 | #define outw(v,p) *(volatile u16 *) (p) = v | |
768 | #define outl(v,p) *(volatile u32 *) (p) = v | |
769 | ||
770 | #define inb(p) *(volatile u8 *) (p) | |
771 | #define inw(p) *(volatile u16 *) (p) | |
772 | #define inl(p) *(volatile u32 *) (p) |