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2e5983d2 WD |
1 | /* |
2 | * (C) Copyright 2003 | |
3 | * Texas Instruments. | |
4 | * Kshitij Gupta <kshitij@ti.com> | |
5 | * Configuation settings for the TI OMAP Innovator board. | |
6 | * | |
7 | * See file CREDITS for list of people who contributed to this | |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
25 | ||
26 | #ifndef __CONFIG_H | |
27 | #define __CONFIG_H | |
28 | ||
29 | /* | |
30 | * High Level Configuration Options | |
31 | * (easy to change) | |
32 | */ | |
33 | #define CONFIG_ARM925T 1 /* This is an arm925t CPU */ | |
34 | #define CONFIG_OMAP 1 /* in a TI OMAP core */ | |
35 | #define CONFIG_OMAP1510 1 /* which is in a 1510 (helen) */ | |
36 | #define CONFIG_INNOVATOROMAP1510 1 /* a Innovator Board */ | |
37 | ||
38 | /* input clock of PLL */ | |
39 | #define CONFIG_SYS_CLK_FREQ 12000000 /* the OMAP1510 Innovator has 12MHz input clock */ | |
40 | ||
41 | #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ | |
42 | ||
43 | #define CONFIG_MISC_INIT_R | |
44 | ||
45 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ | |
46 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
5779d8d9 | 47 | #define CONFIG_INITRD_TAG 1 |
2e5983d2 WD |
48 | |
49 | /* | |
50 | * Size of malloc() pool | |
51 | */ | |
6d0f6bcf JCPV |
52 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) |
53 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ | |
2e5983d2 WD |
54 | |
55 | /* | |
56 | * Hardware drivers | |
57 | */ | |
58 | /* | |
59 | #define CONFIG_DRIVER_SMC9196 | |
60 | #define CONFIG_SMC9196_BASE 0x08000300 | |
61 | #define CONFIG_SMC9196_EXT_PHY | |
62 | */ | |
63 | #define CONFIG_DRIVER_LAN91C96 | |
64 | #define CONFIG_LAN91C96_BASE 0x08000300 | |
65 | #define CONFIG_LAN91C96_EXT_PHY | |
66 | ||
67 | /* | |
68 | * NS16550 Configuration | |
69 | */ | |
6d0f6bcf JCPV |
70 | #define CONFIG_SYS_NS16550 |
71 | #define CONFIG_SYS_NS16550_SERIAL | |
72 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) | |
73 | #define CONFIG_SYS_NS16550_CLK (CONFIG_SYS_CLK_FREQ) /* can be 12M/32Khz or 48Mhz */ | |
74 | #define CONFIG_SYS_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart on helen */ | |
2e5983d2 WD |
75 | |
76 | /* | |
77 | * select serial console configuration | |
78 | */ | |
79 | #define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP1510 Innovator */ | |
80 | ||
81 | /* allow to overwrite serial and ethaddr */ | |
82 | #define CONFIG_ENV_OVERWRITE | |
83 | ||
84 | #define CONFIG_ENV_OVERWRITE | |
85 | #define CONFIG_CONS_INDEX 1 | |
86 | #define CONFIG_BAUDRATE 115200 | |
6d0f6bcf | 87 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
2e5983d2 | 88 | |
a5cb2309 JL |
89 | |
90 | /* | |
91 | * Command line configuration. | |
92 | */ | |
93 | #include <config_cmd_default.h> | |
94 | ||
95 | #define CONFIG_CMD_DHCP | |
96 | ||
97 | ||
d3b8c1a7 JL |
98 | /* |
99 | * BOOTP options | |
100 | */ | |
101 | #define CONFIG_BOOTP_SUBNETMASK | |
102 | #define CONFIG_BOOTP_GATEWAY | |
103 | #define CONFIG_BOOTP_HOSTNAME | |
104 | #define CONFIG_BOOTP_BOOTPATH | |
105 | ||
2e5983d2 | 106 | |
2e5983d2 WD |
107 | #include <configs/omap1510.h> |
108 | ||
109 | #define CONFIG_BOOTDELAY 3 | |
5779d8d9 WD |
110 | #define CONFIG_BOOTARGS "console=ttyS0,115200n8 noinitrd root=/dev/nfs ip=bootp" |
111 | #define CONFIG_BOOTCOMMAND "bootp;tftp;bootm" | |
6d0f6bcf | 112 | #define CONFIG_SYS_AUTOLOAD "n" /* No autoload */ |
2e5983d2 | 113 | |
a5cb2309 | 114 | #if defined(CONFIG_CMD_KGDB) |
2e5983d2 WD |
115 | #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ |
116 | /* what's this ? it's not used anywhere */ | |
117 | #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ | |
118 | #endif | |
119 | ||
120 | /* | |
121 | * Miscellaneous configurable options | |
122 | */ | |
6d0f6bcf JCPV |
123 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
124 | #define CONFIG_SYS_PROMPT "OMAP1510 Innovator # " /* Monitor Command Prompt */ | |
125 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
126 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
127 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
128 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
2e5983d2 | 129 | |
6d0f6bcf JCPV |
130 | #define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */ |
131 | #define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ | |
2e5983d2 | 132 | |
6d0f6bcf | 133 | #undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ |
2e5983d2 | 134 | |
6d0f6bcf | 135 | #define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */ |
2e5983d2 WD |
136 | |
137 | /* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1. | |
138 | * This time is further subdivided by a local divisor. | |
139 | */ | |
6d0f6bcf JCPV |
140 | #define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */ |
141 | #define CONFIG_SYS_PVT 7 /* 2^(pvt+1), divide by 256 */ | |
142 | #define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT)) | |
2e5983d2 WD |
143 | |
144 | /*----------------------------------------------------------------------- | |
145 | * Stack sizes | |
146 | * | |
147 | * The stack sizes are set up in start.S using the settings below | |
148 | */ | |
149 | #define CONFIG_STACKSIZE (128*1024) /* regular stack */ | |
150 | #ifdef CONFIG_USE_IRQ | |
151 | #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ | |
152 | #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ | |
153 | #endif | |
154 | ||
155 | /*----------------------------------------------------------------------- | |
156 | * Physical Memory Map | |
157 | */ | |
158 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ | |
159 | #define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ | |
160 | #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ | |
161 | ||
162 | #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ | |
163 | ||
6d0f6bcf | 164 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
2e5983d2 WD |
165 | |
166 | /*----------------------------------------------------------------------- | |
167 | * FLASH and environment organization | |
168 | */ | |
6d0f6bcf | 169 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
2e5983d2 | 170 | #define PHYS_FLASH_SIZE 0x01000000 /* 16MB */ |
656658dd | 171 | #define PHYS_FLASH_SECT_SIZE (128*1024) /* Size of a sector (128kB) */ |
6d0f6bcf JCPV |
172 | #define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ |
173 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SECT_SIZE) | |
174 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */ | |
175 | #define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE /* Reserve 1 sector */ | |
176 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE } | |
656658dd WD |
177 | |
178 | /*----------------------------------------------------------------------- | |
179 | * FLASH driver setup | |
180 | */ | |
6d0f6bcf | 181 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */ |
00b1883a | 182 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */ |
6d0f6bcf JCPV |
183 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ |
184 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */ | |
2e5983d2 WD |
185 | |
186 | /* timeout values are in ticks */ | |
6d0f6bcf JCPV |
187 | #define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ |
188 | #define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */ | |
2e5983d2 | 189 | |
5a1aceb0 | 190 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
191 | #define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE /* Total Size of Environment Sector */ |
192 | #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE | |
6d0f6bcf | 193 | #define CONFIG_ENV_OFFSET ( CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN ) /* Environment after Monitor */ |
2e5983d2 WD |
194 | |
195 | #endif /* __CONFIG_H */ |