[people/ms/u-boot.git] / include / configs / omap2420h4.h

/*
 * (C) Copyright 2004
 * Texas Instruments.
 * Richard Woodruff <r-woodruff2@ti.com>
 * Kshitij Gupta <kshitij@ti.com>
 *
 * Configuration settings for the 242x TI H4 board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_ARM1136           1    /* This is an arm1136 CPU core */
#define CONFIG_OMAP              1    /* in a TI OMAP core */
#define CONFIG_OMAP2420	         1    /* which is in a 2420 */
#define CONFIG_OMAP2420H4        1    /* and on a H4 board */
/*#define CONFIG_APTIX           1    #* define if on APTIX test chip */
/*#define CONFIG_VIRTIO          1    #* Using Virtio simulator */

/* Clock config to target*/
#define PRCM_CONFIG_II	1
/* #define PRCM_CONFIG_III		1 */

#include <asm/arch/omap2420.h>        /* get chip and board defs */

/* On H4, NOR and NAND flash are mutual exclusive.
   Define this if you want to use NAND
 */
/*#define CONFIG_SYS_NAND_BOOT */

#ifdef CONFIG_APTIX
#define V_SCLK                   1500000
#else
#define V_SCLK                   12000000
#endif

/* input clock of PLL */
/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */
#define CONFIG_SYS_CLK_FREQ      V_SCLK

#undef CONFIG_USE_IRQ                 /* no support for IRQs */
#define CONFIG_MISC_INIT_R

#define CONFIG_CMDLINE_TAG       1    /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG        1
#define CONFIG_REVISION_TAG      1

/*
 * Size of malloc() pool
 */
#define CONFIG_ENV_SIZE             SZ_128K     /* Total Size of Environment Sector */
#define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + SZ_128K)
#define CONFIG_SYS_GBL_DATA_SIZE        128  /* size in bytes reserved for initial data */

/*
 * Hardware drivers
 */

/*
 * SMC91c96 Etherent
 */
#define CONFIG_NET_MULTI
#define CONFIG_LAN91C96
#define CONFIG_LAN91C96_BASE     (H4_CS1_BASE+0x300)
#define CONFIG_LAN91C96_EXT_PHY

/*
 * NS16550 Configuration
 */
#ifdef CONFIG_APTIX
#define V_NS16550_CLK            (6000000)   /* 6MHz in current MaxSet */
#else
#define V_NS16550_CLK            (48000000)  /* 48MHz (APLL96/2) */
#endif

#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE     (-4)
#define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK   /* 3MHz (1.5MHz*2) */
#define CONFIG_SYS_NS16550_COM1         OMAP2420_UART1

/*
 * select serial console configuration
 */
#define CONFIG_SERIAL1           1    /* UART1 on H4 */

  /*
   * I2C configuration
   */
#define CONFIG_HARD_I2C
#define CONFIG_SYS_I2C_SPEED          100000
#define CONFIG_SYS_I2C_SLAVE          1
#define CONFIG_DRIVER_OMAP24XX_I2C

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX        1
#define CONFIG_BAUDRATE          115200
#define CONFIG_SYS_BAUDRATE_TABLE       {9600, 19200, 38400, 57600, 115200}


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#ifdef CONFIG_SYS_NAND_BOOT
    #define CONFIG_CMD_DHCP
    #define CONFIG_CMD_I2C
    #define CONFIG_CMD_NAND
    #define CONFIG_CMD_JFFS2
#else
    #define CONFIG_CMD_DHCP
    #define CONFIG_CMD_I2C
    #define CONFIG_CMD_JFFS2

    #undef CONFIG_CMD_SOURCE
#endif


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH

#define CONFIG_BOOTDELAY         3

#ifdef NFS_BOOT_DEFAULTS
#define CONFIG_BOOTARGS	         "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw nfsroot=128.247.77.158:/home/a0384864/wtbu/rootfs ip=dhcp"
#else
#define CONFIG_BOOTARGS          "root=/dev/ram0 rw mem=32M console=ttyS0,115200n8 initrd=0x80600000,8M ramdisk_size=8192"
#endif

#define CONFIG_NETMASK           255.255.254.0
#define CONFIG_IPADDR            128.247.77.90
#define CONFIG_SERVERIP          128.247.77.158
#define CONFIG_BOOTFILE          "uImage"

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP             /* undef to save memory */
#ifdef CONFIG_APTIX
# define CONFIG_SYS_PROMPT		"OMAP2420 Aptix # "
#else
# define CONFIG_SYS_PROMPT		"OMAP242x H4 # "
#endif
#define CONFIG_SYS_CBSIZE               256  /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS              16          /* max number of command args */
#define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size */

#define CONFIG_SYS_MEMTEST_START        (OMAP2420_SDRC_CS0)  /* memtest works on */
#define CONFIG_SYS_MEMTEST_END          (OMAP2420_SDRC_CS0+SZ_31M)

#define CONFIG_SYS_LOAD_ADDR            (OMAP2420_SDRC_CS0) /* default load address */

/* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
 * 32KHz clk, or from external sig. This rate is divided by a local divisor.
 */
#ifdef CONFIG_APTIX
#define V_PTV			3
#else
#define V_PTV			7	/* use with 12MHz/128 */
#endif

#define CONFIG_SYS_TIMERBASE		OMAP2420_GPT2
#define CONFIG_SYS_PTV			V_PTV	/* 2^(PTV+1) */
#define CONFIG_SYS_HZ			((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))

/*-----------------------------------------------------------------------
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE         SZ_128K /* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ     SZ_4K   /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ     SZ_4K   /* FIQ stack */
#endif

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS     2                 /* CS1 may or may not be populated */
#define PHYS_SDRAM_1             OMAP2420_SDRC_CS0
#define PHYS_SDRAM_1_SIZE        SZ_32M            /* at least 32 meg */
#define PHYS_SDRAM_2             OMAP2420_SDRC_CS1

#define PHYS_FLASH_SECT_SIZE     SZ_128K
#define PHYS_FLASH_1             H4_CS0_BASE	   /* Flash Bank #1 */
#define PHYS_FLASH_SIZE_1        SZ_32M
#define PHYS_FLASH_2             (H4_CS0_BASE+SZ_32M) /* same cs, 2 chips in series */
#define PHYS_FLASH_SIZE_2        SZ_32M

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */
#define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
#define CONFIG_SYS_MAX_FLASH_BANKS      2           /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT       (259)	     /* max number of sectors on one chip */
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
#define CONFIG_SYS_MONITOR_LEN		SZ_128K      /* Reserve 1 sector */
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE_1 }

#ifdef CONFIG_SYS_NAND_BOOT
#define CONFIG_ENV_IS_IN_NAND	1
#define CONFIG_ENV_OFFSET	0x80000	/* environment starts here  */
#else
#define CONFIG_ENV_ADDR             (CONFIG_SYS_FLASH_BASE + SZ_128K)
#define	CONFIG_ENV_IS_IN_FLASH      1
#define CONFIG_ENV_SECT_SIZE	PHYS_FLASH_SECT_SIZE
#define CONFIG_ENV_OFFSET	( CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN ) /* Environment after Monitor */
#endif

/*-----------------------------------------------------------------------
 * CFI FLASH driver setup
 */
#define CONFIG_SYS_FLASH_CFI		1	/* Flash memory is CFI compliant */
#define CONFIG_FLASH_CFI_DRIVER	1	/* Use drivers/mtd/cfi_flash.c */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* Use buffered writes (~10x faster) */
#define CONFIG_SYS_FLASH_PROTECTION	1	/* Use hardware sector protection */

/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT     (100*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
#define CONFIG_SYS_FLASH_WRITE_TOUT     (100*CONFIG_SYS_HZ) /* Timeout for Flash Write */

#define CONFIG_SYS_JFFS2_MEM_NAND

/*
 * JFFS2 partitions
 */
/* No command line, one static partition, whole device */
#undef CONFIG_CMD_MTDPARTS
#define CONFIG_JFFS2_DEV		"nor1"
#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
#define CONFIG_JFFS2_PART_OFFSET	0x00000000

/* mtdparts command line support */
/* Note: fake mtd_id used, no linux mtd map file */
/*
#define CONFIG_CMD_MTDPARTS
#define MTDIDS_DEFAULT		"nor1=omap2420-1"
#define MTDPARTS_DEFAULT	"mtdparts=omap2420-1:-(jffs2)"
*/

#endif							/* __CONFIG_H */
Commit	Line	Data
8ed96046 WD	1	/*
	2	* (C) Copyright 2004
	3	* Texas Instruments.
	4	* Richard Woodruff <r-woodruff2@ti.com>
	5	* Kshitij Gupta <kshitij@ti.com>
	6	*
	7	* Configuration settings for the 242x TI H4 board.
	8	*
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	*/
	34	#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
	35	#define CONFIG_OMAP 1 /* in a TI OMAP core */
	36	#define CONFIG_OMAP2420 1 /* which is in a 2420 */
	37	#define CONFIG_OMAP2420H4 1 /* and on a H4 board */
082acfd4 WD	38	/#define CONFIG_APTIX 1 # define if on APTIX test chip */
082acfd4 WD	39	/#define CONFIG_VIRTIO 1 # Using Virtio simulator */
8ed96046	40
289f932c	41	/* Clock config to target*/
49a7581c	42	#define PRCM_CONFIG_II 1
716c1dcb	43	/* #define PRCM_CONFIG_III 1 */
8ed96046 WD	44
	45	#include <asm/arch/omap2420.h> /* get chip and board defs */
	46
289f932c WD	47	/* On H4, NOR and NAND flash are mutual exclusive.
	48	Define this if you want to use NAND
	49	*/
6d0f6bcf	50	/#define CONFIG_SYS_NAND_BOOT /
289f932c	51
8ed96046 WD	52	#ifdef CONFIG_APTIX
	53	#define V_SCLK 1500000
	54	#else
	55	#define V_SCLK 12000000
	56	#endif
	57
	58	/* input clock of PLL */
	59	/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */
	60	#define CONFIG_SYS_CLK_FREQ V_SCLK
	61
	62	#undef CONFIG_USE_IRQ /* no support for IRQs */
	63	#define CONFIG_MISC_INIT_R
	64
	65	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	66	#define CONFIG_SETUP_MEMORY_TAGS 1
	67	#define CONFIG_INITRD_TAG 1
289f932c	68	#define CONFIG_REVISION_TAG 1
8ed96046 WD	69
	70	/*
	71	* Size of malloc() pool
	72	*/
0e8d1586	73	#define CONFIG_ENV_SIZE SZ_128K /* Total Size of Environment Sector */
6d0f6bcf JCPV	74	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K)
6d0f6bcf JCPV	75	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
8ed96046 WD	76
	77	/*
	78	* Hardware drivers
	79	*/
082acfd4	80
8ed96046 WD	81	/*
	82	* SMC91c96 Etherent
	83	*/
ac6b362a NM	84	#define CONFIG_NET_MULTI
ac6b362a NM	85	#define CONFIG_LAN91C96
8ed96046 WD	86	#define CONFIG_LAN91C96_BASE (H4_CS1_BASE+0x300)
	87	#define CONFIG_LAN91C96_EXT_PHY
	88
	89	/*
	90	* NS16550 Configuration
	91	*/
	92	#ifdef CONFIG_APTIX
	93	#define V_NS16550_CLK (6000000) /* 6MHz in current MaxSet */
	94	#else
	95	#define V_NS16550_CLK (48000000) /* 48MHz (APLL96/2) */
	96	#endif
	97
6d0f6bcf JCPV	98	#define CONFIG_SYS_NS16550
	99	#define CONFIG_SYS_NS16550_SERIAL
	100	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	101	#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK /* 3MHz (1.5MHz2) /
	102	#define CONFIG_SYS_NS16550_COM1 OMAP2420_UART1
8ed96046 WD	103
	104	/*
	105	* select serial console configuration
	106	*/
	107	#define CONFIG_SERIAL1 1 /* UART1 on H4 */
	108
	109	/*
	110	* I2C configuration
	111	*/
	112	#define CONFIG_HARD_I2C
6d0f6bcf JCPV	113	#define CONFIG_SYS_I2C_SPEED 100000
6d0f6bcf JCPV	114	#define CONFIG_SYS_I2C_SLAVE 1
8ed96046 WD	115	#define CONFIG_DRIVER_OMAP24XX_I2C
	116
	117	/* allow to overwrite serial and ethaddr */
	118	#define CONFIG_ENV_OVERWRITE
	119	#define CONFIG_CONS_INDEX 1
	120	#define CONFIG_BAUDRATE 115200
6d0f6bcf	121	#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
8ed96046	122
a5cb2309 JL	123
	124	/*
	125	* Command line configuration.
	126	*/
	127	#include <config_cmd_default.h>
	128
6d0f6bcf	129	#ifdef CONFIG_SYS_NAND_BOOT
a5cb2309 JL	130	#define CONFIG_CMD_DHCP
	131	#define CONFIG_CMD_I2C
	132	#define CONFIG_CMD_NAND
	133	#define CONFIG_CMD_JFFS2
289f932c	134	#else
a5cb2309 JL	135	#define CONFIG_CMD_DHCP
	136	#define CONFIG_CMD_I2C
	137	#define CONFIG_CMD_JFFS2
	138
74de7aef	139	#undef CONFIG_CMD_SOURCE
289f932c	140	#endif
8ed96046	141
a5cb2309	142
d3b8c1a7 JL	143	/*
	144	* BOOTP options
	145	*/
	146	#define CONFIG_BOOTP_SUBNETMASK
	147	#define CONFIG_BOOTP_GATEWAY
	148	#define CONFIG_BOOTP_HOSTNAME
	149	#define CONFIG_BOOTP_BOOTPATH
	150
8ed96046 WD	151	#define CONFIG_BOOTDELAY 3
	152
	153	#ifdef NFS_BOOT_DEFAULTS
	154	#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw nfsroot=128.247.77.158:/home/a0384864/wtbu/rootfs ip=dhcp"
	155	#else
	156	#define CONFIG_BOOTARGS "root=/dev/ram0 rw mem=32M console=ttyS0,115200n8 initrd=0x80600000,8M ramdisk_size=8192"
	157	#endif
	158
	159	#define CONFIG_NETMASK 255.255.254.0
	160	#define CONFIG_IPADDR 128.247.77.90
	161	#define CONFIG_SERVERIP 128.247.77.158
	162	#define CONFIG_BOOTFILE "uImage"
	163
	164	/*
	165	* Miscellaneous configurable options
	166	*/
1270ec13	167	#define CONFIG_SYS_LONGHELP /* undef to save memory */
8ed96046	168	#ifdef CONFIG_APTIX
1270ec13	169	# define CONFIG_SYS_PROMPT "OMAP2420 Aptix # "
8ed96046	170	#else
1270ec13	171	# define CONFIG_SYS_PROMPT "OMAP242x H4 # "
8ed96046	172	#endif
6d0f6bcf	173	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
8ed96046	174	/* Print Buffer Size */
6d0f6bcf JCPV	175	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
	176	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	177	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
8ed96046	178
6d0f6bcf JCPV	179	#define CONFIG_SYS_MEMTEST_START (OMAP2420_SDRC_CS0) /* memtest works on */
6d0f6bcf JCPV	180	#define CONFIG_SYS_MEMTEST_END (OMAP2420_SDRC_CS0+SZ_31M)
8ed96046	181
6d0f6bcf	182	#define CONFIG_SYS_LOAD_ADDR (OMAP2420_SDRC_CS0) /* default load address */
8ed96046 WD	183
	184	/* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
	185	* 32KHz clk, or from external sig. This rate is divided by a local divisor.
	186	*/
	187	#ifdef CONFIG_APTIX
81472d89	188	#define V_PTV 3
8ed96046	189	#else
81472d89	190	#define V_PTV 7 /* use with 12MHz/128 */
8ed96046 WD	191	#endif
8ed96046 WD	192
81472d89 LM	193	#define CONFIG_SYS_TIMERBASE OMAP2420_GPT2
	194	#define CONFIG_SYS_PTV V_PTV /* 2^(PTV+1) */
	195	#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
8ed96046 WD	196
	197	/*-----------------------------------------------------------------------
	198	* Stack sizes
	199	*
	200	* The stack sizes are set up in start.S using the settings below
	201	*/
	202	#define CONFIG_STACKSIZE SZ_128K /* regular stack */
	203	#ifdef CONFIG_USE_IRQ
	204	#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */
	205	#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */
	206	#endif
	207
	208	/*-----------------------------------------------------------------------
	209	* Physical Memory Map
	210	*/
	211	#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
	212	#define PHYS_SDRAM_1 OMAP2420_SDRC_CS0
	213	#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */
	214	#define PHYS_SDRAM_2 OMAP2420_SDRC_CS1
	215
49a7581c	216	#define PHYS_FLASH_SECT_SIZE SZ_128K
8ed96046 WD	217	#define PHYS_FLASH_1 H4_CS0_BASE /* Flash Bank #1 */
	218	#define PHYS_FLASH_SIZE_1 SZ_32M
	219	#define PHYS_FLASH_2 (H4_CS0_BASE+SZ_32M) /* same cs, 2 chips in series */
	220	#define PHYS_FLASH_SIZE_2 SZ_32M
8ed96046 WD	221
	222	/*-----------------------------------------------------------------------
	223	* FLASH and environment organization
	224	*/
6d0f6bcf JCPV	225	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
	226	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
	227	#define CONFIG_SYS_MAX_FLASH_SECT (259) /* max number of sectors on one chip */
	228	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
	229	#define CONFIG_SYS_MONITOR_LEN SZ_128K /* Reserve 1 sector */
	230	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE_1 }
	231
	232	#ifdef CONFIG_SYS_NAND_BOOT
51bfee19	233	#define CONFIG_ENV_IS_IN_NAND 1
0e8d1586	234	#define CONFIG_ENV_OFFSET 0x80000 /* environment starts here */
289f932c	235	#else
6d0f6bcf	236	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + SZ_128K)
5a1aceb0	237	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586	238	#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE
6d0f6bcf	239	#define CONFIG_ENV_OFFSET ( CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN ) /* Environment after Monitor */
289f932c	240	#endif
8ed96046	241
49a7581c WD	242	/*-----------------------------------------------------------------------
	243	* CFI FLASH driver setup
	244	*/
6d0f6bcf	245	#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */
00b1883a	246	#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */
6d0f6bcf JCPV	247	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
6d0f6bcf JCPV	248	#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */
49a7581c	249
8ed96046	250	/* timeout values are in ticks */
6d0f6bcf JCPV	251	#define CONFIG_SYS_FLASH_ERASE_TOUT (100CONFIG_SYS_HZ) / Timeout for Flash Erase */
6d0f6bcf JCPV	252	#define CONFIG_SYS_FLASH_WRITE_TOUT (100CONFIG_SYS_HZ) / Timeout for Flash Write */
289f932c	253
6d0f6bcf	254	#define CONFIG_SYS_JFFS2_MEM_NAND
700a0c64 WD	255
	256	/*
	257	* JFFS2 partitions
	258	*/
	259	/* No command line, one static partition, whole device */
68d7d651	260	#undef CONFIG_CMD_MTDPARTS
700a0c64 WD	261	#define CONFIG_JFFS2_DEV "nor1"
	262	#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
	263	#define CONFIG_JFFS2_PART_OFFSET 0x00000000
	264
	265	/* mtdparts command line support */
	266	/* Note: fake mtd_id used, no linux mtd map file */
	267	/*
68d7d651	268	#define CONFIG_CMD_MTDPARTS
700a0c64 WD	269	#define MTDIDS_DEFAULT "nor1=omap2420-1"
	270	#define MTDPARTS_DEFAULT "mtdparts=omap2420-1:-(jffs2)"
	271	*/
8ed96046 WD	272
8ed96046 WD	273	#endif /* __CONFIG_H */