[people/ms/u-boot.git] / include / configs / omap2420h4.h

/*
 * (C) Copyright 2004
 * Texas Instruments.
 * Richard Woodruff <r-woodruff2@ti.com>
 * Kshitij Gupta <kshitij@ti.com>
 *
 * Configuration settings for the 242x TI H4 board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_ARM1136           1    /* This is an arm1136 CPU core */
#define CONFIG_OMAP              1    /* in a TI OMAP core */
#define CONFIG_OMAP2420	         1    /* which is in a 2420 */
#define CONFIG_OMAP2420H4        1    /* and on a H4 board */
/*#define CONFIG_APTIX           1    #* define if on APTIX test chip */
/*#define CONFIG_VIRTIO          1    #* Using Virtio simulator */

/* Clock config to target*/
#define PRCM_CONFIG_II	1
/* #define PRCM_CONFIG_III		1 */

#include <asm/arch/omap2420.h>        /* get chip and board defs */

/* On H4, NOR and NAND flash are mutual exclusive.
   Define this if you want to use NAND
 */
/*#define CFG_NAND_BOOT */

#ifdef CONFIG_APTIX
#define V_SCLK                   1500000
#else
#define V_SCLK                   12000000
#endif

/* input clock of PLL */
/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */
#define CONFIG_SYS_CLK_FREQ      V_SCLK

#undef CONFIG_USE_IRQ                 /* no support for IRQs */
#define CONFIG_MISC_INIT_R

#define CONFIG_CMDLINE_TAG       1    /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG        1
#define CONFIG_REVISION_TAG      1

/*
 * Size of malloc() pool
 */
#define CFG_ENV_SIZE             SZ_128K     /* Total Size of Environment Sector */
#define CFG_MALLOC_LEN           (CFG_ENV_SIZE + SZ_128K)
#define CFG_GBL_DATA_SIZE        128  /* size in bytes reserved for initial data */

/*
 * Hardware drivers
 */

/*
 * SMC91c96 Etherent
 */
#define CONFIG_DRIVER_LAN91C96
#define CONFIG_LAN91C96_BASE     (H4_CS1_BASE+0x300)
#define CONFIG_LAN91C96_EXT_PHY

/*
 * NS16550 Configuration
 */
#ifdef CONFIG_APTIX
#define V_NS16550_CLK            (6000000)   /* 6MHz in current MaxSet */
#else
#define V_NS16550_CLK            (48000000)  /* 48MHz (APLL96/2) */
#endif

#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE     (-4)
#define CFG_NS16550_CLK          V_NS16550_CLK   /* 3MHz (1.5MHz*2) */
#define CFG_NS16550_COM1         OMAP2420_UART1

/*
 * select serial console configuration
 */
#define CONFIG_SERIAL1           1    /* UART1 on H4 */

  /*
   * I2C configuration
   */
#define CONFIG_HARD_I2C
#define CFG_I2C_SPEED          100000
#define CFG_I2C_SLAVE          1
#define CONFIG_DRIVER_OMAP24XX_I2C

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX        1
#define CONFIG_BAUDRATE          115200
#define CFG_BAUDRATE_TABLE       {9600, 19200, 38400, 57600, 115200}


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#ifdef CFG_NAND_BOOT
    #define CONFIG_CMD_DHCP
    #define CONFIG_CMD_I2C
    #define CONFIG_CMD_NAND
    #define CONFIG_CMD_JFFS2
#else
    #define CONFIG_CMD_DHCP
    #define CONFIG_CMD_I2C
    #define CONFIG_CMD_JFFS2

    #undef CONFIG_CMD_AUTOSCRIPT
#endif


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH


/*
 *  Board NAND Info.
 */
#define CFG_NAND_LEGACY
#define CFG_NAND_ADDR 0x04000000  /* physical address to access nand at CS0*/

#define CFG_MAX_NAND_DEVICE 1	/* Max number of NAND devices */
#define SECTORSIZE          512

#define ADDR_COLUMN         1
#define ADDR_PAGE           2
#define ADDR_COLUMN_PAGE    3

#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS     1
#define NAND_MAX_CHIPS      1

#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u16 *)0x6800A07C = d;} while(0)
#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u16 *)0x6800A080 = d;} while(0)
#define WRITE_NAND(d, adr) do {*(volatile u16 *)0x6800A084 = d;} while(0)
#define READ_NAND(adr) (*(volatile u16 *)0x6800A084)
#define NAND_WAIT_READY(nand)  udelay(10)

#define NAND_NO_RB          1

#define CFG_NAND_WP
#define NAND_WP_OFF()  do {*(volatile u32 *)(0x6800A050) |= 0x00000010;} while(0)
#define NAND_WP_ON()  do {*(volatile u32 *)(0x6800A050) &= ~0x00000010;} while(0)

#define NAND_CTL_CLRALE(nandptr)
#define NAND_CTL_SETALE(nandptr)
#define NAND_CTL_CLRCLE(nandptr)
#define NAND_CTL_SETCLE(nandptr)
#define NAND_DISABLE_CE(nand)
#define NAND_ENABLE_CE(nand)

#define CONFIG_BOOTDELAY         3

#ifdef NFS_BOOT_DEFAULTS
#define CONFIG_BOOTARGS	         "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw nfsroot=128.247.77.158:/home/a0384864/wtbu/rootfs ip=dhcp"
#else
#define CONFIG_BOOTARGS          "root=/dev/ram0 rw mem=32M console=ttyS0,115200n8 initrd=0x80600000,8M ramdisk_size=8192"
#endif

#define CONFIG_NETMASK           255.255.254.0
#define CONFIG_IPADDR            128.247.77.90
#define CONFIG_SERVERIP          128.247.77.158
#define CONFIG_BOOTFILE          "uImage"

/*
 * Miscellaneous configurable options
 */
#ifdef CONFIG_APTIX
#define V_PROMPT                 "OMAP2420 Aptix # "
#else
#define V_PROMPT                 "OMAP242x H4 # "
#endif

#define CFG_LONGHELP             /* undef to save memory */
#define CFG_PROMPT               V_PROMPT
#define CFG_CBSIZE               256  /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CFG_PBSIZE               (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
#define CFG_MAXARGS              16          /* max number of command args */
#define CFG_BARGSIZE             CFG_CBSIZE  /* Boot Argument Buffer Size */

#define CFG_MEMTEST_START        (OMAP2420_SDRC_CS0)  /* memtest works on */
#define CFG_MEMTEST_END          (OMAP2420_SDRC_CS0+SZ_31M)

#undef	CFG_CLKS_IN_HZ           /* everything, incl board info, in Hz */

#define CFG_LOAD_ADDR            (OMAP2420_SDRC_CS0) /* default load address */

/* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
 * 32KHz clk, or from external sig. This rate is divided by a local divisor.
 */
#ifdef CONFIG_APTIX
#define V_PVT                    3
#else
#define V_PVT                    7  /* use with 12MHz/128 */
#endif

#define CFG_TIMERBASE            OMAP2420_GPT2
#define CFG_PVT                  V_PVT  /* 2^(pvt+1) */
#define CFG_HZ	                 ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))

/*-----------------------------------------------------------------------
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE         SZ_128K /* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ     SZ_4K   /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ     SZ_4K   /* FIQ stack */
#endif

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS     2                 /* CS1 may or may not be populated */
#define PHYS_SDRAM_1             OMAP2420_SDRC_CS0
#define PHYS_SDRAM_1_SIZE        SZ_32M            /* at least 32 meg */
#define PHYS_SDRAM_2             OMAP2420_SDRC_CS1

#define PHYS_FLASH_SECT_SIZE     SZ_128K
#define PHYS_FLASH_1             H4_CS0_BASE	   /* Flash Bank #1 */
#define PHYS_FLASH_SIZE_1        SZ_32M
#define PHYS_FLASH_2             (H4_CS0_BASE+SZ_32M) /* same cs, 2 chips in series */
#define PHYS_FLASH_SIZE_2        SZ_32M

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */
#define CFG_FLASH_BASE           PHYS_FLASH_1
#define CFG_MAX_FLASH_BANKS      2           /* max number of memory banks */
#define CFG_MAX_FLASH_SECT       (259)	     /* max number of sectors on one chip */
#define CFG_MONITOR_BASE	CFG_FLASH_BASE /* Monitor at beginning of flash */
#define CFG_MONITOR_LEN		SZ_128K      /* Reserve 1 sector */
#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE, CFG_FLASH_BASE + PHYS_FLASH_SIZE_1 }

#ifdef CFG_NAND_BOOT
#define CFG_ENV_IS_IN_NAND	1
#define CFG_ENV_OFFSET	0x80000	/* environment starts here  */
#else
#define CFG_ENV_ADDR             (CFG_FLASH_BASE + SZ_128K)
#define	CFG_ENV_IS_IN_FLASH      1
#define CFG_ENV_SECT_SIZE	PHYS_FLASH_SECT_SIZE
#define CFG_ENV_OFFSET	( CFG_MONITOR_BASE + CFG_MONITOR_LEN ) /* Environment after Monitor */
#endif

/*-----------------------------------------------------------------------
 * CFI FLASH driver setup
 */
#define CFG_FLASH_CFI		1	/* Flash memory is CFI compliant */
#define CFG_FLASH_CFI_DRIVER	1	/* Use drivers/cfi_flash.c */
#define CFG_FLASH_USE_BUFFER_WRITE 1	/* Use buffered writes (~10x faster) */
#define CFG_FLASH_PROTECTION	1	/* Use hardware sector protection */

/* timeout values are in ticks */
#define CFG_FLASH_ERASE_TOUT     (100*CFG_HZ) /* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT     (100*CFG_HZ) /* Timeout for Flash Write */

#define CFG_JFFS2_MEM_NAND

/*
 * JFFS2 partitions
 */
/* No command line, one static partition, whole device */
#undef CONFIG_JFFS2_CMDLINE
#define CONFIG_JFFS2_DEV		"nor1"
#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
#define CONFIG_JFFS2_PART_OFFSET	0x00000000

/* mtdparts command line support */
/* Note: fake mtd_id used, no linux mtd map file */
/*
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT		"nor1=omap2420-1"
#define MTDPARTS_DEFAULT	"mtdparts=omap2420-1:-(jffs2)"
*/

#endif							/* __CONFIG_H */
Commit	Line	Data
8ed96046 WD	1	/*
	2	* (C) Copyright 2004
	3	* Texas Instruments.
	4	* Richard Woodruff <r-woodruff2@ti.com>
	5	* Kshitij Gupta <kshitij@ti.com>
	6	*
	7	* Configuration settings for the 242x TI H4 board.
	8	*
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	*/
	34	#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
	35	#define CONFIG_OMAP 1 /* in a TI OMAP core */
	36	#define CONFIG_OMAP2420 1 /* which is in a 2420 */
	37	#define CONFIG_OMAP2420H4 1 /* and on a H4 board */
082acfd4 WD	38	/#define CONFIG_APTIX 1 # define if on APTIX test chip */
082acfd4 WD	39	/#define CONFIG_VIRTIO 1 # Using Virtio simulator */
8ed96046	40
289f932c	41	/* Clock config to target*/
49a7581c	42	#define PRCM_CONFIG_II 1
716c1dcb	43	/* #define PRCM_CONFIG_III 1 */
8ed96046 WD	44
	45	#include <asm/arch/omap2420.h> /* get chip and board defs */
	46
289f932c WD	47	/* On H4, NOR and NAND flash are mutual exclusive.
	48	Define this if you want to use NAND
	49	*/
5a95f6fb	50	/#define CFG_NAND_BOOT /
289f932c	51
8ed96046 WD	52	#ifdef CONFIG_APTIX
	53	#define V_SCLK 1500000
	54	#else
	55	#define V_SCLK 12000000
	56	#endif
	57
	58	/* input clock of PLL */
	59	/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */
	60	#define CONFIG_SYS_CLK_FREQ V_SCLK
	61
	62	#undef CONFIG_USE_IRQ /* no support for IRQs */
	63	#define CONFIG_MISC_INIT_R
	64
	65	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	66	#define CONFIG_SETUP_MEMORY_TAGS 1
	67	#define CONFIG_INITRD_TAG 1
289f932c	68	#define CONFIG_REVISION_TAG 1
8ed96046 WD	69
	70	/*
	71	* Size of malloc() pool
	72	*/
	73	#define CFG_ENV_SIZE SZ_128K /* Total Size of Environment Sector */
	74	#define CFG_MALLOC_LEN (CFG_ENV_SIZE + SZ_128K)
	75	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	76
	77	/*
	78	* Hardware drivers
	79	*/
082acfd4	80
8ed96046 WD	81	/*
	82	* SMC91c96 Etherent
	83	*/
	84	#define CONFIG_DRIVER_LAN91C96
	85	#define CONFIG_LAN91C96_BASE (H4_CS1_BASE+0x300)
	86	#define CONFIG_LAN91C96_EXT_PHY
	87
	88	/*
	89	* NS16550 Configuration
	90	*/
	91	#ifdef CONFIG_APTIX
	92	#define V_NS16550_CLK (6000000) /* 6MHz in current MaxSet */
	93	#else
	94	#define V_NS16550_CLK (48000000) /* 48MHz (APLL96/2) */
	95	#endif
	96
	97	#define CFG_NS16550
	98	#define CFG_NS16550_SERIAL
	99	#define CFG_NS16550_REG_SIZE (-4)
	100	#define CFG_NS16550_CLK V_NS16550_CLK /* 3MHz (1.5MHz2) /
	101	#define CFG_NS16550_COM1 OMAP2420_UART1
	102
	103	/*
	104	* select serial console configuration
	105	*/
	106	#define CONFIG_SERIAL1 1 /* UART1 on H4 */
	107
	108	/*
	109	* I2C configuration
	110	*/
	111	#define CONFIG_HARD_I2C
	112	#define CFG_I2C_SPEED 100000
	113	#define CFG_I2C_SLAVE 1
	114	#define CONFIG_DRIVER_OMAP24XX_I2C
	115
	116	/* allow to overwrite serial and ethaddr */
	117	#define CONFIG_ENV_OVERWRITE
	118	#define CONFIG_CONS_INDEX 1
	119	#define CONFIG_BAUDRATE 115200
	120	#define CFG_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
	121
a5cb2309 JL	122
	123	/*
	124	* Command line configuration.
	125	*/
	126	#include <config_cmd_default.h>
	127
289f932c	128	#ifdef CFG_NAND_BOOT
a5cb2309 JL	129	#define CONFIG_CMD_DHCP
	130	#define CONFIG_CMD_I2C
	131	#define CONFIG_CMD_NAND
	132	#define CONFIG_CMD_JFFS2
289f932c	133	#else
a5cb2309 JL	134	#define CONFIG_CMD_DHCP
	135	#define CONFIG_CMD_I2C
	136	#define CONFIG_CMD_JFFS2
	137
	138	#undef CONFIG_CMD_AUTOSCRIPT
289f932c	139	#endif
8ed96046	140
a5cb2309	141
d3b8c1a7 JL	142	/*
	143	* BOOTP options
	144	*/
	145	#define CONFIG_BOOTP_SUBNETMASK
	146	#define CONFIG_BOOTP_GATEWAY
	147	#define CONFIG_BOOTP_HOSTNAME
	148	#define CONFIG_BOOTP_BOOTPATH
	149
8ed96046	150
289f932c WD	151	/*
	152	* Board NAND Info.
	153	*/
6db39708	154	#define CFG_NAND_LEGACY
289f932c WD	155	#define CFG_NAND_ADDR 0x04000000 /* physical address to access nand at CS0*/
	156
	157	#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
	158	#define SECTORSIZE 512
	159
	160	#define ADDR_COLUMN 1
	161	#define ADDR_PAGE 2
	162	#define ADDR_COLUMN_PAGE 3
	163
	164	#define NAND_ChipID_UNKNOWN 0x00
	165	#define NAND_MAX_FLOORS 1
	166	#define NAND_MAX_CHIPS 1
	167
	168	#define WRITE_NAND_COMMAND(d, adr) do {(volatile u16 )0x6800A07C = d;} while(0)
	169	#define WRITE_NAND_ADDRESS(d, adr) do {(volatile u16 )0x6800A080 = d;} while(0)
	170	#define WRITE_NAND(d, adr) do {(volatile u16 )0x6800A084 = d;} while(0)
	171	#define READ_NAND(adr) ((volatile u16 )0x6800A084)
	172	#define NAND_WAIT_READY(nand) udelay(10)
	173
	174	#define NAND_NO_RB 1
	175
	176	#define CFG_NAND_WP
	177	#define NAND_WP_OFF() do {(volatile u32 )(0x6800A050) \|= 0x00000010;} while(0)
	178	#define NAND_WP_ON() do {(volatile u32 )(0x6800A050) &= ~0x00000010;} while(0)
	179
289f932c WD	180	#define NAND_CTL_CLRALE(nandptr)
	181	#define NAND_CTL_SETALE(nandptr)
	182	#define NAND_CTL_CLRCLE(nandptr)
	183	#define NAND_CTL_SETCLE(nandptr)
	184	#define NAND_DISABLE_CE(nand)
	185	#define NAND_ENABLE_CE(nand)
	186
8ed96046 WD	187	#define CONFIG_BOOTDELAY 3
	188
	189	#ifdef NFS_BOOT_DEFAULTS
	190	#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw nfsroot=128.247.77.158:/home/a0384864/wtbu/rootfs ip=dhcp"
	191	#else
	192	#define CONFIG_BOOTARGS "root=/dev/ram0 rw mem=32M console=ttyS0,115200n8 initrd=0x80600000,8M ramdisk_size=8192"
	193	#endif
	194
	195	#define CONFIG_NETMASK 255.255.254.0
	196	#define CONFIG_IPADDR 128.247.77.90
	197	#define CONFIG_SERVERIP 128.247.77.158
	198	#define CONFIG_BOOTFILE "uImage"
	199
	200	/*
	201	* Miscellaneous configurable options
	202	*/
	203	#ifdef CONFIG_APTIX
	204	#define V_PROMPT "OMAP2420 Aptix # "
	205	#else
	206	#define V_PROMPT "OMAP242x H4 # "
	207	#endif
	208
	209	#define CFG_LONGHELP /* undef to save memory */
	210	#define CFG_PROMPT V_PROMPT
	211	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	212	/* Print Buffer Size */
	213	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
	214	#define CFG_MAXARGS 16 /* max number of command args */
	215	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	216
	217	#define CFG_MEMTEST_START (OMAP2420_SDRC_CS0) /* memtest works on */
	218	#define CFG_MEMTEST_END (OMAP2420_SDRC_CS0+SZ_31M)
	219
	220	#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
	221
	222	#define CFG_LOAD_ADDR (OMAP2420_SDRC_CS0) /* default load address */
	223
	224	/* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
	225	* 32KHz clk, or from external sig. This rate is divided by a local divisor.
	226	*/
	227	#ifdef CONFIG_APTIX
	228	#define V_PVT 3
	229	#else
	230	#define V_PVT 7 /* use with 12MHz/128 */
	231	#endif
	232
	233	#define CFG_TIMERBASE OMAP2420_GPT2
	234	#define CFG_PVT V_PVT /* 2^(pvt+1) */
	235	#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
	236
	237	/*-----------------------------------------------------------------------
	238	* Stack sizes
	239	*
	240	* The stack sizes are set up in start.S using the settings below
	241	*/
	242	#define CONFIG_STACKSIZE SZ_128K /* regular stack */
	243	#ifdef CONFIG_USE_IRQ
	244	#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */
	245	#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */
	246	#endif
	247
	248	/*-----------------------------------------------------------------------
	249	* Physical Memory Map
	250	*/
251	#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
252	#define PHYS_SDRAM_1 OMAP2420_SDRC_CS0
253	#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */
254	#define PHYS_SDRAM_2 OMAP2420_SDRC_CS1
255
49a7581c	256	#define PHYS_FLASH_SECT_SIZE SZ_128K
8ed96046 WD	257	#define PHYS_FLASH_1 H4_CS0_BASE /* Flash Bank #1 */
	258	#define PHYS_FLASH_SIZE_1 SZ_32M
	259	#define PHYS_FLASH_2 (H4_CS0_BASE+SZ_32M) /* same cs, 2 chips in series */
	260	#define PHYS_FLASH_SIZE_2 SZ_32M
8ed96046 WD	261
	262	/*-----------------------------------------------------------------------
	263	* FLASH and environment organization
	264	*/
49a7581c	265	#define CFG_FLASH_BASE PHYS_FLASH_1
8ed96046 WD	266	#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
8ed96046 WD	267	#define CFG_MAX_FLASH_SECT (259) /* max number of sectors on one chip */
49a7581c WD	268	#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at beginning of flash */
	269	#define CFG_MONITOR_LEN SZ_128K /* Reserve 1 sector */
	270	#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE + PHYS_FLASH_SIZE_1 }
8ed96046	271
289f932c WD	272	#ifdef CFG_NAND_BOOT
	273	#define CFG_ENV_IS_IN_NAND 1
	274	#define CFG_ENV_OFFSET 0x80000 /* environment starts here */
	275	#else
8ed96046 WD	276	#define CFG_ENV_ADDR (CFG_FLASH_BASE + SZ_128K)
8ed96046 WD	277	#define CFG_ENV_IS_IN_FLASH 1
49a7581c WD	278	#define CFG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE
49a7581c WD	279	#define CFG_ENV_OFFSET ( CFG_MONITOR_BASE + CFG_MONITOR_LEN ) /* Environment after Monitor */
289f932c	280	#endif
8ed96046	281
49a7581c WD	282	/*-----------------------------------------------------------------------
	283	* CFI FLASH driver setup
	284	*/
	285	#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */
	286	#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
	287	#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
	288	#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */
	289
8ed96046	290	/* timeout values are in ticks */
49a7581c WD	291	#define CFG_FLASH_ERASE_TOUT (100CFG_HZ) / Timeout for Flash Erase */
49a7581c WD	292	#define CFG_FLASH_WRITE_TOUT (100CFG_HZ) / Timeout for Flash Write */
289f932c	293
289f932c	294	#define CFG_JFFS2_MEM_NAND
700a0c64 WD	295
	296	/*
	297	* JFFS2 partitions
	298	*/
	299	/* No command line, one static partition, whole device */
	300	#undef CONFIG_JFFS2_CMDLINE
	301	#define CONFIG_JFFS2_DEV "nor1"
	302	#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
	303	#define CONFIG_JFFS2_PART_OFFSET 0x00000000
	304
	305	/* mtdparts command line support */
	306	/* Note: fake mtd_id used, no linux mtd map file */
	307	/*
	308	#define CONFIG_JFFS2_CMDLINE
	309	#define MTDIDS_DEFAULT "nor1=omap2420-1"
	310	#define MTDPARTS_DEFAULT "mtdparts=omap2420-1:-(jffs2)"
	311	*/
8ed96046 WD	312
8ed96046 WD	313	#endif /* __CONFIG_H */