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f904cdbb DB |
1 | /* |
2 | * (C) Copyright 2006-2008 | |
3 | * Texas Instruments. | |
4 | * Richard Woodruff <r-woodruff2@ti.com> | |
5 | * Syed Mohammed Khasim <x0khasim@ti.com> | |
6 | * | |
7 | * Configuration settings for the TI OMAP3530 Beagle board. | |
8 | * | |
9 | * See file CREDITS for list of people who contributed to this | |
10 | * project. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of | |
15 | * the License, or (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
25 | * MA 02111-1307 USA | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
f904cdbb DB |
30 | |
31 | /* | |
32 | * High Level Configuration Options | |
33 | */ | |
f56348af | 34 | #define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ |
f904cdbb DB |
35 | #define CONFIG_OMAP 1 /* in a TI OMAP core */ |
36 | #define CONFIG_OMAP34XX 1 /* which is a 34XX */ | |
37 | #define CONFIG_OMAP3430 1 /* which is in a 3430 */ | |
38 | #define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */ | |
39 | ||
cae377b5 VH |
40 | #define CONFIG_SDRC /* The chip has SDRC controller */ |
41 | ||
f904cdbb DB |
42 | #include <asm/arch/cpu.h> /* get chip and board defs */ |
43 | #include <asm/arch/omap3.h> | |
44 | ||
6a6b62e3 SP |
45 | /* |
46 | * Display CPU and Board information | |
47 | */ | |
48 | #define CONFIG_DISPLAY_CPUINFO 1 | |
49 | #define CONFIG_DISPLAY_BOARDINFO 1 | |
50 | ||
f904cdbb DB |
51 | /* Clock Defines */ |
52 | #define V_OSCK 26000000 /* Clock output from T2 */ | |
53 | #define V_SCLK (V_OSCK >> 1) | |
54 | ||
55 | #undef CONFIG_USE_IRQ /* no support for IRQs */ | |
56 | #define CONFIG_MISC_INIT_R | |
57 | ||
b485556b JR |
58 | #define CONFIG_OF_LIBFDT 1 |
59 | /* | |
60 | * The early kernel mapping on ARM currently only maps from the base of DRAM | |
61 | * to the end of the kernel image. The kernel is loaded at DRAM base + 0x8000. | |
62 | * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000, | |
63 | * so that leaves DRAM base to DRAM base + 0x4000 available. | |
64 | */ | |
65 | #define CONFIG_SYS_BOOTMAPSZ 0x4000 | |
66 | ||
f904cdbb DB |
67 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
68 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
69 | #define CONFIG_INITRD_TAG 1 | |
70 | #define CONFIG_REVISION_TAG 1 | |
71 | ||
72 | /* | |
73 | * Size of malloc() pool | |
74 | */ | |
9c44ddcc | 75 | #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ |
f904cdbb | 76 | /* Sector */ |
9c44ddcc | 77 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) |
f904cdbb DB |
78 | /* initial data */ |
79 | ||
80 | /* | |
81 | * Hardware drivers | |
82 | */ | |
83 | ||
84 | /* | |
85 | * NS16550 Configuration | |
86 | */ | |
87 | #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ | |
88 | ||
89 | #define CONFIG_SYS_NS16550 | |
90 | #define CONFIG_SYS_NS16550_SERIAL | |
91 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) | |
92 | #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK | |
93 | ||
94 | /* | |
95 | * select serial console configuration | |
96 | */ | |
97 | #define CONFIG_CONS_INDEX 3 | |
98 | #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 | |
99 | #define CONFIG_SERIAL3 3 /* UART3 on Beagle Rev 2 */ | |
100 | ||
101 | /* allow to overwrite serial and ethaddr */ | |
102 | #define CONFIG_ENV_OVERWRITE | |
103 | #define CONFIG_BAUDRATE 115200 | |
104 | #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ | |
105 | 115200} | |
0cd31144 | 106 | #define CONFIG_GENERIC_MMC 1 |
f904cdbb | 107 | #define CONFIG_MMC 1 |
0cd31144 | 108 | #define CONFIG_OMAP_HSMMC 1 |
f904cdbb DB |
109 | #define CONFIG_DOS_PARTITION 1 |
110 | ||
30563a04 NM |
111 | /* DDR - I use Micron DDR */ |
112 | #define CONFIG_OMAP3_MICRON_DDR 1 | |
113 | ||
25374bfb TR |
114 | /* USB */ |
115 | #define CONFIG_MUSB_UDC 1 | |
116 | #define CONFIG_USB_OMAP3 1 | |
117 | #define CONFIG_TWL4030_USB 1 | |
118 | ||
119 | /* USB device configuration */ | |
120 | #define CONFIG_USB_DEVICE 1 | |
121 | #define CONFIG_USB_TTY 1 | |
122 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 | |
25374bfb | 123 | |
f904cdbb DB |
124 | /* commands to include */ |
125 | #include <config_cmd_default.h> | |
126 | ||
95c6f6d3 | 127 | #define CONFIG_CMD_CACHE |
f904cdbb DB |
128 | #define CONFIG_CMD_EXT2 /* EXT2 Support */ |
129 | #define CONFIG_CMD_FAT /* FAT support */ | |
130 | #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ | |
917cfc70 | 131 | #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ |
942556a9 | 132 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
917cfc70 NM |
133 | #define MTDIDS_DEFAULT "nand0=nand" |
134 | #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ | |
135 | "1920k(u-boot),128k(u-boot-env),"\ | |
136 | "4m(kernel),-(fs)" | |
f904cdbb DB |
137 | |
138 | #define CONFIG_CMD_I2C /* I2C serial bus support */ | |
139 | #define CONFIG_CMD_MMC /* MMC support */ | |
140 | #define CONFIG_CMD_NAND /* NAND support */ | |
141 | ||
142 | #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ | |
143 | #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ | |
144 | #undef CONFIG_CMD_IMI /* iminfo */ | |
145 | #undef CONFIG_CMD_IMLS /* List all found images */ | |
146 | #undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ | |
147 | #undef CONFIG_CMD_NFS /* NFS support */ | |
148 | ||
149 | #define CONFIG_SYS_NO_FLASH | |
0297ec7e | 150 | #define CONFIG_HARD_I2C 1 |
f904cdbb DB |
151 | #define CONFIG_SYS_I2C_SPEED 100000 |
152 | #define CONFIG_SYS_I2C_SLAVE 1 | |
153 | #define CONFIG_SYS_I2C_BUS 0 | |
154 | #define CONFIG_SYS_I2C_BUS_SELECT 1 | |
155 | #define CONFIG_DRIVER_OMAP34XX_I2C 1 | |
156 | ||
2c155130 TR |
157 | /* |
158 | * TWL4030 | |
159 | */ | |
160 | #define CONFIG_TWL4030_POWER 1 | |
161 | #define CONFIG_TWL4030_LED 1 | |
162 | ||
f904cdbb DB |
163 | /* |
164 | * Board NAND Info. | |
165 | */ | |
60c23173 | 166 | #define CONFIG_SYS_NAND_QUIET_TEST 1 |
f904cdbb DB |
167 | #define CONFIG_NAND_OMAP_GPMC |
168 | #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ | |
169 | /* to access nand */ | |
170 | #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ | |
171 | /* to access nand at */ | |
172 | /* CS0 */ | |
173 | #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 | |
174 | ||
175 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ | |
176 | /* devices */ | |
f904cdbb DB |
177 | #define CONFIG_JFFS2_NAND |
178 | /* nand device jffs2 lives on */ | |
179 | #define CONFIG_JFFS2_DEV "nand0" | |
180 | /* start of jffs2 partition */ | |
181 | #define CONFIG_JFFS2_PART_OFFSET 0x680000 | |
182 | #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ | |
183 | /* partition */ | |
184 | ||
185 | /* Environment information */ | |
186 | #define CONFIG_BOOTDELAY 10 | |
187 | ||
188 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
189 | "loadaddr=0x82000000\0" \ | |
25374bfb | 190 | "usbtty=cdc_acm\0" \ |
f904cdbb | 191 | "console=ttyS2,115200n8\0" \ |
5af32460 | 192 | "mpurate=500\0" \ |
13d2cb98 SS |
193 | "vram=12M\0" \ |
194 | "dvimode=1024x768MR-16@60\0" \ | |
195 | "defaultdisplay=dvi\0" \ | |
0cd31144 | 196 | "mmcdev=0\0" \ |
13d2cb98 SS |
197 | "mmcroot=/dev/mmcblk0p2 rw\0" \ |
198 | "mmcrootfstype=ext3 rootwait\0" \ | |
199 | "nandroot=/dev/mtdblock4 rw\0" \ | |
200 | "nandrootfstype=jffs2\0" \ | |
f904cdbb | 201 | "mmcargs=setenv bootargs console=${console} " \ |
5af32460 | 202 | "mpurate=${mpurate} " \ |
13d2cb98 SS |
203 | "vram=${vram} " \ |
204 | "omapfb.mode=dvi:${dvimode} " \ | |
205 | "omapfb.debug=y " \ | |
206 | "omapdss.def_disp=${defaultdisplay} " \ | |
207 | "root=${mmcroot} " \ | |
208 | "rootfstype=${mmcrootfstype}\0" \ | |
f904cdbb | 209 | "nandargs=setenv bootargs console=${console} " \ |
5af32460 | 210 | "mpurate=${mpurate} " \ |
13d2cb98 SS |
211 | "vram=${vram} " \ |
212 | "omapfb.mode=dvi:${dvimode} " \ | |
213 | "omapfb.debug=y " \ | |
214 | "omapdss.def_disp=${defaultdisplay} " \ | |
215 | "root=${nandroot} " \ | |
216 | "rootfstype=${nandrootfstype}\0" \ | |
0cd31144 | 217 | "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ |
f904cdbb | 218 | "bootscript=echo Running bootscript from mmc ...; " \ |
74de7aef | 219 | "source ${loadaddr}\0" \ |
0cd31144 | 220 | "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ |
f904cdbb DB |
221 | "mmcboot=echo Booting from mmc ...; " \ |
222 | "run mmcargs; " \ | |
223 | "bootm ${loadaddr}\0" \ | |
224 | "nandboot=echo Booting from nand ...; " \ | |
225 | "run nandargs; " \ | |
226 | "nand read ${loadaddr} 280000 400000; " \ | |
227 | "bootm ${loadaddr}\0" \ | |
228 | ||
229 | #define CONFIG_BOOTCOMMAND \ | |
0cd31144 | 230 | "if mmc rescan ${mmcdev}; then " \ |
f904cdbb DB |
231 | "if run loadbootscript; then " \ |
232 | "run bootscript; " \ | |
233 | "else " \ | |
234 | "if run loaduimage; then " \ | |
235 | "run mmcboot; " \ | |
236 | "else run nandboot; " \ | |
237 | "fi; " \ | |
238 | "fi; " \ | |
239 | "else run nandboot; fi" | |
240 | ||
241 | #define CONFIG_AUTO_COMPLETE 1 | |
242 | /* | |
243 | * Miscellaneous configurable options | |
244 | */ | |
f904cdbb DB |
245 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
246 | #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ | |
247 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
1270ec13 | 248 | #define CONFIG_SYS_PROMPT "OMAP3 beagleboard.org # " |
f904cdbb DB |
249 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
250 | /* Print Buffer Size */ | |
251 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
252 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
253 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
254 | /* Boot Argument Buffer Size */ | |
255 | #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) | |
256 | ||
257 | #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ | |
258 | /* works on */ | |
259 | #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ | |
260 | 0x01F00000) /* 31MB */ | |
261 | ||
f904cdbb DB |
262 | #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ |
263 | /* load address */ | |
264 | ||
265 | /* | |
d3a513c2 MP |
266 | * OMAP3 has 12 GP timers, they can be driven by the system clock |
267 | * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). | |
268 | * This rate is divided by a local divisor. | |
f904cdbb | 269 | */ |
f904cdbb | 270 | #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) |
d3a513c2 MP |
271 | #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ |
272 | #define CONFIG_SYS_HZ 1000 | |
f904cdbb DB |
273 | |
274 | /*----------------------------------------------------------------------- | |
275 | * Stack sizes | |
276 | * | |
277 | * The stack sizes are set up in start.S using the settings below | |
278 | */ | |
9c44ddcc | 279 | #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ |
f904cdbb | 280 | #ifdef CONFIG_USE_IRQ |
9c44ddcc SP |
281 | #define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ |
282 | #define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ | |
f904cdbb DB |
283 | #endif |
284 | ||
285 | /*----------------------------------------------------------------------- | |
286 | * Physical Memory Map | |
287 | */ | |
288 | #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ | |
289 | #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 | |
9c44ddcc | 290 | #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ |
f904cdbb DB |
291 | #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 |
292 | ||
293 | /* SDRAM Bank Allocation method */ | |
294 | #define SDRC_R_B_C 1 | |
295 | ||
296 | /*----------------------------------------------------------------------- | |
297 | * FLASH and environment organization | |
298 | */ | |
299 | ||
300 | /* **** PISMO SUPPORT *** */ | |
301 | ||
302 | /* Configure the PISMO */ | |
303 | #define PISMO1_NAND_SIZE GPMC_SIZE_128M | |
304 | #define PISMO1_ONEN_SIZE GPMC_SIZE_128M | |
305 | ||
306 | #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */ | |
307 | /* one chip */ | |
308 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ | |
9c44ddcc | 309 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ |
f904cdbb DB |
310 | |
311 | #define CONFIG_SYS_FLASH_BASE boot_flash_base | |
312 | ||
313 | /* Monitor at start of flash */ | |
314 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
315 | #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP | |
316 | ||
317 | #define CONFIG_ENV_IS_IN_NAND 1 | |
318 | #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ | |
319 | #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ | |
320 | ||
321 | #define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec | |
322 | #define CONFIG_ENV_OFFSET boot_flash_off | |
323 | #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET | |
324 | ||
325 | /*----------------------------------------------------------------------- | |
326 | * CFI FLASH driver setup | |
327 | */ | |
328 | /* timeout values are in ticks */ | |
329 | #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) | |
330 | #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) | |
331 | ||
332 | /* Flash banks JFFS2 should use */ | |
333 | #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ | |
334 | CONFIG_SYS_MAX_NAND_DEVICE) | |
335 | #define CONFIG_SYS_JFFS2_MEM_NAND | |
336 | /* use flash_info[2] */ | |
337 | #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS | |
338 | #define CONFIG_SYS_JFFS2_NUM_BANKS 1 | |
339 | ||
340 | #ifndef __ASSEMBLY__ | |
f904cdbb DB |
341 | extern unsigned int boot_flash_base; |
342 | extern volatile unsigned int boot_flash_env_addr; | |
343 | extern unsigned int boot_flash_off; | |
344 | extern unsigned int boot_flash_sec; | |
345 | extern unsigned int boot_flash_type; | |
346 | #endif | |
347 | ||
a784c01a | 348 | /* additions for new relocation code, must be added to all boards */ |
561142af | 349 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
25ddd1fb | 350 | #define CONFIG_SYS_INIT_SP_ADDR (LOW_LEVEL_SRAM_STACK - GENERATED_GBL_DATA_SIZE) |
561142af | 351 | |
f904cdbb | 352 | #endif /* __CONFIG_H */ |