[people/ms/u-boot.git] / include / configs / omap3_beagle.h

/*
 * (C) Copyright 2006-2008
 * Texas Instruments.
 * Richard Woodruff <r-woodruff2@ti.com>
 * Syed Mohammed Khasim <x0khasim@ti.com>
 *
 * Configuration settings for the TI OMAP3530 Beagle board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_OMAP		1	/* in a TI OMAP core */
#define CONFIG_OMAP34XX		1	/* which is a 34XX */
#define CONFIG_OMAP3_BEAGLE	1	/* working with BEAGLE */
#define CONFIG_OMAP_GPIO

#define CONFIG_SDRC	/* The chip has SDRC controller */

#include <asm/arch/cpu.h>		/* get chip and board defs */
#include <asm/arch/omap3.h>

/*
 * Display CPU and Board information
 */
#define CONFIG_DISPLAY_CPUINFO		1
#define CONFIG_DISPLAY_BOARDINFO	1

/* Clock Defines */
#define V_OSCK			26000000	/* Clock output from T2 */
#define V_SCLK			(V_OSCK >> 1)

#define CONFIG_MISC_INIT_R

#define CONFIG_OF_LIBFDT
#define CONFIG_CMD_BOOTZ

#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_INITRD_TAG		1
#define CONFIG_REVISION_TAG		1

/*
 * Size of malloc() pool
 */
#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
						/* Sector */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))

/*
 * Hardware drivers
 */

/*
 * NS16550 Configuration
 */
#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */

#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK

/*
 * select serial console configuration
 */
#define CONFIG_CONS_INDEX		3
#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
#define CONFIG_SERIAL3			3	/* UART3 on Beagle Rev 2 */

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
					115200}
#define CONFIG_GENERIC_MMC		1
#define CONFIG_MMC			1
#define CONFIG_OMAP_HSMMC		1
#define CONFIG_DOS_PARTITION		1

/* Status LED */
#define CONFIG_STATUS_LED		1
#define CONFIG_BOARD_SPECIFIC_LED	1
#define STATUS_LED_BIT			0x01
#define STATUS_LED_STATE		STATUS_LED_ON
#define STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 2)
#define STATUS_LED_BIT1			0x02
#define STATUS_LED_STATE1		STATUS_LED_ON
#define STATUS_LED_PERIOD1		(CONFIG_SYS_HZ / 2)
#define STATUS_LED_BOOT			STATUS_LED_BIT
#define STATUS_LED_GREEN		STATUS_LED_BIT1

/* Enable Multi Bus support for I2C */
#define CONFIG_I2C_MULTI_BUS		1

/* Probe all devices */
#define CONFIG_SYS_I2C_NOPROBES		{{0x0, 0x0}}

/* USB */
#define CONFIG_MUSB_GADGET
#define CONFIG_USB_MUSB_OMAP2PLUS
#define CONFIG_MUSB_PIO_ONLY
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_TWL4030_USB		1
#define CONFIG_USB_ETHER
#define CONFIG_USB_ETHER_RNDIS

/* USB EHCI */
#define CONFIG_CMD_USB
#define CONFIG_USB_EHCI

#define CONFIG_USB_EHCI_OMAP
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO	147

#define CONFIG_USB_ULPI
#define CONFIG_USB_ULPI_VIEWPORT_OMAP

#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_SMSC95XX
#define CONFIG_USB_ETHER_ASIX


/* commands to include */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV

#define CONFIG_CMD_CACHE
#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
#define CONFIG_CMD_FAT		/* FAT support			*/
#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
#define CONFIG_CMD_MTDPARTS	/* Enable MTD parts commands */
#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
#define MTDIDS_DEFAULT			"nand0=nand"
#define MTDPARTS_DEFAULT		"mtdparts=nand:512k(x-loader),"\
					"1920k(u-boot),128k(u-boot-env),"\
					"4m(kernel),-(fs)"

#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
#define CONFIG_CMD_MMC		/* MMC support			*/
#define CONFIG_USB_STORAGE	/* USB storage support		*/
#define CONFIG_CMD_NAND		/* NAND support			*/
#define CONFIG_CMD_LED		/* LED support			*/
#define CONFIG_CMD_NET      /* bootp, tftpboot, rarpboot    */
#define CONFIG_CMD_NFS      /* NFS support          */
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_SETEXPR	/* Evaluate expressions		*/
#define CONFIG_CMD_GPIO     /* Enable gpio command */

#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
#undef CONFIG_CMD_IMI		/* iminfo			*/
#undef CONFIG_CMD_IMLS		/* List all found images	*/

#define CONFIG_SYS_NO_FLASH
#define CONFIG_HARD_I2C			1
#define CONFIG_SYS_I2C_SPEED		100000
#define CONFIG_SYS_I2C_SLAVE		1
#define CONFIG_I2C_MULTI_BUS		1
#define CONFIG_DRIVER_OMAP34XX_I2C	1
#define CONFIG_VIDEO_OMAP3	/* DSS Support			*/

/*
 * TWL4030
 */
#define CONFIG_TWL4030_POWER		1
#define CONFIG_TWL4030_LED		1

/*
 * Board NAND Info.
 */
#define CONFIG_SYS_NAND_QUIET_TEST	1
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
							/* to access nand */
#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
							/* to access nand at */
							/* CS0 */
#define GPMC_NAND_ECC_LP_x16_LAYOUT	1

#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
							/* devices */
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV		"nand0"
/* start of jffs2 partition */
#define CONFIG_JFFS2_PART_OFFSET	0x680000
#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* size of jffs2 */
							/* partition */

/* Environment information */
#define CONFIG_BOOTDELAY		3

#define CONFIG_EXTRA_ENV_SETTINGS \
	"loadaddr=0x80200000\0" \
	"rdaddr=0x81000000\0" \
	"usbtty=cdc_acm\0" \
	"bootfile=uImage.beagle\0" \
	"console=ttyO2,115200n8\0" \
	"mpurate=auto\0" \
	"buddy=none\0" \
	"optargs=\0" \
	"camera=none\0" \
	"vram=12M\0" \
	"dvimode=640x480MR-16@60\0" \
	"defaultdisplay=dvi\0" \
	"mmcdev=0\0" \
	"mmcroot=/dev/mmcblk0p2 rw\0" \
	"mmcrootfstype=ext3 rootwait\0" \
	"nandroot=ubi0:rootfs ubi.mtd=4\0" \
	"nandrootfstype=ubifs\0" \
	"ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=0x81000000,64M\0" \
	"ramrootfstype=ext2\0" \
	"mmcargs=setenv bootargs console=${console} " \
		"${optargs} " \
		"mpurate=${mpurate} " \
		"buddy=${buddy} "\
		"camera=${camera} "\
		"vram=${vram} " \
		"omapfb.mode=dvi:${dvimode} " \
		"omapdss.def_disp=${defaultdisplay} " \
		"root=${mmcroot} " \
		"rootfstype=${mmcrootfstype}\0" \
	"nandargs=setenv bootargs console=${console} " \
		"${optargs} " \
		"mpurate=${mpurate} " \
		"buddy=${buddy} "\
		"camera=${camera} "\
		"vram=${vram} " \
		"omapfb.mode=dvi:${dvimode} " \
		"omapdss.def_disp=${defaultdisplay} " \
		"root=${nandroot} " \
		"rootfstype=${nandrootfstype}\0" \
	"bootenv=uEnv.txt\0" \
	"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
	"importbootenv=echo Importing environment from mmc ...; " \
		"env import -t $loadaddr $filesize\0" \
	"ramargs=setenv bootargs console=${console} " \
		"${optargs} " \
		"mpurate=${mpurate} " \
		"buddy=${buddy} "\
		"vram=${vram} " \
		"omapfb.mode=dvi:${dvimode} " \
		"omapdss.def_disp=${defaultdisplay} " \
		"root=${ramroot} " \
		"rootfstype=${ramrootfstype}\0" \
	"loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
	"loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
	"loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} /boot/uImage\0" \
	"mmcboot=echo Booting from mmc ...; " \
		"run mmcargs; " \
		"bootm ${loadaddr}\0" \
	"nandboot=echo Booting from nand ...; " \
		"run nandargs; " \
		"nand read ${loadaddr} 280000 400000; " \
		"bootm ${loadaddr}\0" \
	"ramboot=echo Booting from ramdisk ...; " \
		"run ramargs; " \
		"bootm ${loadaddr}\0" \
	"userbutton=if gpio input 173; then run userbutton_xm; " \
		"else run userbutton_nonxm; fi;\0" \
	"userbutton_xm=gpio input 4;\0" \
	"userbutton_nonxm=gpio input 7;\0"
/* "run userbutton" will return 1 (false) if pressed and 0 (true) if not */
#define CONFIG_BOOTCOMMAND \
	"mmc dev ${mmcdev}; if mmc rescan; then " \
		"if run userbutton; then " \
			"setenv bootenv uEnv.txt;" \
		"else " \
			"setenv bootenv user.txt;" \
		"fi;" \
		"echo SD/MMC found on device ${mmcdev};" \
		"if run loadbootenv; then " \
			"echo Loaded environment from ${bootenv};" \
			"run importbootenv;" \
		"fi;" \
		"if test -n $uenvcmd; then " \
			"echo Running uenvcmd ...;" \
			"run uenvcmd;" \
		"fi;" \
		"if run loaduimage; then " \
			"run mmcboot;" \
		"fi;" \
	"fi;" \
	"run nandboot;" \

#define CONFIG_AUTO_COMPLETE		1
/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
#define CONFIG_SYS_PROMPT		"OMAP3 beagleboard.org # "
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		32	/* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)

#define CONFIG_SYS_ALT_MEMTEST		1
#define CONFIG_SYS_MEMTEST_START	(0x82000000)		/* memtest */
								/* defaults */
#define CONFIG_SYS_MEMTEST_END		(0x87FFFFFF) 		/* 128MB */
#define CONFIG_SYS_MEMTEST_SCRATCH	(0x81000000)	/* dummy address */

#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)	/* default */
							/* load address */

/*
 * OMAP3 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
#define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ			1000

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */

/* **** PISMO SUPPORT *** */

/* Configure the PISMO */
#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M

#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */

#if defined(CONFIG_CMD_NAND)
#define CONFIG_SYS_FLASH_BASE		PISMO1_NAND_BASE
#endif

/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP

#define CONFIG_ENV_IS_IN_NAND		1
#define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */

#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE	0x800
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - \
					 GENERATED_GBL_DATA_SIZE)

#define CONFIG_OMAP3_SPI

#define CONFIG_SYS_CACHELINE_SIZE	64

/* Defines for SPL */
#define CONFIG_SPL
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_TEXT_BASE		0x40200800
#define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK

#define CONFIG_SPL_BSS_START_ADDR	0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */

#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"

#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_OMAP3_ID_NAND
#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"

/* NAND boot config */
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_PAGE_SIZE	2048
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
						10, 11, 12, 13}
#define CONFIG_SYS_NAND_ECCSIZE		512
#define CONFIG_SYS_NAND_ECCBYTES	3
#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000

/*
 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
 * 64 bytes before this address should be set aside for u-boot.img's
 * header. That is 0x800FFFC0--0x80100000 should not be used for any
 * other needs.
 */
#define CONFIG_SYS_TEXT_BASE		0x80100000
#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000

#endif /* __CONFIG_H */
Commit	Line	Data
f904cdbb DB	1	/*
	2	* (C) Copyright 2006-2008
	3	* Texas Instruments.
	4	* Richard Woodruff <r-woodruff2@ti.com>
	5	* Syed Mohammed Khasim <x0khasim@ti.com>
	6	*
	7	* Configuration settings for the TI OMAP3530 Beagle board.
	8	*
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
f904cdbb DB	30
	31	/*
	32	* High Level Configuration Options
	33	*/
f904cdbb DB	34	#define CONFIG_OMAP 1 /* in a TI OMAP core */
f904cdbb DB	35	#define CONFIG_OMAP34XX 1 /* which is a 34XX */
f904cdbb	36	#define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */
308252ad	37	#define CONFIG_OMAP_GPIO
f904cdbb	38
cae377b5 VH	39	#define CONFIG_SDRC /* The chip has SDRC controller */
cae377b5 VH	40
f904cdbb DB	41	#include <asm/arch/cpu.h> /* get chip and board defs */
	42	#include <asm/arch/omap3.h>
	43
6a6b62e3 SP	44	/*
	45	* Display CPU and Board information
	46	*/
	47	#define CONFIG_DISPLAY_CPUINFO 1
	48	#define CONFIG_DISPLAY_BOARDINFO 1
	49
f904cdbb DB	50	/* Clock Defines */
	51	#define V_OSCK 26000000 /* Clock output from T2 */
	52	#define V_SCLK (V_OSCK >> 1)
	53
f904cdbb DB	54	#define CONFIG_MISC_INIT_R
f904cdbb DB	55
03a2075a TR	56	#define CONFIG_OF_LIBFDT
03a2075a TR	57	#define CONFIG_CMD_BOOTZ
b485556b	58
f904cdbb DB	59	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	60	#define CONFIG_SETUP_MEMORY_TAGS 1
	61	#define CONFIG_INITRD_TAG 1
	62	#define CONFIG_REVISION_TAG 1
	63
	64	/*
	65	* Size of malloc() pool
	66	*/
9c44ddcc	67	#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
f904cdbb	68	/* Sector */
9c44ddcc	69	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
f904cdbb DB	70
	71	/*
	72	* Hardware drivers
	73	*/
	74
	75	/*
	76	* NS16550 Configuration
	77	*/
	78	#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
	79
	80	#define CONFIG_SYS_NS16550
	81	#define CONFIG_SYS_NS16550_SERIAL
	82	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	83	#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
	84
	85	/*
	86	* select serial console configuration
	87	*/
	88	#define CONFIG_CONS_INDEX 3
	89	#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
	90	#define CONFIG_SERIAL3 3 /* UART3 on Beagle Rev 2 */
	91
	92	/* allow to overwrite serial and ethaddr */
	93	#define CONFIG_ENV_OVERWRITE
	94	#define CONFIG_BAUDRATE 115200
	95	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
	96	115200}
0cd31144	97	#define CONFIG_GENERIC_MMC 1
f904cdbb	98	#define CONFIG_MMC 1
0cd31144	99	#define CONFIG_OMAP_HSMMC 1
f904cdbb DB	100	#define CONFIG_DOS_PARTITION 1
f904cdbb DB	101
70d8c944 JK	102	/* Status LED */
	103	#define CONFIG_STATUS_LED 1
	104	#define CONFIG_BOARD_SPECIFIC_LED 1
	105	#define STATUS_LED_BIT 0x01
	106	#define STATUS_LED_STATE STATUS_LED_ON
	107	#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
	108	#define STATUS_LED_BIT1 0x02
	109	#define STATUS_LED_STATE1 STATUS_LED_ON
	110	#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
	111	#define STATUS_LED_BOOT STATUS_LED_BIT
	112	#define STATUS_LED_GREEN STATUS_LED_BIT1
	113
f74fc4ae JK	114	/* Enable Multi Bus support for I2C */
	115	#define CONFIG_I2C_MULTI_BUS 1
	116
	117	/* Probe all devices */
8c4e0ca6	118	#define CONFIG_SYS_I2C_NOPROBES {{0x0, 0x0}}
f74fc4ae	119
25374bfb	120	/* USB */
c2af345e IY	121	#define CONFIG_MUSB_GADGET
	122	#define CONFIG_USB_MUSB_OMAP2PLUS
	123	#define CONFIG_MUSB_PIO_ONLY
	124	#define CONFIG_USB_GADGET_DUALSPEED
25374bfb	125	#define CONFIG_TWL4030_USB 1
c642b151 IY	126	#define CONFIG_USB_ETHER
c642b151 IY	127	#define CONFIG_USB_ETHER_RNDIS
25374bfb	128
d90859a6 AH	129	/* USB EHCI */
	130	#define CONFIG_CMD_USB
	131	#define CONFIG_USB_EHCI
928c4bdf	132
29321c05	133	#define CONFIG_USB_EHCI_OMAP
29321c05 IY	134	#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 147
29321c05 IY	135
928c4bdf G	136	#define CONFIG_USB_ULPI
	137	#define CONFIG_USB_ULPI_VIEWPORT_OMAP
	138
d90859a6	139	#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
2162439a KK	140	#define CONFIG_USB_HOST_ETHER
2162439a KK	141	#define CONFIG_USB_ETHER_SMSC95XX
54b62d59	142	#define CONFIG_USB_ETHER_ASIX
2162439a	143
d90859a6	144
f904cdbb DB	145	/* commands to include */
	146	#include <config_cmd_default.h>
	147
776bebb7 TR	148	#define CONFIG_CMD_ASKENV
776bebb7 TR	149
95c6f6d3	150	#define CONFIG_CMD_CACHE
f904cdbb DB	151	#define CONFIG_CMD_EXT2 /* EXT2 Support */
	152	#define CONFIG_CMD_FAT /* FAT support */
	153	#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
917cfc70	154	#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
942556a9	155	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
917cfc70 NM	156	#define MTDIDS_DEFAULT "nand0=nand"
	157	#define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
	158	"1920k(u-boot),128k(u-boot-env),"\
	159	"4m(kernel),-(fs)"
f904cdbb DB	160
	161	#define CONFIG_CMD_I2C /* I2C serial bus support */
	162	#define CONFIG_CMD_MMC /* MMC support */
d90859a6	163	#define CONFIG_USB_STORAGE /* USB storage support */
f904cdbb	164	#define CONFIG_CMD_NAND /* NAND support */
70d8c944	165	#define CONFIG_CMD_LED /* LED support */
2162439a KK	166	#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
	167	#define CONFIG_CMD_NFS /* NFS support */
	168	#define CONFIG_CMD_PING
54b62d59	169	#define CONFIG_CMD_DHCP
933d3701	170	#define CONFIG_CMD_SETEXPR /* Evaluate expressions */
aae58b95	171	#define CONFIG_CMD_GPIO /* Enable gpio command */
f904cdbb DB	172
	173	#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
	174	#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
	175	#undef CONFIG_CMD_IMI /* iminfo */
	176	#undef CONFIG_CMD_IMLS /* List all found images */
f904cdbb DB	177
f904cdbb DB	178	#define CONFIG_SYS_NO_FLASH
0297ec7e	179	#define CONFIG_HARD_I2C 1
f904cdbb DB	180	#define CONFIG_SYS_I2C_SPEED 100000
f904cdbb DB	181	#define CONFIG_SYS_I2C_SLAVE 1
ca5f80ae	182	#define CONFIG_I2C_MULTI_BUS 1
f904cdbb	183	#define CONFIG_DRIVER_OMAP34XX_I2C 1
25a4d017	184	#define CONFIG_VIDEO_OMAP3 /* DSS Support */
f904cdbb	185
2c155130 TR	186	/*
	187	* TWL4030
	188	*/
	189	#define CONFIG_TWL4030_POWER 1
	190	#define CONFIG_TWL4030_LED 1
	191
f904cdbb DB	192	/*
	193	* Board NAND Info.
	194	*/
60c23173	195	#define CONFIG_SYS_NAND_QUIET_TEST 1
f904cdbb DB	196	#define CONFIG_NAND_OMAP_GPMC
	197	#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
	198	/* to access nand */
	199	#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
	200	/* to access nand at */
	201	/* CS0 */
	202	#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
	203
	204	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
	205	/* devices */
f904cdbb DB	206	#define CONFIG_JFFS2_NAND
	207	/* nand device jffs2 lives on */
	208	#define CONFIG_JFFS2_DEV "nand0"
	209	/* start of jffs2 partition */
	210	#define CONFIG_JFFS2_PART_OFFSET 0x680000
	211	#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
	212	/* partition */
	213
	214	/* Environment information */
1dd07fe8	215	#define CONFIG_BOOTDELAY 3
f904cdbb DB	216
f904cdbb DB	217	#define CONFIG_EXTRA_ENV_SETTINGS \
f4b36ea9 JK	218	"loadaddr=0x80200000\0" \
f4b36ea9 JK	219	"rdaddr=0x81000000\0" \
25374bfb	220	"usbtty=cdc_acm\0" \
e6829308	221	"bootfile=uImage.beagle\0" \
27b8c8f2	222	"console=ttyO2,115200n8\0" \
f6e593bb	223	"mpurate=auto\0" \
847b83d0	224	"buddy=none\0" \
c522eac4 JK	225	"optargs=\0" \
c522eac4 JK	226	"camera=none\0" \
13d2cb98	227	"vram=12M\0" \
f4b36ea9	228	"dvimode=640x480MR-16@60\0" \
13d2cb98	229	"defaultdisplay=dvi\0" \
0cd31144	230	"mmcdev=0\0" \
13d2cb98 SS	231	"mmcroot=/dev/mmcblk0p2 rw\0" \
13d2cb98 SS	232	"mmcrootfstype=ext3 rootwait\0" \
3c6e50d7 SS	233	"nandroot=ubi0:rootfs ubi.mtd=4\0" \
3c6e50d7 SS	234	"nandrootfstype=ubifs\0" \
f4b36ea9 JK	235	"ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=0x81000000,64M\0" \
f4b36ea9 JK	236	"ramrootfstype=ext2\0" \
f904cdbb	237	"mmcargs=setenv bootargs console=${console} " \
c522eac4	238	"${optargs} " \
5af32460	239	"mpurate=${mpurate} " \
b1660314	240	"buddy=${buddy} "\
c522eac4	241	"camera=${camera} "\
13d2cb98 SS	242	"vram=${vram} " \
13d2cb98 SS	243	"omapfb.mode=dvi:${dvimode} " \
13d2cb98 SS	244	"omapdss.def_disp=${defaultdisplay} " \
	245	"root=${mmcroot} " \
	246	"rootfstype=${mmcrootfstype}\0" \
f904cdbb	247	"nandargs=setenv bootargs console=${console} " \
c522eac4	248	"${optargs} " \
5af32460	249	"mpurate=${mpurate} " \
b1660314	250	"buddy=${buddy} "\
c522eac4	251	"camera=${camera} "\
13d2cb98 SS	252	"vram=${vram} " \
13d2cb98 SS	253	"omapfb.mode=dvi:${dvimode} " \
13d2cb98 SS	254	"omapdss.def_disp=${defaultdisplay} " \
	255	"root=${nandroot} " \
	256	"rootfstype=${nandrootfstype}\0" \
f835ea71 JK	257	"bootenv=uEnv.txt\0" \
f835ea71 JK	258	"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
cf073e49 AH	259	"importbootenv=echo Importing environment from mmc ...; " \
cf073e49 AH	260	"env import -t $loadaddr $filesize\0" \
f4b36ea9 JK	261	"ramargs=setenv bootargs console=${console} " \
	262	"${optargs} " \
	263	"mpurate=${mpurate} " \
	264	"buddy=${buddy} "\
	265	"vram=${vram} " \
	266	"omapfb.mode=dvi:${dvimode} " \
	267	"omapdss.def_disp=${defaultdisplay} " \
	268	"root=${ramroot} " \
	269	"rootfstype=${ramrootfstype}\0" \
	270	"loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
e5549f0f KK	271	"loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
e5549f0f KK	272	"loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} /boot/uImage\0" \
f904cdbb DB	273	"mmcboot=echo Booting from mmc ...; " \
	274	"run mmcargs; " \
	275	"bootm ${loadaddr}\0" \
	276	"nandboot=echo Booting from nand ...; " \
	277	"run nandargs; " \
	278	"nand read ${loadaddr} 280000 400000; " \
	279	"bootm ${loadaddr}\0" \
f4b36ea9 JK	280	"ramboot=echo Booting from ramdisk ...; " \
	281	"run ramargs; " \
	282	"bootm ${loadaddr}\0" \
aae58b95 JF	283	"userbutton=if gpio input 173; then run userbutton_xm; " \
	284	"else run userbutton_nonxm; fi;\0" \
	285	"userbutton_xm=gpio input 4;\0" \
	286	"userbutton_nonxm=gpio input 7;\0"
d7aff44a	287	/* "run userbutton" will return 1 (false) if pressed and 0 (true) if not */
f904cdbb	288	#define CONFIG_BOOTCOMMAND \
66968110	289	"mmc dev ${mmcdev}; if mmc rescan; then " \
aae58b95 JF	290	"if run userbutton; then " \
	291	"setenv bootenv uEnv.txt;" \
	292	"else " \
f835ea71 JK	293	"setenv bootenv user.txt;" \
f835ea71 JK	294	"fi;" \
cf073e49 AH	295	"echo SD/MMC found on device ${mmcdev};" \
cf073e49 AH	296	"if run loadbootenv; then " \
f835ea71	297	"echo Loaded environment from ${bootenv};" \
cf073e49 AH	298	"run importbootenv;" \
	299	"fi;" \
	300	"if test -n $uenvcmd; then " \
	301	"echo Running uenvcmd ...;" \
	302	"run uenvcmd;" \
	303	"fi;" \
	304	"if run loaduimage; then " \
	305	"run mmcboot;" \
	306	"fi;" \
	307	"fi;" \
	308	"run nandboot;" \
f904cdbb DB	309
	310	#define CONFIG_AUTO_COMPLETE 1
	311	/*
	312	* Miscellaneous configurable options
	313	*/
f904cdbb DB	314	#define CONFIG_SYS_LONGHELP /* undef to save memory */
f904cdbb DB	315	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
1270ec13	316	#define CONFIG_SYS_PROMPT "OMAP3 beagleboard.org # "
f62b1257	317	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
f904cdbb DB	318	/* Print Buffer Size */
	319	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	320	sizeof(CONFIG_SYS_PROMPT) + 16)
933d3701	321	#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
f904cdbb DB	322	/* Boot Argument Buffer Size */
	323	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	324
780a97f8 JK	325	#define CONFIG_SYS_ALT_MEMTEST 1
	326	#define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */
	327	/* defaults */
	328	#define CONFIG_SYS_MEMTEST_END (0x87FFFFFF) /* 128MB */
	329	#define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */
f904cdbb	330
f904cdbb DB	331	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
	332	/* load address */
	333
	334	/*
d3a513c2 MP	335	* OMAP3 has 12 GP timers, they can be driven by the system clock
	336	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
	337	* This rate is divided by a local divisor.
f904cdbb	338	*/
f904cdbb	339	#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
d3a513c2 MP	340	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
d3a513c2 MP	341	#define CONFIG_SYS_HZ 1000
f904cdbb	342
f904cdbb DB	343	/*-----------------------------------------------------------------------
	344	* Physical Memory Map
	345	*/
	346	#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
	347	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
f904cdbb DB	348	#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
f904cdbb DB	349
f904cdbb DB	350	/*-----------------------------------------------------------------------
	351	* FLASH and environment organization
	352	*/
	353
	354	/* ** PISMO SUPPORT * */
	355
	356	/* Configure the PISMO */
	357	#define PISMO1_NAND_SIZE GPMC_SIZE_128M
	358	#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
	359
9c44ddcc	360	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
f904cdbb	361
6cbec7b3 LC	362	#if defined(CONFIG_CMD_NAND)
	363	#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
	364	#endif
f904cdbb DB	365
	366	/* Monitor at start of flash */
	367	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	368	#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
	369
	370	#define CONFIG_ENV_IS_IN_NAND 1
	371	#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
	372	#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
	373
6cbec7b3 LC	374	#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
6cbec7b3 LC	375	#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
f904cdbb DB	376	#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
f904cdbb DB	377
561142af	378	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
31bfcf1c SS	379	#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
	380	#define CONFIG_SYS_INIT_RAM_SIZE 0x800
	381	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	382	CONFIG_SYS_INIT_RAM_SIZE - \
	383	GENERATED_GBL_DATA_SIZE)
561142af	384
53736baa DB	385	#define CONFIG_OMAP3_SPI
53736baa DB	386
8e40852f A	387	#define CONFIG_SYS_CACHELINE_SIZE 64
8e40852f A	388
75c57a35 TR	389	/* Defines for SPL */
75c57a35 TR	390	#define CONFIG_SPL
47f7bcae	391	#define CONFIG_SPL_FRAMEWORK
75c57a35 TR	392	#define CONFIG_SPL_NAND_SIMPLE
75c57a35 TR	393	#define CONFIG_SPL_TEXT_BASE 0x40200800
e0820ccc	394	#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
75c57a35 TR	395	#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
	396
	397	#define CONFIG_SPL_BSS_START_ADDR 0x80000000
	398	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
	399
	400	#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
	401	#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
	402	#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
	403	#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
	404
49175c49	405	#define CONFIG_SPL_BOARD_INIT
75c57a35 TR	406	#define CONFIG_SPL_LIBCOMMON_SUPPORT
	407	#define CONFIG_SPL_LIBDISK_SUPPORT
	408	#define CONFIG_SPL_I2C_SUPPORT
	409	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	410	#define CONFIG_SPL_MMC_SUPPORT
	411	#define CONFIG_SPL_FAT_SUPPORT
	412	#define CONFIG_SPL_SERIAL_SUPPORT
	413	#define CONFIG_SPL_NAND_SUPPORT
6f2f01b9 SW	414	#define CONFIG_SPL_NAND_BASE
	415	#define CONFIG_SPL_NAND_DRIVERS
	416	#define CONFIG_SPL_NAND_ECC
16e41c85	417	#define CONFIG_SPL_GPIO_SUPPORT
75c57a35 TR	418	#define CONFIG_SPL_POWER_SUPPORT
	419	#define CONFIG_SPL_OMAP3_ID_NAND
	420	#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
	421
	422	/* NAND boot config */
	423	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	424	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	425	#define CONFIG_SYS_NAND_PAGE_SIZE 2048
	426	#define CONFIG_SYS_NAND_OOBSIZE 64
	427	#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
	428	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
	429	#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
	430	10, 11, 12, 13}
	431	#define CONFIG_SYS_NAND_ECCSIZE 512
	432	#define CONFIG_SYS_NAND_ECCBYTES 3
75c57a35 TR	433	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
	434	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
	435
	436	/*
	437	* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
	438	* 64 bytes before this address should be set aside for u-boot.img's
	439	* header. That is 0x800FFFC0--0x80100000 should not be used for any
	440	* other needs.
	441	*/
	442	#define CONFIG_SYS_TEXT_BASE 0x80100000
	443	#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
	444	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
	445
f904cdbb	446	#endif /* __CONFIG_H */