[people/ms/u-boot.git] / include / configs / omap3_beagle.h

/*
 * (C) Copyright 2006-2008
 * Texas Instruments.
 * Richard Woodruff <r-woodruff2@ti.com>
 * Syed Mohammed Khasim <x0khasim@ti.com>
 *
 * Configuration settings for the TI OMAP3530 Beagle board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_ARMV7		1	/* This is an ARM V7 CPU core */
#define CONFIG_OMAP		1	/* in a TI OMAP core */
#define CONFIG_OMAP34XX		1	/* which is a 34XX */
#define CONFIG_OMAP3430		1	/* which is in a 3430 */
#define CONFIG_OMAP3_BEAGLE	1	/* working with BEAGLE */

#define CONFIG_SDRC	/* The chip has SDRC controller */

#include <asm/arch/cpu.h>		/* get chip and board defs */
#include <asm/arch/omap3.h>

/*
 * Display CPU and Board information
 */
#define CONFIG_DISPLAY_CPUINFO		1
#define CONFIG_DISPLAY_BOARDINFO	1

/* Clock Defines */
#define V_OSCK			26000000	/* Clock output from T2 */
#define V_SCLK			(V_OSCK >> 1)

#undef CONFIG_USE_IRQ				/* no support for IRQs */
#define CONFIG_MISC_INIT_R

#define CONFIG_OF_LIBFDT		1
/*
 * The early kernel mapping on ARM currently only maps from the base of DRAM
 * to the end of the kernel image.  The kernel is loaded at DRAM base + 0x8000.
 * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000,
 * so that leaves DRAM base to DRAM base + 0x4000 available.
 */
#define CONFIG_SYS_BOOTMAPSZ	        0x4000

#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_INITRD_TAG		1
#define CONFIG_REVISION_TAG		1

/*
 * Size of malloc() pool
 */
#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
						/* Sector */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
						/* initial data */

/*
 * Hardware drivers
 */

/*
 * NS16550 Configuration
 */
#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */

#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK

/*
 * select serial console configuration
 */
#define CONFIG_CONS_INDEX		3
#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
#define CONFIG_SERIAL3			3	/* UART3 on Beagle Rev 2 */

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
					115200}
#define CONFIG_GENERIC_MMC		1
#define CONFIG_MMC			1
#define CONFIG_OMAP_HSMMC		1
#define CONFIG_DOS_PARTITION		1

/* DDR - I use Micron DDR */
#define CONFIG_OMAP3_MICRON_DDR		1

/* USB */
#define CONFIG_MUSB_UDC			1
#define CONFIG_USB_OMAP3		1
#define CONFIG_TWL4030_USB		1

/* USB device configuration */
#define CONFIG_USB_DEVICE		1
#define CONFIG_USB_TTY			1
#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1

/* commands to include */
#include <config_cmd_default.h>

#define CONFIG_CMD_CACHE
#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
#define CONFIG_CMD_FAT		/* FAT support			*/
#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
#define CONFIG_CMD_MTDPARTS	/* Enable MTD parts commands */
#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
#define MTDIDS_DEFAULT			"nand0=nand"
#define MTDPARTS_DEFAULT		"mtdparts=nand:512k(x-loader),"\
					"1920k(u-boot),128k(u-boot-env),"\
					"4m(kernel),-(fs)"

#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
#define CONFIG_CMD_MMC		/* MMC support			*/
#define CONFIG_CMD_NAND		/* NAND support			*/

#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
#undef CONFIG_CMD_IMI		/* iminfo			*/
#undef CONFIG_CMD_IMLS		/* List all found images	*/
#undef CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
#undef CONFIG_CMD_NFS		/* NFS support			*/

#define CONFIG_SYS_NO_FLASH
#define CONFIG_HARD_I2C			1
#define CONFIG_SYS_I2C_SPEED		100000
#define CONFIG_SYS_I2C_SLAVE		1
#define CONFIG_SYS_I2C_BUS		0
#define CONFIG_SYS_I2C_BUS_SELECT	1
#define CONFIG_I2C_MULTI_BUS		1
#define CONFIG_DRIVER_OMAP34XX_I2C	1

/*
 * TWL4030
 */
#define CONFIG_TWL4030_POWER		1
#define CONFIG_TWL4030_LED		1

/*
 * Board NAND Info.
 */
#define CONFIG_SYS_NAND_QUIET_TEST	1
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
							/* to access nand */
#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
							/* to access nand at */
							/* CS0 */
#define GPMC_NAND_ECC_LP_x16_LAYOUT	1

#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
							/* devices */
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV		"nand0"
/* start of jffs2 partition */
#define CONFIG_JFFS2_PART_OFFSET	0x680000
#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* size of jffs2 */
							/* partition */

/* Environment information */
#define CONFIG_BOOTDELAY		10

#define CONFIG_EXTRA_ENV_SETTINGS \
	"loadaddr=0x82000000\0" \
	"usbtty=cdc_acm\0" \
	"console=ttyS2,115200n8\0" \
	"mpurate=500\0" \
	"vram=12M\0" \
	"dvimode=1024x768MR-16@60\0" \
	"defaultdisplay=dvi\0" \
	"mmcdev=0\0" \
	"mmcroot=/dev/mmcblk0p2 rw\0" \
	"mmcrootfstype=ext3 rootwait\0" \
	"nandroot=/dev/mtdblock4 rw\0" \
	"nandrootfstype=jffs2\0" \
	"mmcargs=setenv bootargs console=${console} " \
		"mpurate=${mpurate} " \
		"vram=${vram} " \
		"omapfb.mode=dvi:${dvimode} " \
		"omapfb.debug=y " \
		"omapdss.def_disp=${defaultdisplay} " \
		"root=${mmcroot} " \
		"rootfstype=${mmcrootfstype}\0" \
	"nandargs=setenv bootargs console=${console} " \
		"mpurate=${mpurate} " \
		"vram=${vram} " \
		"omapfb.mode=dvi:${dvimode} " \
		"omapfb.debug=y " \
		"omapdss.def_disp=${defaultdisplay} " \
		"root=${nandroot} " \
		"rootfstype=${nandrootfstype}\0" \
	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
	"bootscript=echo Running bootscript from mmc ...; " \
		"source ${loadaddr}\0" \
	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
	"mmcboot=echo Booting from mmc ...; " \
		"run mmcargs; " \
		"bootm ${loadaddr}\0" \
	"nandboot=echo Booting from nand ...; " \
		"run nandargs; " \
		"nand read ${loadaddr} 280000 400000; " \
		"bootm ${loadaddr}\0" \

#define CONFIG_BOOTCOMMAND \
	"if mmc rescan ${mmcdev}; then " \
		"if run loadbootscript; then " \
			"run bootscript; " \
		"else " \
			"if run loaduimage; then " \
				"run mmcboot; " \
			"else run nandboot; " \
			"fi; " \
		"fi; " \
	"else run nandboot; fi"

#define CONFIG_AUTO_COMPLETE		1
/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
#define CONFIG_SYS_PROMPT		"OMAP3 beagleboard.org # "
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)

#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)	/* memtest */
								/* works on */
#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
					0x01F00000) /* 31MB */

#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)	/* default */
							/* load address */

/*
 * OMAP3 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
#define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ			1000

/*-----------------------------------------------------------------------
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ	(4 << 10)	/* IRQ stack 4 KiB */
#define CONFIG_STACKSIZE_FIQ	(4 << 10)	/* FIQ stack 4 KiB */
#endif

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

/* SDRAM Bank Allocation method */
#define SDRC_R_B_C		1

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */

/* **** PISMO SUPPORT *** */

/* Configure the PISMO */
#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M

#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */

#define CONFIG_SYS_FLASH_BASE		boot_flash_base

/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP

#define CONFIG_ENV_IS_IN_NAND		1
#define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */

#define CONFIG_SYS_ENV_SECT_SIZE	boot_flash_sec
#define CONFIG_ENV_OFFSET		boot_flash_off
#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET

#ifndef __ASSEMBLY__
extern unsigned int boot_flash_base;
extern volatile unsigned int boot_flash_env_addr;
extern unsigned int boot_flash_off;
extern unsigned int boot_flash_sec;
extern unsigned int boot_flash_type;
#endif

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE	0x800
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - \
					 GENERATED_GBL_DATA_SIZE)

#define CONFIG_OMAP3_SPI

#endif /* __CONFIG_H */
Commit	Line	Data
f904cdbb DB	1	/*
	2	* (C) Copyright 2006-2008
	3	* Texas Instruments.
	4	* Richard Woodruff <r-woodruff2@ti.com>
	5	* Syed Mohammed Khasim <x0khasim@ti.com>
	6	*
	7	* Configuration settings for the TI OMAP3530 Beagle board.
	8	*
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
f904cdbb DB	30
	31	/*
	32	* High Level Configuration Options
	33	*/
f56348af	34	#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
f904cdbb DB	35	#define CONFIG_OMAP 1 /* in a TI OMAP core */
	36	#define CONFIG_OMAP34XX 1 /* which is a 34XX */
	37	#define CONFIG_OMAP3430 1 /* which is in a 3430 */
	38	#define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */
	39
cae377b5 VH	40	#define CONFIG_SDRC /* The chip has SDRC controller */
cae377b5 VH	41
f904cdbb DB	42	#include <asm/arch/cpu.h> /* get chip and board defs */
	43	#include <asm/arch/omap3.h>
	44
6a6b62e3 SP	45	/*
	46	* Display CPU and Board information
	47	*/
	48	#define CONFIG_DISPLAY_CPUINFO 1
	49	#define CONFIG_DISPLAY_BOARDINFO 1
	50
f904cdbb DB	51	/* Clock Defines */
	52	#define V_OSCK 26000000 /* Clock output from T2 */
	53	#define V_SCLK (V_OSCK >> 1)
	54
	55	#undef CONFIG_USE_IRQ /* no support for IRQs */
	56	#define CONFIG_MISC_INIT_R
	57
b485556b JR	58	#define CONFIG_OF_LIBFDT 1
	59	/*
	60	* The early kernel mapping on ARM currently only maps from the base of DRAM
	61	* to the end of the kernel image. The kernel is loaded at DRAM base + 0x8000.
	62	* The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000,
	63	* so that leaves DRAM base to DRAM base + 0x4000 available.
	64	*/
	65	#define CONFIG_SYS_BOOTMAPSZ 0x4000
	66
f904cdbb DB	67	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	68	#define CONFIG_SETUP_MEMORY_TAGS 1
	69	#define CONFIG_INITRD_TAG 1
	70	#define CONFIG_REVISION_TAG 1
	71
	72	/*
	73	* Size of malloc() pool
	74	*/
9c44ddcc	75	#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
f904cdbb	76	/* Sector */
9c44ddcc	77	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
f904cdbb DB	78	/* initial data */
	79
	80	/*
	81	* Hardware drivers
	82	*/
	83
	84	/*
	85	* NS16550 Configuration
	86	*/
	87	#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
	88
	89	#define CONFIG_SYS_NS16550
	90	#define CONFIG_SYS_NS16550_SERIAL
	91	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	92	#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
	93
	94	/*
	95	* select serial console configuration
	96	*/
	97	#define CONFIG_CONS_INDEX 3
	98	#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
	99	#define CONFIG_SERIAL3 3 /* UART3 on Beagle Rev 2 */
	100
	101	/* allow to overwrite serial and ethaddr */
	102	#define CONFIG_ENV_OVERWRITE
	103	#define CONFIG_BAUDRATE 115200
	104	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
	105	115200}
0cd31144	106	#define CONFIG_GENERIC_MMC 1
f904cdbb	107	#define CONFIG_MMC 1
0cd31144	108	#define CONFIG_OMAP_HSMMC 1
f904cdbb DB	109	#define CONFIG_DOS_PARTITION 1
f904cdbb DB	110
30563a04 NM	111	/* DDR - I use Micron DDR */
	112	#define CONFIG_OMAP3_MICRON_DDR 1
	113
25374bfb TR	114	/* USB */
	115	#define CONFIG_MUSB_UDC 1
	116	#define CONFIG_USB_OMAP3 1
	117	#define CONFIG_TWL4030_USB 1
	118
	119	/* USB device configuration */
	120	#define CONFIG_USB_DEVICE 1
	121	#define CONFIG_USB_TTY 1
	122	#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
25374bfb	123
f904cdbb DB	124	/* commands to include */
	125	#include <config_cmd_default.h>
	126
95c6f6d3	127	#define CONFIG_CMD_CACHE
f904cdbb DB	128	#define CONFIG_CMD_EXT2 /* EXT2 Support */
	129	#define CONFIG_CMD_FAT /* FAT support */
	130	#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
917cfc70	131	#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
942556a9	132	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
917cfc70 NM	133	#define MTDIDS_DEFAULT "nand0=nand"
	134	#define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
	135	"1920k(u-boot),128k(u-boot-env),"\
	136	"4m(kernel),-(fs)"
f904cdbb DB	137
	138	#define CONFIG_CMD_I2C /* I2C serial bus support */
	139	#define CONFIG_CMD_MMC /* MMC support */
	140	#define CONFIG_CMD_NAND /* NAND support */
	141
	142	#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
	143	#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
	144	#undef CONFIG_CMD_IMI /* iminfo */
	145	#undef CONFIG_CMD_IMLS /* List all found images */
	146	#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
	147	#undef CONFIG_CMD_NFS /* NFS support */
	148
	149	#define CONFIG_SYS_NO_FLASH
0297ec7e	150	#define CONFIG_HARD_I2C 1
f904cdbb DB	151	#define CONFIG_SYS_I2C_SPEED 100000
	152	#define CONFIG_SYS_I2C_SLAVE 1
	153	#define CONFIG_SYS_I2C_BUS 0
	154	#define CONFIG_SYS_I2C_BUS_SELECT 1
ca5f80ae	155	#define CONFIG_I2C_MULTI_BUS 1
f904cdbb DB	156	#define CONFIG_DRIVER_OMAP34XX_I2C 1
f904cdbb DB	157
2c155130 TR	158	/*
	159	* TWL4030
	160	*/
	161	#define CONFIG_TWL4030_POWER 1
	162	#define CONFIG_TWL4030_LED 1
	163
f904cdbb DB	164	/*
	165	* Board NAND Info.
	166	*/
60c23173	167	#define CONFIG_SYS_NAND_QUIET_TEST 1
f904cdbb DB	168	#define CONFIG_NAND_OMAP_GPMC
	169	#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
	170	/* to access nand */
	171	#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
	172	/* to access nand at */
	173	/* CS0 */
	174	#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
	175
	176	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
	177	/* devices */
f904cdbb DB	178	#define CONFIG_JFFS2_NAND
	179	/* nand device jffs2 lives on */
	180	#define CONFIG_JFFS2_DEV "nand0"
	181	/* start of jffs2 partition */
	182	#define CONFIG_JFFS2_PART_OFFSET 0x680000
	183	#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
	184	/* partition */
	185
	186	/* Environment information */
	187	#define CONFIG_BOOTDELAY 10
	188
	189	#define CONFIG_EXTRA_ENV_SETTINGS \
	190	"loadaddr=0x82000000\0" \
25374bfb	191	"usbtty=cdc_acm\0" \
f904cdbb	192	"console=ttyS2,115200n8\0" \
5af32460	193	"mpurate=500\0" \
13d2cb98 SS	194	"vram=12M\0" \
	195	"dvimode=1024x768MR-16@60\0" \
	196	"defaultdisplay=dvi\0" \
0cd31144	197	"mmcdev=0\0" \
13d2cb98 SS	198	"mmcroot=/dev/mmcblk0p2 rw\0" \
	199	"mmcrootfstype=ext3 rootwait\0" \
	200	"nandroot=/dev/mtdblock4 rw\0" \
	201	"nandrootfstype=jffs2\0" \
f904cdbb	202	"mmcargs=setenv bootargs console=${console} " \
5af32460	203	"mpurate=${mpurate} " \
13d2cb98 SS	204	"vram=${vram} " \
	205	"omapfb.mode=dvi:${dvimode} " \
	206	"omapfb.debug=y " \
	207	"omapdss.def_disp=${defaultdisplay} " \
	208	"root=${mmcroot} " \
	209	"rootfstype=${mmcrootfstype}\0" \
f904cdbb	210	"nandargs=setenv bootargs console=${console} " \
5af32460	211	"mpurate=${mpurate} " \
13d2cb98 SS	212	"vram=${vram} " \
	213	"omapfb.mode=dvi:${dvimode} " \
	214	"omapfb.debug=y " \
	215	"omapdss.def_disp=${defaultdisplay} " \
	216	"root=${nandroot} " \
	217	"rootfstype=${nandrootfstype}\0" \
0cd31144	218	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
f904cdbb	219	"bootscript=echo Running bootscript from mmc ...; " \
74de7aef	220	"source ${loadaddr}\0" \
0cd31144	221	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
f904cdbb DB	222	"mmcboot=echo Booting from mmc ...; " \
	223	"run mmcargs; " \
	224	"bootm ${loadaddr}\0" \
	225	"nandboot=echo Booting from nand ...; " \
	226	"run nandargs; " \
	227	"nand read ${loadaddr} 280000 400000; " \
	228	"bootm ${loadaddr}\0" \
	229
	230	#define CONFIG_BOOTCOMMAND \
0cd31144	231	"if mmc rescan ${mmcdev}; then " \
f904cdbb DB	232	"if run loadbootscript; then " \
	233	"run bootscript; " \
	234	"else " \
	235	"if run loaduimage; then " \
	236	"run mmcboot; " \
	237	"else run nandboot; " \
	238	"fi; " \
	239	"fi; " \
	240	"else run nandboot; fi"
	241
	242	#define CONFIG_AUTO_COMPLETE 1
	243	/*
	244	* Miscellaneous configurable options
	245	*/
f904cdbb DB	246	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	247	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
	248	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
1270ec13	249	#define CONFIG_SYS_PROMPT "OMAP3 beagleboard.org # "
f904cdbb DB	250	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	251	/* Print Buffer Size */
	252	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	253	sizeof(CONFIG_SYS_PROMPT) + 16)
	254	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	255	/* Boot Argument Buffer Size */
	256	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	257
	258	#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
	259	/* works on */
	260	#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
	261	0x01F00000) /* 31MB */
	262
f904cdbb DB	263	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
	264	/* load address */
	265
	266	/*
d3a513c2 MP	267	* OMAP3 has 12 GP timers, they can be driven by the system clock
	268	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
	269	* This rate is divided by a local divisor.
f904cdbb	270	*/
f904cdbb	271	#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
d3a513c2 MP	272	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
d3a513c2 MP	273	#define CONFIG_SYS_HZ 1000
f904cdbb DB	274
	275	/*-----------------------------------------------------------------------
	276	* Stack sizes
	277	*
	278	* The stack sizes are set up in start.S using the settings below
	279	*/
9c44ddcc	280	#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
f904cdbb	281	#ifdef CONFIG_USE_IRQ
9c44ddcc SP	282	#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
9c44ddcc SP	283	#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
f904cdbb DB	284	#endif
	285
	286	/*-----------------------------------------------------------------------
	287	* Physical Memory Map
	288	*/
	289	#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
	290	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
9c44ddcc	291	#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
f904cdbb DB	292	#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
	293
	294	/* SDRAM Bank Allocation method */
	295	#define SDRC_R_B_C 1
	296
	297	/*-----------------------------------------------------------------------
	298	* FLASH and environment organization
	299	*/
	300
	301	/* ** PISMO SUPPORT * */
	302
	303	/* Configure the PISMO */
	304	#define PISMO1_NAND_SIZE GPMC_SIZE_128M
	305	#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
	306
9c44ddcc	307	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
f904cdbb DB	308
	309	#define CONFIG_SYS_FLASH_BASE boot_flash_base
	310
	311	/* Monitor at start of flash */
	312	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	313	#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
	314
	315	#define CONFIG_ENV_IS_IN_NAND 1
	316	#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
	317	#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
	318
	319	#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
	320	#define CONFIG_ENV_OFFSET boot_flash_off
	321	#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
	322
f904cdbb	323	#ifndef __ASSEMBLY__
f904cdbb DB	324	extern unsigned int boot_flash_base;
	325	extern volatile unsigned int boot_flash_env_addr;
	326	extern unsigned int boot_flash_off;
	327	extern unsigned int boot_flash_sec;
	328	extern unsigned int boot_flash_type;
	329	#endif
	330
561142af	331	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
31bfcf1c SS	332	#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
	333	#define CONFIG_SYS_INIT_RAM_SIZE 0x800
	334	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	335	CONFIG_SYS_INIT_RAM_SIZE - \
	336	GENERATED_GBL_DATA_SIZE)
561142af	337
53736baa DB	338	#define CONFIG_OMAP3_SPI
53736baa DB	339
f904cdbb	340	#endif /* __CONFIG_H */