[people/ms/u-boot.git] / include / configs / omap3_beagle.h

/*
 * (C) Copyright 2006-2008
 * Texas Instruments.
 * Richard Woodruff <r-woodruff2@ti.com>
 * Syed Mohammed Khasim <x0khasim@ti.com>
 *
 * Configuration settings for the TI OMAP3530 Beagle board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_OMAP		1	/* in a TI OMAP core */
#define CONFIG_OMAP34XX		1	/* which is a 34XX */
#define CONFIG_OMAP3430		1	/* which is in a 3430 */
#define CONFIG_OMAP3_BEAGLE	1	/* working with BEAGLE */

#define CONFIG_SDRC	/* The chip has SDRC controller */

#include <asm/arch/cpu.h>		/* get chip and board defs */
#include <asm/arch/omap3.h>

/*
 * Display CPU and Board information
 */
#define CONFIG_DISPLAY_CPUINFO		1
#define CONFIG_DISPLAY_BOARDINFO	1

/* Clock Defines */
#define V_OSCK			26000000	/* Clock output from T2 */
#define V_SCLK			(V_OSCK >> 1)

#undef CONFIG_USE_IRQ				/* no support for IRQs */
#define CONFIG_MISC_INIT_R

#define CONFIG_OF_LIBFDT		1

#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_INITRD_TAG		1
#define CONFIG_REVISION_TAG		1

/*
 * Size of malloc() pool
 */
#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
						/* Sector */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))

/*
 * Hardware drivers
 */

/*
 * NS16550 Configuration
 */
#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */

#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK

/*
 * select serial console configuration
 */
#define CONFIG_CONS_INDEX		3
#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
#define CONFIG_SERIAL3			3	/* UART3 on Beagle Rev 2 */

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
					115200}
#define CONFIG_GENERIC_MMC		1
#define CONFIG_MMC			1
#define CONFIG_OMAP_HSMMC		1
#define CONFIG_DOS_PARTITION		1

/* Status LED */
#define CONFIG_STATUS_LED		1
#define CONFIG_BOARD_SPECIFIC_LED	1
#define STATUS_LED_BIT			0x01
#define STATUS_LED_STATE		STATUS_LED_ON
#define STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 2)
#define STATUS_LED_BIT1			0x02
#define STATUS_LED_STATE1		STATUS_LED_ON
#define STATUS_LED_PERIOD1		(CONFIG_SYS_HZ / 2)
#define STATUS_LED_BOOT			STATUS_LED_BIT
#define STATUS_LED_GREEN		STATUS_LED_BIT1

/* DDR - I use Micron DDR */
#define CONFIG_OMAP3_MICRON_DDR		1

/* USB */
#define CONFIG_MUSB_UDC			1
#define CONFIG_USB_OMAP3		1
#define CONFIG_TWL4030_USB		1

/* USB device configuration */
#define CONFIG_USB_DEVICE		1
#define CONFIG_USB_TTY			1
#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1

/* USB EHCI */
#define CONFIG_CMD_USB
#define CONFIG_USB_EHCI
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3

/* commands to include */
#include <config_cmd_default.h>

#define CONFIG_CMD_CACHE
#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
#define CONFIG_CMD_FAT		/* FAT support			*/
#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
#define CONFIG_CMD_MTDPARTS	/* Enable MTD parts commands */
#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
#define MTDIDS_DEFAULT			"nand0=nand"
#define MTDPARTS_DEFAULT		"mtdparts=nand:512k(x-loader),"\
					"1920k(u-boot),128k(u-boot-env),"\
					"4m(kernel),-(fs)"

#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
#define CONFIG_CMD_MMC		/* MMC support			*/
#define CONFIG_USB_STORAGE	/* USB storage support		*/
#define CONFIG_CMD_NAND		/* NAND support			*/
#define CONFIG_CMD_LED		/* LED support			*/

#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
#undef CONFIG_CMD_IMI		/* iminfo			*/
#undef CONFIG_CMD_IMLS		/* List all found images	*/
#undef CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
#undef CONFIG_CMD_NFS		/* NFS support			*/

#define CONFIG_SYS_NO_FLASH
#define CONFIG_HARD_I2C			1
#define CONFIG_SYS_I2C_SPEED		100000
#define CONFIG_SYS_I2C_SLAVE		1
#define CONFIG_SYS_I2C_BUS		0
#define CONFIG_SYS_I2C_BUS_SELECT	1
#define CONFIG_I2C_MULTI_BUS		1
#define CONFIG_DRIVER_OMAP34XX_I2C	1

/*
 * TWL4030
 */
#define CONFIG_TWL4030_POWER		1
#define CONFIG_TWL4030_LED		1

/*
 * Board NAND Info.
 */
#define CONFIG_SYS_NAND_QUIET_TEST	1
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
							/* to access nand */
#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
							/* to access nand at */
							/* CS0 */
#define GPMC_NAND_ECC_LP_x16_LAYOUT	1

#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
							/* devices */
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV		"nand0"
/* start of jffs2 partition */
#define CONFIG_JFFS2_PART_OFFSET	0x680000
#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* size of jffs2 */
							/* partition */

/* Environment information */
#define CONFIG_BOOTDELAY		2

#define CONFIG_EXTRA_ENV_SETTINGS \
	"loadaddr=0x82000000\0" \
	"usbtty=cdc_acm\0" \
	"usbethaddr=de:ad:be:ef\0" \
	"bootfile=uImage.beagle\0" \
	"console=ttyS2,115200n8\0" \
	"mpurate=auto\0" \
	"buddy=none "\
	"vram=12M\0" \
	"dvimode=1024x768MR-16@60\0" \
	"defaultdisplay=dvi\0" \
	"mmcdev=0\0" \
	"mmcroot=/dev/mmcblk0p2 rw\0" \
	"mmcrootfstype=ext3 rootwait\0" \
	"nandroot=/dev/mtdblock4 rw\0" \
	"nandrootfstype=jffs2\0" \
	"mmcargs=setenv bootargs console=${console} " \
		"mpurate=${mpurate} " \
		"buddy=${buddy} "\
		"vram=${vram} " \
		"omapfb.mode=dvi:${dvimode} " \
		"omapdss.def_disp=${defaultdisplay} " \
		"root=${mmcroot} " \
		"rootfstype=${mmcrootfstype}\0" \
	"nandargs=setenv bootargs console=${console} " \
		"mpurate=${mpurate} " \
		"buddy=${buddy} "\
		"vram=${vram} " \
		"omapfb.mode=dvi:${dvimode} " \
		"omapdss.def_disp=${defaultdisplay} " \
		"root=${nandroot} " \
		"rootfstype=${nandrootfstype}\0" \
	"bootenv=uEnv.txt\0" \
	"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
	"importbootenv=echo Importing environment from mmc ...; " \
		"env import -t $loadaddr $filesize\0" \
	"loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
	"loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} /boot/uImage\0" \
	"mmcboot=echo Booting from mmc ...; " \
		"run mmcargs; " \
		"bootm ${loadaddr}\0" \
	"nandboot=echo Booting from nand ...; " \
		"run nandargs; " \
		"nand read ${loadaddr} 280000 400000; " \
		"bootm ${loadaddr}\0" \

#define CONFIG_BOOTCOMMAND \
	"if mmc rescan ${mmcdev}; then " \
		"if userbutton; then " \
			"setenv bootenv user.txt;" \
		"fi;" \
		"echo SD/MMC found on device ${mmcdev};" \
		"if run loadbootenv; then " \
			"echo Loaded environment from ${bootenv};" \
			"run importbootenv;" \
		"fi;" \
		"if test -n $uenvcmd; then " \
			"echo Running uenvcmd ...;" \
			"run uenvcmd;" \
		"fi;" \
		"if run loaduimage; then " \
			"run mmcboot;" \
		"fi;" \
	"fi;" \
	"run nandboot;" \

#define CONFIG_AUTO_COMPLETE		1
/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
#define CONFIG_SYS_PROMPT		"OMAP3 beagleboard.org # "
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)

#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)	/* memtest */
								/* works on */
#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
					0x01F00000) /* 31MB */

#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)	/* default */
							/* load address */

/*
 * OMAP3 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
#define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ			1000

/*-----------------------------------------------------------------------
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ	(4 << 10)	/* IRQ stack 4 KiB */
#define CONFIG_STACKSIZE_FIQ	(4 << 10)	/* FIQ stack 4 KiB */
#endif

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

/* SDRAM Bank Allocation method */
#define SDRC_R_B_C		1

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */

/* **** PISMO SUPPORT *** */

/* Configure the PISMO */
#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M

#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */

#if defined(CONFIG_CMD_NAND)
#define CONFIG_SYS_FLASH_BASE		PISMO1_NAND_BASE
#endif

/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP

#define CONFIG_ENV_IS_IN_NAND		1
#define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */

#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE	0x800
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - \
					 GENERATED_GBL_DATA_SIZE)

#define CONFIG_OMAP3_SPI

#endif /* __CONFIG_H */
Commit	Line	Data
f904cdbb DB	1	/*
	2	* (C) Copyright 2006-2008
	3	* Texas Instruments.
	4	* Richard Woodruff <r-woodruff2@ti.com>
	5	* Syed Mohammed Khasim <x0khasim@ti.com>
	6	*
	7	* Configuration settings for the TI OMAP3530 Beagle board.
	8	*
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
f904cdbb DB	30
	31	/*
	32	* High Level Configuration Options
	33	*/
f904cdbb DB	34	#define CONFIG_OMAP 1 /* in a TI OMAP core */
	35	#define CONFIG_OMAP34XX 1 /* which is a 34XX */
	36	#define CONFIG_OMAP3430 1 /* which is in a 3430 */
	37	#define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */
	38
cae377b5 VH	39	#define CONFIG_SDRC /* The chip has SDRC controller */
cae377b5 VH	40
f904cdbb DB	41	#include <asm/arch/cpu.h> /* get chip and board defs */
	42	#include <asm/arch/omap3.h>
	43
6a6b62e3 SP	44	/*
	45	* Display CPU and Board information
	46	*/
	47	#define CONFIG_DISPLAY_CPUINFO 1
	48	#define CONFIG_DISPLAY_BOARDINFO 1
	49
f904cdbb DB	50	/* Clock Defines */
	51	#define V_OSCK 26000000 /* Clock output from T2 */
	52	#define V_SCLK (V_OSCK >> 1)
	53
	54	#undef CONFIG_USE_IRQ /* no support for IRQs */
	55	#define CONFIG_MISC_INIT_R
	56
b485556b	57	#define CONFIG_OF_LIBFDT 1
b485556b	58
f904cdbb DB	59	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	60	#define CONFIG_SETUP_MEMORY_TAGS 1
	61	#define CONFIG_INITRD_TAG 1
	62	#define CONFIG_REVISION_TAG 1
	63
	64	/*
	65	* Size of malloc() pool
	66	*/
9c44ddcc	67	#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
f904cdbb	68	/* Sector */
9c44ddcc	69	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
f904cdbb DB	70
	71	/*
	72	* Hardware drivers
	73	*/
	74
	75	/*
	76	* NS16550 Configuration
	77	*/
	78	#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
	79
	80	#define CONFIG_SYS_NS16550
	81	#define CONFIG_SYS_NS16550_SERIAL
	82	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	83	#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
	84
	85	/*
	86	* select serial console configuration
	87	*/
	88	#define CONFIG_CONS_INDEX 3
	89	#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
	90	#define CONFIG_SERIAL3 3 /* UART3 on Beagle Rev 2 */
	91
	92	/* allow to overwrite serial and ethaddr */
	93	#define CONFIG_ENV_OVERWRITE
	94	#define CONFIG_BAUDRATE 115200
	95	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
	96	115200}
0cd31144	97	#define CONFIG_GENERIC_MMC 1
f904cdbb	98	#define CONFIG_MMC 1
0cd31144	99	#define CONFIG_OMAP_HSMMC 1
f904cdbb DB	100	#define CONFIG_DOS_PARTITION 1
f904cdbb DB	101
70d8c944 JK	102	/* Status LED */
	103	#define CONFIG_STATUS_LED 1
	104	#define CONFIG_BOARD_SPECIFIC_LED 1
	105	#define STATUS_LED_BIT 0x01
	106	#define STATUS_LED_STATE STATUS_LED_ON
	107	#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
	108	#define STATUS_LED_BIT1 0x02
	109	#define STATUS_LED_STATE1 STATUS_LED_ON
	110	#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
	111	#define STATUS_LED_BOOT STATUS_LED_BIT
	112	#define STATUS_LED_GREEN STATUS_LED_BIT1
	113
30563a04 NM	114	/* DDR - I use Micron DDR */
	115	#define CONFIG_OMAP3_MICRON_DDR 1
	116
25374bfb TR	117	/* USB */
	118	#define CONFIG_MUSB_UDC 1
	119	#define CONFIG_USB_OMAP3 1
	120	#define CONFIG_TWL4030_USB 1
	121
	122	/* USB device configuration */
	123	#define CONFIG_USB_DEVICE 1
	124	#define CONFIG_USB_TTY 1
	125	#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
25374bfb	126
d90859a6 AH	127	/* USB EHCI */
	128	#define CONFIG_CMD_USB
	129	#define CONFIG_USB_EHCI
	130	#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
	131
f904cdbb DB	132	/* commands to include */
	133	#include <config_cmd_default.h>
	134
95c6f6d3	135	#define CONFIG_CMD_CACHE
f904cdbb DB	136	#define CONFIG_CMD_EXT2 /* EXT2 Support */
	137	#define CONFIG_CMD_FAT /* FAT support */
	138	#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
917cfc70	139	#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
942556a9	140	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
917cfc70 NM	141	#define MTDIDS_DEFAULT "nand0=nand"
	142	#define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
	143	"1920k(u-boot),128k(u-boot-env),"\
	144	"4m(kernel),-(fs)"
f904cdbb DB	145
	146	#define CONFIG_CMD_I2C /* I2C serial bus support */
	147	#define CONFIG_CMD_MMC /* MMC support */
d90859a6	148	#define CONFIG_USB_STORAGE /* USB storage support */
f904cdbb	149	#define CONFIG_CMD_NAND /* NAND support */
70d8c944	150	#define CONFIG_CMD_LED /* LED support */
f904cdbb DB	151
	152	#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
	153	#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
	154	#undef CONFIG_CMD_IMI /* iminfo */
	155	#undef CONFIG_CMD_IMLS /* List all found images */
	156	#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
	157	#undef CONFIG_CMD_NFS /* NFS support */
	158
	159	#define CONFIG_SYS_NO_FLASH
0297ec7e	160	#define CONFIG_HARD_I2C 1
f904cdbb DB	161	#define CONFIG_SYS_I2C_SPEED 100000
	162	#define CONFIG_SYS_I2C_SLAVE 1
	163	#define CONFIG_SYS_I2C_BUS 0
	164	#define CONFIG_SYS_I2C_BUS_SELECT 1
ca5f80ae	165	#define CONFIG_I2C_MULTI_BUS 1
f904cdbb DB	166	#define CONFIG_DRIVER_OMAP34XX_I2C 1
f904cdbb DB	167
2c155130 TR	168	/*
	169	* TWL4030
	170	*/
	171	#define CONFIG_TWL4030_POWER 1
	172	#define CONFIG_TWL4030_LED 1
	173
f904cdbb DB	174	/*
	175	* Board NAND Info.
	176	*/
60c23173	177	#define CONFIG_SYS_NAND_QUIET_TEST 1
f904cdbb DB	178	#define CONFIG_NAND_OMAP_GPMC
	179	#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
	180	/* to access nand */
	181	#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
	182	/* to access nand at */
	183	/* CS0 */
	184	#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
	185
	186	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
	187	/* devices */
f904cdbb DB	188	#define CONFIG_JFFS2_NAND
	189	/* nand device jffs2 lives on */
	190	#define CONFIG_JFFS2_DEV "nand0"
	191	/* start of jffs2 partition */
	192	#define CONFIG_JFFS2_PART_OFFSET 0x680000
	193	#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
	194	/* partition */
	195
	196	/* Environment information */
4c37e8de	197	#define CONFIG_BOOTDELAY 2
f904cdbb DB	198
	199	#define CONFIG_EXTRA_ENV_SETTINGS \
	200	"loadaddr=0x82000000\0" \
25374bfb	201	"usbtty=cdc_acm\0" \
ec556ffc	202	"usbethaddr=de:ad:be:ef\0" \
e6829308	203	"bootfile=uImage.beagle\0" \
f904cdbb	204	"console=ttyS2,115200n8\0" \
f6e593bb	205	"mpurate=auto\0" \
b1660314	206	"buddy=none "\
13d2cb98 SS	207	"vram=12M\0" \
	208	"dvimode=1024x768MR-16@60\0" \
	209	"defaultdisplay=dvi\0" \
0cd31144	210	"mmcdev=0\0" \
13d2cb98 SS	211	"mmcroot=/dev/mmcblk0p2 rw\0" \
	212	"mmcrootfstype=ext3 rootwait\0" \
	213	"nandroot=/dev/mtdblock4 rw\0" \
	214	"nandrootfstype=jffs2\0" \
f904cdbb	215	"mmcargs=setenv bootargs console=${console} " \
5af32460	216	"mpurate=${mpurate} " \
b1660314	217	"buddy=${buddy} "\
13d2cb98 SS	218	"vram=${vram} " \
13d2cb98 SS	219	"omapfb.mode=dvi:${dvimode} " \
13d2cb98 SS	220	"omapdss.def_disp=${defaultdisplay} " \
	221	"root=${mmcroot} " \
	222	"rootfstype=${mmcrootfstype}\0" \
f904cdbb	223	"nandargs=setenv bootargs console=${console} " \
5af32460	224	"mpurate=${mpurate} " \
b1660314	225	"buddy=${buddy} "\
13d2cb98 SS	226	"vram=${vram} " \
13d2cb98 SS	227	"omapfb.mode=dvi:${dvimode} " \
13d2cb98 SS	228	"omapdss.def_disp=${defaultdisplay} " \
	229	"root=${nandroot} " \
	230	"rootfstype=${nandrootfstype}\0" \
f835ea71 JK	231	"bootenv=uEnv.txt\0" \
f835ea71 JK	232	"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
cf073e49 AH	233	"importbootenv=echo Importing environment from mmc ...; " \
cf073e49 AH	234	"env import -t $loadaddr $filesize\0" \
e5549f0f KK	235	"loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
e5549f0f KK	236	"loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} /boot/uImage\0" \
f904cdbb DB	237	"mmcboot=echo Booting from mmc ...; " \
	238	"run mmcargs; " \
	239	"bootm ${loadaddr}\0" \
	240	"nandboot=echo Booting from nand ...; " \
	241	"run nandargs; " \
	242	"nand read ${loadaddr} 280000 400000; " \
	243	"bootm ${loadaddr}\0" \
	244
	245	#define CONFIG_BOOTCOMMAND \
0cd31144	246	"if mmc rescan ${mmcdev}; then " \
f835ea71 JK	247	"if userbutton; then " \
	248	"setenv bootenv user.txt;" \
	249	"fi;" \
cf073e49 AH	250	"echo SD/MMC found on device ${mmcdev};" \
cf073e49 AH	251	"if run loadbootenv; then " \
f835ea71	252	"echo Loaded environment from ${bootenv};" \
cf073e49 AH	253	"run importbootenv;" \
	254	"fi;" \
	255	"if test -n $uenvcmd; then " \
	256	"echo Running uenvcmd ...;" \
	257	"run uenvcmd;" \
	258	"fi;" \
	259	"if run loaduimage; then " \
	260	"run mmcboot;" \
	261	"fi;" \
	262	"fi;" \
	263	"run nandboot;" \
f904cdbb DB	264
	265	#define CONFIG_AUTO_COMPLETE 1
	266	/*
	267	* Miscellaneous configurable options
	268	*/
f904cdbb DB	269	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	270	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
	271	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
1270ec13	272	#define CONFIG_SYS_PROMPT "OMAP3 beagleboard.org # "
f62b1257	273	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
f904cdbb DB	274	/* Print Buffer Size */
	275	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	276	sizeof(CONFIG_SYS_PROMPT) + 16)
	277	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	278	/* Boot Argument Buffer Size */
	279	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	280
	281	#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
	282	/* works on */
	283	#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
	284	0x01F00000) /* 31MB */
	285
f904cdbb DB	286	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
	287	/* load address */
	288
	289	/*
d3a513c2 MP	290	* OMAP3 has 12 GP timers, they can be driven by the system clock
	291	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
	292	* This rate is divided by a local divisor.
f904cdbb	293	*/
f904cdbb	294	#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
d3a513c2 MP	295	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
d3a513c2 MP	296	#define CONFIG_SYS_HZ 1000
f904cdbb DB	297
	298	/*-----------------------------------------------------------------------
	299	* Stack sizes
	300	*
	301	* The stack sizes are set up in start.S using the settings below
	302	*/
9c44ddcc	303	#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
f904cdbb	304	#ifdef CONFIG_USE_IRQ
9c44ddcc SP	305	#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
9c44ddcc SP	306	#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
f904cdbb DB	307	#endif
	308
	309	/*-----------------------------------------------------------------------
	310	* Physical Memory Map
	311	*/
	312	#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
	313	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
9c44ddcc	314	#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
f904cdbb DB	315	#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
	316
	317	/* SDRAM Bank Allocation method */
	318	#define SDRC_R_B_C 1
	319
	320	/*-----------------------------------------------------------------------
	321	* FLASH and environment organization
	322	*/
	323
	324	/* ** PISMO SUPPORT * */
	325
	326	/* Configure the PISMO */
	327	#define PISMO1_NAND_SIZE GPMC_SIZE_128M
	328	#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
	329
9c44ddcc	330	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
f904cdbb	331
6cbec7b3 LC	332	#if defined(CONFIG_CMD_NAND)
	333	#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
	334	#endif
f904cdbb DB	335
	336	/* Monitor at start of flash */
	337	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	338	#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
	339
	340	#define CONFIG_ENV_IS_IN_NAND 1
	341	#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
	342	#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
	343
6cbec7b3 LC	344	#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
6cbec7b3 LC	345	#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
f904cdbb DB	346	#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
f904cdbb DB	347
561142af	348	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
31bfcf1c SS	349	#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
	350	#define CONFIG_SYS_INIT_RAM_SIZE 0x800
	351	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	352	CONFIG_SYS_INIT_RAM_SIZE - \
	353	GENERATED_GBL_DATA_SIZE)
561142af	354
53736baa DB	355	#define CONFIG_OMAP3_SPI
53736baa DB	356
f904cdbb	357	#endif /* __CONFIG_H */