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d275c40c AA |
1 | /* |
2 | * Configuration settings for the QUIPOS Cairo board. | |
3 | * | |
4 | * Copyright (C) DENX GmbH | |
5 | * | |
6 | * Author : | |
7 | * Albert ARIBAUD <albert.aribaud@3adev.fr> | |
8 | * | |
9 | * Derived from EVM code by | |
10 | * Manikandan Pillai <mani.pillai@ti.com> | |
11 | * Itself derived from Beagle Board and 3430 SDP code by | |
12 | * Richard Woodruff <r-woodruff2@ti.com> | |
13 | * Syed Mohammed Khasim <khasim@ti.com> | |
14 | * | |
15 | * Also derived from include/configs/omap3_beagle.h | |
16 | * | |
17 | * SPDX-License-Identifier: GPL-2.0+ | |
18 | */ | |
19 | ||
20 | #ifndef __OMAP3_CAIRO_CONFIG_H | |
21 | #define __OMAP3_CAIRO_CONFIG_H | |
22 | ||
23 | #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ | |
24 | ||
25 | /* | |
26 | * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM | |
27 | * 64 bytes before this address should be set aside for u-boot.img's | |
28 | * header. That is 0x800FFFC0--0x80100000 should not be used for any | |
29 | * other needs. We use this rather than the inherited defines from | |
30 | * ti_armv7_common.h for backwards compatibility. | |
31 | */ | |
32 | #define CONFIG_SYS_TEXT_BASE 0x80100000 | |
33 | #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE | |
34 | #define CONFIG_SPL_BSS_START_ADDR 0x80000000 | |
35 | #define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */ | |
36 | #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 | |
37 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 | |
38 | ||
d275c40c AA |
39 | #include <configs/ti_omap3_common.h> |
40 | ||
d275c40c AA |
41 | #define CONFIG_MISC_INIT_R |
42 | ||
43 | #define CONFIG_REVISION_TAG 1 | |
44 | #define CONFIG_ENV_OVERWRITE | |
45 | ||
46 | /* Enable Multi Bus support for I2C */ | |
47 | #define CONFIG_I2C_MULTI_BUS 1 | |
48 | ||
49 | /* Probe all devices */ | |
50 | #define CONFIG_SYS_I2C_NOPROBES { {0x0, 0x0} } | |
51 | ||
d275c40c AA |
52 | /* |
53 | * TWL4030 | |
54 | */ | |
55 | #define CONFIG_TWL4030_LED 1 | |
56 | ||
57 | /* | |
58 | * Board NAND Info. | |
59 | */ | |
d275c40c AA |
60 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ |
61 | /* devices */ | |
d275c40c AA |
62 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
63 | "machid=ffffffff\0" \ | |
64 | "fdt_high=0x87000000\0" \ | |
65 | "baudrate=115200\0" \ | |
d275c40c AA |
66 | "fec_addr=00:50:C2:7E:90:F0\0" \ |
67 | "netmask=255.255.255.0\0" \ | |
68 | "ipaddr=192.168.2.9\0" \ | |
69 | "gateway=192.168.2.1\0" \ | |
70 | "serverip=192.168.2.10\0" \ | |
71 | "nfshost=192.168.2.10\0" \ | |
72 | "stdin=serial\0" \ | |
73 | "stdout=serial\0" \ | |
74 | "stderr=serial\0" \ | |
75 | "bootargs_mmc_ramdisk=mem=128M " \ | |
76 | "console=ttyO1,115200n8 " \ | |
77 | "root=/dev/ram0 rw " \ | |
78 | "initrd=0x81600000,16M " \ | |
79 | "mpurate=600 ramdisk_size=16384 omapfb.rotate=1 " \ | |
80 | "omapfb.rotate_type=1 omap_vout.vid1_static_vrfb_alloc=y\0" \ | |
81 | "mmcboot=mmc init; " \ | |
82 | "fatload mmc 0 0x80000000 uImage; " \ | |
83 | "fatload mmc 0 0x81600000 ramdisk.gz; " \ | |
84 | "setenv bootargs ${bootargs_mmc_ramdisk}; " \ | |
85 | "bootm 0x80000000\0" \ | |
86 | "bootargs_nfs=mem=99M console=ttyO0,115200n8 noinitrd rw ip=dhcp " \ | |
87 | "root=/dev/nfs " \ | |
88 | "nfsroot=192.168.2.10:/home/spiid/workdir/Quipos/rootfs,nolock " \ | |
89 | "mpurate=600 omapfb.rotate=1 omapfb.rotate_type=1 " \ | |
90 | "omap_vout.vid1_static_vrfb_alloc=y\0" \ | |
91 | "boot_nfs=run get_kernel; setenv bootargs ${bootargs_nfs}; " \ | |
92 | "bootm 0x80000000\0" \ | |
93 | "bootargs_nand=mem=128M console=ttyO1,115200n8 noinitrd " \ | |
94 | "root=/dev/mtdblock4 rw rootfstype=jffs2 mpurate=600 " \ | |
95 | "omap_vout.vid1_static_vrfb_alloc=y omapfb.rotate=1 " \ | |
96 | "omapfb.rotate_type=1\0" \ | |
97 | "boot_nand=nand read.i 0x80000000 280000 300000; setenv " \ | |
98 | "bootargs ${bootargs_nand}; bootm 0x80000000\0" \ | |
99 | "ledorange=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \ | |
100 | "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \ | |
101 | "i2c mw 60 09 10 1; i2c mw 60 06 10 1\0" \ | |
102 | "ledgreen=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \ | |
103 | "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; i2c " \ | |
104 | "mw 60 09 00 1; i2c mw 60 06 10 1\0" \ | |
105 | "ledoff=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \ | |
106 | "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \ | |
107 | "i2c mw 60 09 00 1; i2c mw 60 06 0 1\0" \ | |
108 | "ledred=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \ | |
109 | "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \ | |
110 | "i2c mw 60 09 10 1; i2c mw 60 06 0 1\0" \ | |
111 | "flash_xloader=mw.b 0x81600000 0xff 0x20000; " \ | |
112 | "nand erase 0 20000; " \ | |
113 | "fatload mmc 0 0x81600000 MLO; " \ | |
114 | "nandecc hw; " \ | |
115 | "nand write.i 0x81600000 0 20000;\0" \ | |
116 | "flash_uboot=mw.b 0x81600000 0xff 0x40000; " \ | |
117 | "nand erase 80000 40000; " \ | |
118 | "fatload mmc 0 0x81600000 u-boot.bin; " \ | |
119 | "nandecc sw; " \ | |
120 | "nand write.i 0x81600000 80000 40000;\0" \ | |
121 | "flash_kernel=mw.b 0x81600000 0xff 0x300000; " \ | |
122 | "nand erase 280000 300000; " \ | |
123 | "fatload mmc 0 0x81600000 uImage; " \ | |
124 | "nandecc sw; " \ | |
125 | "nand write.i 0x81600000 280000 300000;\0" \ | |
126 | "flash_rootfs=fatload mmc 0 0x81600000 rootfs.jffs2; " \ | |
127 | "nandecc sw; " \ | |
128 | "nand write.jffs2 0x680000 0xFF ${filesize}; " \ | |
129 | "nand erase 680000 ${filesize}; " \ | |
130 | "nand write.jffs2 81600000 680000 ${filesize};\0" \ | |
131 | "flash_scrub=nand scrub; " \ | |
132 | "run flash_xloader; " \ | |
133 | "run flash_uboot; " \ | |
134 | "run flash_kernel; " \ | |
135 | "run flash_rootfs;\0" \ | |
136 | "flash_all=run ledred; " \ | |
137 | "nand erase.chip; " \ | |
138 | "run ledorange; " \ | |
139 | "run flash_xloader; " \ | |
140 | "run flash_uboot; " \ | |
141 | "run flash_kernel; " \ | |
142 | "run flash_rootfs; " \ | |
143 | "run ledgreen; " \ | |
144 | "run boot_nand; \0" \ | |
145 | ||
146 | #define CONFIG_BOOTCOMMAND \ | |
147 | "if fatload mmc 0 0x81600000 MLO; then run flash_all; " \ | |
148 | "else run boot_nand; fi" | |
149 | ||
150 | /* | |
151 | * OMAP3 has 12 GP timers, they can be driven by the system clock | |
152 | * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). | |
153 | * This rate is divided by a local divisor. | |
154 | */ | |
155 | #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ | |
156 | ||
157 | /*----------------------------------------------------------------------- | |
158 | * FLASH and environment organization | |
159 | */ | |
160 | ||
161 | /* **** PISMO SUPPORT *** */ | |
162 | #if defined(CONFIG_CMD_NAND) | |
163 | #define CONFIG_SYS_FLASH_BASE NAND_BASE | |
164 | #endif | |
165 | ||
166 | /* Monitor at start of flash */ | |
167 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
168 | #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP | |
169 | ||
d275c40c AA |
170 | #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ |
171 | #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ | |
d275c40c AA |
172 | |
173 | #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ | |
7672d9d5 AF |
174 | #define CONFIG_ENV_OFFSET 0x260000 |
175 | #define CONFIG_ENV_ADDR 0x260000 | |
d275c40c | 176 | |
d275c40c | 177 | /* Defines for SPL */ |
d275c40c AA |
178 | |
179 | /* NAND boot config */ | |
180 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE | |
181 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 | |
182 | #define CONFIG_SYS_NAND_PAGE_SIZE 2048 | |
183 | #define CONFIG_SYS_NAND_OOBSIZE 64 | |
184 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) | |
185 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 | |
186 | #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ | |
187 | 10, 11, 12, 13} | |
188 | #define CONFIG_SYS_NAND_ECCSIZE 512 | |
189 | #define CONFIG_SYS_NAND_ECCBYTES 3 | |
190 | #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW | |
191 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 | |
192 | /* NAND: SPL falcon mode configs */ | |
193 | #ifdef CONFIG_SPL_OS_BOOT | |
d275c40c | 194 | #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 |
d275c40c AA |
195 | #endif |
196 | ||
197 | /* env defaults */ | |
198 | #define CONFIG_BOOTFILE "uImage" | |
199 | ||
200 | /* Override OMAP3 common serial console configuration from UART3 | |
201 | * to UART2. | |
202 | * | |
203 | * Attention: for UART2, special MUX settings (MUX_DEFAULT(), MCBSP3) | |
204 | * are needed and peripheral clocks for UART2 must be enabled in | |
205 | * function per_clocks_enable(). | |
206 | */ | |
207 | #undef CONFIG_CONS_INDEX | |
208 | #define CONFIG_CONS_INDEX 2 | |
209 | #ifdef CONFIG_SPL_BUILD | |
210 | #undef CONFIG_SYS_NS16550_COM3 | |
211 | #define CONFIG_SYS_NS16550_COM2 OMAP34XX_UART2 | |
212 | #undef CONFIG_SERIAL3 | |
213 | #define CONFIG_SERIAL2 | |
214 | #endif | |
215 | ||
cd7b6344 TR |
216 | /* Provide the MACH_TYPE value the vendor kernel requires */ |
217 | #define CONFIG_MACH_TYPE 3063 | |
d275c40c AA |
218 | |
219 | /*----------------------------------------------------------------------- | |
220 | * FLASH and environment organization | |
221 | */ | |
222 | ||
223 | /* **** PISMO SUPPORT *** */ | |
224 | ||
225 | #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ | |
226 | /* on one chip */ | |
227 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ | |
228 | ||
229 | /*----------------------------------------------------------------------- | |
230 | * CFI FLASH driver setup | |
231 | */ | |
232 | /* timeout values are in ticks */ | |
233 | #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) | |
234 | #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) | |
235 | ||
236 | /* Flash banks JFFS2 should use */ | |
237 | #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ | |
238 | CONFIG_SYS_MAX_NAND_DEVICE) | |
239 | #define CONFIG_SYS_JFFS2_MEM_NAND | |
240 | /* use flash_info[2] */ | |
241 | #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS | |
242 | #define CONFIG_SYS_JFFS2_NUM_BANKS 1 | |
243 | ||
244 | #endif /* __OMAP3_CAIRO_CONFIG_H */ |