projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| ad9bc8e5 | 1 | /* |
| 741de266 SP |
2 | * Configuration settings for the TI OMAP3 EVM board. |
| 3 | * | |
| 4 | * Copyright (C) 2006-2011 Texas Instruments Incorporated - http://www.ti.com/ | |
| 5 | * | |
| ad9bc8e5 DB |
6 | * Author : |
| 7 | * Manikandan Pillai <mani.pillai@ti.com> | |
| 8 | * Derived from Beagle Board and 3430 SDP code by | |
| 9 | * Richard Woodruff <r-woodruff2@ti.com> | |
| 10 | * Syed Mohammed Khasim <khasim@ti.com> | |
| 11 | * | |
| 12 | * Manikandan Pillai <mani.pillai@ti.com> | |
| 13 | * | |
| 3765b3e7 | 14 | * SPDX-License-Identifier: GPL-2.0+ |
| ad9bc8e5 DB |
15 | */ |
| 16 | ||
| 741de266 SP |
17 | #ifndef __OMAP3EVM_CONFIG_H |
| 18 | #define __OMAP3EVM_CONFIG_H | |
| 19 | ||
| 20 | #include <asm/arch/cpu.h> | |
| 987ec585 | 21 | #include <asm/arch/omap.h> |
| 741de266 | 22 | |
| 741de266 | 23 | /* ---------------------------------------------------------------------------- |
| a187559e | 24 | * Supported U-Boot commands |
| 741de266 SP |
25 | * ---------------------------------------------------------------------------- |
| 26 | */ | |
| 1ee6d31f | 27 | |
| 3970884c | 28 | #define CONFIG_CMD_JFFS2 |
| 741de266 | 29 | |
| 3970884c | 30 | #define CONFIG_CMD_NAND |
| 741de266 | 31 | |
| 741de266 | 32 | /* ---------------------------------------------------------------------------- |
| a187559e | 33 | * Supported U-Boot features |
| 741de266 SP |
34 | * ---------------------------------------------------------------------------- |
| 35 | */ | |
| 36 | #define CONFIG_SYS_LONGHELP | |
| 741de266 | 37 | |
| 741de266 SP |
38 | /* Allow to overwrite serial and ethaddr */ |
| 39 | #define CONFIG_ENV_OVERWRITE | |
| 40 | ||
| 41 | /* Add auto-completion support */ | |
| 42 | #define CONFIG_AUTO_COMPLETE | |
| 43 | ||
| 44 | /* ---------------------------------------------------------------------------- | |
| 45 | * Supported hardware | |
| 46 | * ---------------------------------------------------------------------------- | |
| 47 | */ | |
| 48 | ||
| 673283f3 | 49 | /* SPL */ |
| e2ccdf89 | 50 | #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 |
| 205b4f33 | 51 | #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" |
| 673283f3 TR |
52 | |
| 53 | /* Partition tables */ | |
| 741de266 SP |
54 | |
| 55 | /* USB | |
| 56 | * | |
| 95de1e2f PK |
57 | * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard |
| 58 | * Enable CONFIG_USB_MUSB_UDD for Device functionalities. | |
| 741de266 SP |
59 | */ |
| 60 | #define CONFIG_USB_OMAP3 | |
| 95de1e2f PK |
61 | #define CONFIG_USB_MUSB_HCD |
| 62 | /* #define CONFIG_USB_MUSB_UDC */ | |
| 741de266 | 63 | |
| 673283f3 TR |
64 | /* NAND SPL */ |
| 65 | #define CONFIG_SPL_NAND_SIMPLE | |
| 6f2f01b9 SW |
66 | #define CONFIG_SPL_NAND_BASE |
| 67 | #define CONFIG_SPL_NAND_DRIVERS | |
| 68 | #define CONFIG_SPL_NAND_ECC | |
| 673283f3 TR |
69 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE |
| 70 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 | |
| 71 | #define CONFIG_SYS_NAND_PAGE_SIZE 2048 | |
| 72 | #define CONFIG_SYS_NAND_OOBSIZE 64 | |
| 73 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) | |
| 74 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 | |
| 75 | #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ | |
| 76 | 10, 11, 12, 13} | |
| 77 | #define CONFIG_SYS_NAND_ECCSIZE 512 | |
| 78 | #define CONFIG_SYS_NAND_ECCBYTES 3 | |
| 3f719069 | 79 | #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW |
| 673283f3 TR |
80 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE |
| 81 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 | |
| 82 | ||
| 584550d7 TR |
83 | /* |
| 84 | * High level configuration options | |
| 85 | */ | |
| 86 | #define CONFIG_OMAP /* This is TI OMAP core */ | |
| 87 | #define CONFIG_OMAP_GPIO | |
| 584550d7 TR |
88 | |
| 89 | #define CONFIG_SDRC /* The chip has SDRC controller */ | |
| 90 | ||
| 91 | #define CONFIG_OMAP3_EVM /* This is a OMAP3 EVM */ | |
| 92 | #define CONFIG_TWL4030_POWER /* with TWL4030 PMIC */ | |
| 93 | ||
| 94 | /* | |
| 95 | * Clock related definitions | |
| 96 | */ | |
| 97 | #define V_OSCK 26000000 /* Clock output from T2 */ | |
| 98 | #define V_SCLK (V_OSCK >> 1) | |
| 99 | ||
| 100 | /* | |
| 101 | * OMAP3 has 12 GP timers, they can be driven by the system clock | |
| 102 | * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). | |
| 103 | * This rate is divided by a local divisor. | |
| 104 | */ | |
| 105 | #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 | |
| 106 | #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ | |
| 107 | ||
| 108 | /* Size of environment - 128KB */ | |
| 109 | #define CONFIG_ENV_SIZE (128 << 10) | |
| 110 | ||
| 111 | /* Size of malloc pool */ | |
| 112 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) | |
| 113 | ||
| 114 | /* | |
| 115 | * Physical Memory Map | |
| 116 | * Note 1: CS1 may or may not be populated | |
| 117 | * Note 2: SDRAM size is expected to be at least 32MB | |
| 118 | */ | |
| 119 | #define CONFIG_NR_DRAM_BANKS 2 | |
| 120 | #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 | |
| 121 | #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 | |
| 122 | ||
| 123 | /* Limits for memtest */ | |
| 124 | #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) | |
| 125 | #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ | |
| 126 | 0x01F00000) /* 31MB */ | |
| 127 | ||
| 128 | /* Default load address */ | |
| 129 | #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) | |
| 130 | ||
| 741de266 | 131 | /* ----------------------------------------------------------------------------- |
| 584550d7 | 132 | * Hardware drivers |
| ee8e2254 | 133 | * ----------------------------------------------------------------------------- |
| ad9bc8e5 | 134 | */ |
| 584550d7 TR |
135 | |
| 136 | /* | |
| 137 | * NS16550 Configuration | |
| 138 | */ | |
| 139 | #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ | |
| 140 | ||
| 141 | #define CONFIG_SYS_NS16550_SERIAL | |
| 142 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) | |
| 143 | #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK | |
| 144 | ||
| 145 | /* | |
| 146 | * select serial console configuration | |
| 147 | */ | |
| 148 | #define CONFIG_CONS_INDEX 1 | |
| 149 | #define CONFIG_SERIAL1 1 /* UART1 on OMAP3 EVM */ | |
| 150 | #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 | |
| 584550d7 TR |
151 | #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ |
| 152 | 115200} | |
| 153 | ||
| 154 | /* | |
| 155 | * I2C | |
| 156 | */ | |
| 157 | #define CONFIG_SYS_I2C | |
| 158 | #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 | |
| 159 | #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 | |
| 160 | #define CONFIG_SYS_I2C_OMAP34XX | |
| 161 | ||
| 162 | /* | |
| 163 | * PISMO support | |
| 164 | */ | |
| 165 | /* Monitor at start of flash - Reserve 2 sectors */ | |
| 166 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
| 167 | ||
| 168 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) | |
| 169 | ||
| 170 | /* Start location & size of environment */ | |
| 171 | #define ONENAND_ENV_OFFSET 0x260000 | |
| 172 | #define SMNAND_ENV_OFFSET 0x260000 | |
| 173 | ||
| 174 | #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ | |
| 175 | ||
| 176 | /* | |
| 177 | * NAND | |
| 178 | */ | |
| 179 | /* Physical address to access NAND */ | |
| 180 | #define CONFIG_SYS_NAND_ADDR NAND_BASE | |
| 181 | ||
| 182 | /* Physical address to access NAND at CS0 */ | |
| 183 | #define CONFIG_SYS_NAND_BASE NAND_BASE | |
| 184 | ||
| 185 | /* Max number of NAND devices */ | |
| 186 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
| 187 | #define CONFIG_SYS_NAND_BUSWIDTH_16BIT | |
| 188 | /* Timeout values (in ticks) */ | |
| 189 | #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) | |
| 190 | #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) | |
| 191 | ||
| 192 | /* Flash banks JFFS2 should use */ | |
| 193 | #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ | |
| 194 | CONFIG_SYS_MAX_NAND_DEVICE) | |
| 195 | ||
| 196 | #define CONFIG_SYS_JFFS2_MEM_NAND | |
| 197 | #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS | |
| 198 | #define CONFIG_SYS_JFFS2_NUM_BANKS 1 | |
| 199 | ||
| 200 | #define CONFIG_JFFS2_NAND | |
| 201 | /* nand device jffs2 lives on */ | |
| 202 | #define CONFIG_JFFS2_DEV "nand0" | |
| 203 | /* Start of jffs2 partition */ | |
| 204 | #define CONFIG_JFFS2_PART_OFFSET 0x680000 | |
| 205 | /* Size of jffs2 partition */ | |
| 206 | #define CONFIG_JFFS2_PART_SIZE 0xf980000 | |
| 207 | ||
| 208 | /* | |
| 209 | * USB | |
| 210 | */ | |
| 211 | #ifdef CONFIG_USB_OMAP3 | |
| 212 | ||
| 213 | #ifdef CONFIG_USB_MUSB_HCD | |
| 214 | ||
| 584550d7 TR |
215 | #ifdef CONFIG_USB_KEYBOARD |
| 216 | #define CONFIG_SYS_USB_EVENT_POLL | |
| 217 | #define CONFIG_PREBOOT "usb start" | |
| 218 | #endif /* CONFIG_USB_KEYBOARD */ | |
| 219 | ||
| 220 | #endif /* CONFIG_USB_MUSB_HCD */ | |
| 221 | ||
| 222 | #ifdef CONFIG_USB_MUSB_UDC | |
| 223 | /* USB device configuration */ | |
| 224 | #define CONFIG_USB_DEVICE | |
| 225 | #define CONFIG_USB_TTY | |
| 584550d7 TR |
226 | |
| 227 | /* Change these to suit your needs */ | |
| 228 | #define CONFIG_USBD_VENDORID 0x0451 | |
| 229 | #define CONFIG_USBD_PRODUCTID 0x5678 | |
| 230 | #define CONFIG_USBD_MANUFACTURER "Texas Instruments" | |
| 231 | #define CONFIG_USBD_PRODUCT_NAME "EVM" | |
| 232 | #endif /* CONFIG_USB_MUSB_UDC */ | |
| 233 | ||
| 234 | #endif /* CONFIG_USB_OMAP3 */ | |
| 235 | ||
| 236 | /* ---------------------------------------------------------------------------- | |
| 237 | * U-Boot features | |
| 238 | * ---------------------------------------------------------------------------- | |
| 239 | */ | |
| 240 | #define CONFIG_SYS_MAXARGS 16 /* max args for a command */ | |
| 241 | ||
| 242 | #define CONFIG_MISC_INIT_R | |
| 243 | ||
| 244 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ | |
| 245 | #define CONFIG_SETUP_MEMORY_TAGS | |
| 246 | #define CONFIG_INITRD_TAG | |
| 247 | #define CONFIG_REVISION_TAG | |
| 248 | ||
| 249 | /* Size of Console IO buffer */ | |
| 250 | #define CONFIG_SYS_CBSIZE 512 | |
| 251 | ||
| 252 | /* Size of print buffer */ | |
| 253 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
| 254 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
| 255 | ||
| 256 | /* Size of bootarg buffer */ | |
| 257 | #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) | |
| 258 | ||
| 259 | #define CONFIG_BOOTFILE "uImage" | |
| 260 | ||
| 261 | /* | |
| 262 | * NAND / OneNAND | |
| 263 | */ | |
| 264 | #if defined(CONFIG_CMD_NAND) | |
| 265 | #define CONFIG_SYS_FLASH_BASE NAND_BASE | |
| 266 | ||
| 267 | #define CONFIG_NAND_OMAP_GPMC | |
| 268 | #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET | |
| 269 | #elif defined(CONFIG_CMD_ONENAND) | |
| 270 | #define CONFIG_SYS_FLASH_BASE ONENAND_MAP | |
| 271 | #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP | |
| 272 | #endif | |
| 273 | ||
| 274 | #if !defined(CONFIG_ENV_IS_NOWHERE) | |
| 275 | #if defined(CONFIG_CMD_NAND) | |
| 276 | #define CONFIG_ENV_IS_IN_NAND | |
| 277 | #elif defined(CONFIG_CMD_ONENAND) | |
| 278 | #define CONFIG_ENV_IS_IN_ONENAND | |
| 279 | #define CONFIG_ENV_OFFSET ONENAND_ENV_OFFSET | |
| 280 | #endif | |
| 281 | #endif /* CONFIG_ENV_IS_NOWHERE */ | |
| 282 | ||
| 283 | #define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET | |
| 284 | ||
| 285 | #if defined(CONFIG_CMD_NET) | |
| 286 | ||
| 287 | /* Ethernet (SMSC9115 from SMSC9118 family) */ | |
| 288 | #define CONFIG_SMC911X | |
| 289 | #define CONFIG_SMC911X_32_BIT | |
| 290 | #define CONFIG_SMC911X_BASE 0x2C000000 | |
| 291 | ||
| 292 | /* BOOTP fields */ | |
| 293 | #define CONFIG_BOOTP_SUBNETMASK 0x00000001 | |
| 294 | #define CONFIG_BOOTP_GATEWAY 0x00000002 | |
| 295 | #define CONFIG_BOOTP_HOSTNAME 0x00000004 | |
| 296 | #define CONFIG_BOOTP_BOOTPATH 0x00000010 | |
| 297 | ||
| 298 | #endif /* CONFIG_CMD_NET */ | |
| 299 | ||
| 300 | /* Support for relocation */ | |
| 301 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | |
| 302 | #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 | |
| 303 | #define CONFIG_SYS_INIT_RAM_SIZE 0x800 | |
| 304 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ | |
| 305 | CONFIG_SYS_INIT_RAM_SIZE - \ | |
| 306 | GENERATED_GBL_DATA_SIZE) | |
| 307 | ||
| 308 | /* ----------------------------------------------------------------------------- | |
| 309 | * Board specific | |
| 310 | * ----------------------------------------------------------------------------- | |
| 311 | */ | |
| 584550d7 TR |
312 | |
| 313 | /* Uncomment to define the board revision statically */ | |
| 314 | /* #define CONFIG_STATIC_BOARD_REV OMAP3EVM_BOARD_GEN_2 */ | |
| 315 | ||
| 584550d7 TR |
316 | /* Defines for SPL */ |
| 317 | #define CONFIG_SPL_FRAMEWORK | |
| 318 | #define CONFIG_SPL_TEXT_BASE 0x40200800 | |
| fa2f81b0 TR |
319 | #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ |
| 320 | CONFIG_SPL_TEXT_BASE) | |
| 584550d7 TR |
321 | |
| 322 | #define CONFIG_SPL_BSS_START_ADDR 0x80000000 | |
| 323 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ | |
| 324 | ||
| 325 | #define CONFIG_SPL_BOARD_INIT | |
| 584550d7 | 326 | #define CONFIG_SPL_OMAP3_ID_NAND |
| 983e3700 | 327 | #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" |
| 584550d7 TR |
328 | |
| 329 | /* | |
| 330 | * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM | |
| 331 | * 64 bytes before this address should be set aside for u-boot.img's | |
| 332 | * header. That is 0x800FFFC0--0x80100000 should not be used for any | |
| 333 | * other needs. | |
| 334 | */ | |
| 335 | #define CONFIG_SYS_TEXT_BASE 0x80100000 | |
| 336 | #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 | |
| 337 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 | |
| ad9bc8e5 | 338 | |
| ee8e2254 SP |
339 | /* ----------------------------------------------------------------------------- |
| 340 | * Default environment | |
| 341 | * ----------------------------------------------------------------------------- | |
| 342 | */ | |
| 136cf92d | 343 | |
| ad9bc8e5 DB |
344 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 345 | "loadaddr=0x82000000\0" \ | |
| 73c8640e | 346 | "usbtty=cdc_acm\0" \ |
| dcc4f38b | 347 | "mmcdev=0\0" \ |
| effeda55 | 348 | "console=ttyO0,115200n8\0" \ |
| ad9bc8e5 DB |
349 | "mmcargs=setenv bootargs console=${console} " \ |
| 350 | "root=/dev/mmcblk0p2 rw " \ | |
| 351 | "rootfstype=ext3 rootwait\0" \ | |
| 352 | "nandargs=setenv bootargs console=${console} " \ | |
| 353 | "root=/dev/mtdblock4 rw " \ | |
| 354 | "rootfstype=jffs2\0" \ | |
| dcc4f38b | 355 | "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ |
| ad9bc8e5 | 356 | "bootscript=echo Running bootscript from mmc ...; " \ |
| 74de7aef | 357 | "source ${loadaddr}\0" \ |
| dcc4f38b | 358 | "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ |
| ad9bc8e5 DB |
359 | "mmcboot=echo Booting from mmc ...; " \ |
| 360 | "run mmcargs; " \ | |
| 361 | "bootm ${loadaddr}\0" \ | |
| 362 | "nandboot=echo Booting from nand ...; " \ | |
| 363 | "run nandargs; " \ | |
| 364 | "onenand read ${loadaddr} 280000 400000; " \ | |
| 365 | "bootm ${loadaddr}\0" \ | |
| 366 | ||
| 367 | #define CONFIG_BOOTCOMMAND \ | |
| 66968110 | 368 | "mmc dev ${mmcdev}; if mmc rescan; then " \ |
| ad9bc8e5 DB |
369 | "if run loadbootscript; then " \ |
| 370 | "run bootscript; " \ | |
| 371 | "else " \ | |
| 372 | "if run loaduimage; then " \ | |
| 373 | "run mmcboot; " \ | |
| 374 | "else run nandboot; " \ | |
| 375 | "fi; " \ | |
| 376 | "fi; " \ | |
| 377 | "else run nandboot; fi" | |
| 378 | ||
| 741de266 | 379 | #endif /* __OMAP3EVM_CONFIG_H */ |