[people/ms/u-boot.git] / include / configs / omap3_evm.h

/*
 * Configuration settings for the TI OMAP3 EVM board.
 *
 * Copyright (C) 2006-2011 Texas Instruments Incorporated - http://www.ti.com/
 *
 * Author :
 *	Manikandan Pillai <mani.pillai@ti.com>
 * Derived from Beagle Board and 3430 SDP code by
 *	Richard Woodruff <r-woodruff2@ti.com>
 *	Syed Mohammed Khasim <khasim@ti.com>
 *
 * Manikandan Pillai <mani.pillai@ti.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __OMAP3EVM_CONFIG_H
#define __OMAP3EVM_CONFIG_H

#include <asm/arch/cpu.h>
#include <asm/arch/omap.h>

/* ----------------------------------------------------------------------------
 * Supported U-Boot commands
 * ----------------------------------------------------------------------------
 */

#define CONFIG_CMD_JFFS2

#define CONFIG_CMD_NAND

/* ----------------------------------------------------------------------------
 * Supported U-Boot features
 * ----------------------------------------------------------------------------
 */
#define CONFIG_SYS_LONGHELP

/* Allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

/* Add auto-completion support */
#define CONFIG_AUTO_COMPLETE

/* ----------------------------------------------------------------------------
 * Supported hardware
 * ----------------------------------------------------------------------------
 */

/* SPL */
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"

/* Partition tables */

/* USB
 *
 * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard
 * Enable CONFIG_USB_MUSB_UDD for Device functionalities.
 */
#define CONFIG_USB_OMAP3
#define CONFIG_USB_MUSB_HCD
/* #define CONFIG_USB_MUSB_UDC */

/* NAND SPL */
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_PAGE_SIZE	2048
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
						10, 11, 12, 13}
#define CONFIG_SYS_NAND_ECCSIZE		512
#define CONFIG_SYS_NAND_ECCBYTES	3
#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
#define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000

/*
 * High level configuration options
 */
#define CONFIG_OMAP			/* This is TI OMAP core */
#define CONFIG_OMAP_GPIO
/* Common ARM Erratas */
#define CONFIG_ARM_ERRATA_454179
#define CONFIG_ARM_ERRATA_430973
#define CONFIG_ARM_ERRATA_621766

#define CONFIG_SDRC			/* The chip has SDRC controller */

#define CONFIG_OMAP3_EVM		/* This is a OMAP3 EVM */
#define CONFIG_TWL4030_POWER		/* with TWL4030 PMIC */

/*
 * Clock related definitions
 */
#define V_OSCK			26000000	/* Clock output from T2 */
#define V_SCLK			(V_OSCK >> 1)

/*
 * OMAP3 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */

/* Size of environment - 128KB */
#define CONFIG_ENV_SIZE			(128 << 10)

/* Size of malloc pool */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))

/*
 * Physical Memory Map
 * Note 1: CS1 may or may not be populated
 * Note 2: SDRAM size is expected to be at least 32MB
 */
#define CONFIG_NR_DRAM_BANKS		2
#define PHYS_SDRAM_1			OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_2			OMAP34XX_SDRC_CS1

/* Limits for memtest */
#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
						0x01F00000) /* 31MB */

/* Default load address */
#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)

/* -----------------------------------------------------------------------------
 * Hardware drivers
 * -----------------------------------------------------------------------------
 */

/*
 * NS16550 Configuration
 */
#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */

#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK

/*
 * select serial console configuration
 */
#define CONFIG_CONS_INDEX		1
#define CONFIG_SERIAL1			1	/* UART1 on OMAP3 EVM */
#define CONFIG_SYS_NS16550_COM1		OMAP34XX_UART1
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
					115200}

/*
 * I2C
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
#define CONFIG_SYS_I2C_OMAP34XX

/*
 * PISMO support
 */
/* Monitor at start of flash - Reserve 2 sectors */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE

#define CONFIG_SYS_MONITOR_LEN		(256 << 10)

/* Start location & size of environment */
#define ONENAND_ENV_OFFSET		0x260000
#define SMNAND_ENV_OFFSET		0x260000

#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */

/*
 * NAND
 */
/* Physical address to access NAND */
#define CONFIG_SYS_NAND_ADDR		NAND_BASE

/* Physical address to access NAND at CS0 */
#define CONFIG_SYS_NAND_BASE		NAND_BASE

/* Max number of NAND devices */
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
/* Timeout values (in ticks) */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)

/* Flash banks JFFS2 should use */
#define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
						CONFIG_SYS_MAX_NAND_DEVICE)

#define CONFIG_SYS_JFFS2_MEM_NAND
#define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
#define CONFIG_SYS_JFFS2_NUM_BANKS	1

#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV		"nand0"
/* Start of jffs2 partition */
#define CONFIG_JFFS2_PART_OFFSET	0x680000
/* Size of jffs2 partition */
#define CONFIG_JFFS2_PART_SIZE		0xf980000

/*
 * USB
 */
#ifdef CONFIG_USB_OMAP3

#ifdef CONFIG_USB_MUSB_HCD

#define CONGIG_CMD_STORAGE

#ifdef CONFIG_USB_KEYBOARD
#define CONFIG_SYS_USB_EVENT_POLL
#define CONFIG_PREBOOT			"usb start"
#endif /* CONFIG_USB_KEYBOARD */

#endif /* CONFIG_USB_MUSB_HCD */

#ifdef CONFIG_USB_MUSB_UDC
/* USB device configuration */
#define CONFIG_USB_DEVICE
#define CONFIG_USB_TTY

/* Change these to suit your needs */
#define CONFIG_USBD_VENDORID		0x0451
#define CONFIG_USBD_PRODUCTID		0x5678
#define CONFIG_USBD_MANUFACTURER	"Texas Instruments"
#define CONFIG_USBD_PRODUCT_NAME	"EVM"
#endif /* CONFIG_USB_MUSB_UDC */

#endif /* CONFIG_USB_OMAP3 */

/* ----------------------------------------------------------------------------
 * U-Boot features
 * ----------------------------------------------------------------------------
 */
#define CONFIG_SYS_MAXARGS		16	/* max args for a command */

#define CONFIG_MISC_INIT_R

#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG

/* Size of Console IO buffer */
#define CONFIG_SYS_CBSIZE		512

/* Size of print buffer */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
						sizeof(CONFIG_SYS_PROMPT) + 16)

/* Size of bootarg buffer */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)

#define CONFIG_BOOTFILE			"uImage"

/*
 * NAND / OneNAND
 */
#if defined(CONFIG_CMD_NAND)
#define CONFIG_SYS_FLASH_BASE		NAND_BASE

#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
#elif defined(CONFIG_CMD_ONENAND)
#define CONFIG_SYS_FLASH_BASE		ONENAND_MAP
#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
#endif

#if !defined(CONFIG_ENV_IS_NOWHERE)
#if defined(CONFIG_CMD_NAND)
#define CONFIG_ENV_IS_IN_NAND
#elif defined(CONFIG_CMD_ONENAND)
#define CONFIG_ENV_IS_IN_ONENAND
#define CONFIG_ENV_OFFSET		ONENAND_ENV_OFFSET
#endif
#endif /* CONFIG_ENV_IS_NOWHERE */

#define CONFIG_ENV_ADDR			CONFIG_ENV_OFFSET

#if defined(CONFIG_CMD_NET)

/* Ethernet (SMSC9115 from SMSC9118 family) */
#define CONFIG_SMC911X
#define CONFIG_SMC911X_32_BIT
#define CONFIG_SMC911X_BASE		0x2C000000

/* BOOTP fields */
#define CONFIG_BOOTP_SUBNETMASK		0x00000001
#define CONFIG_BOOTP_GATEWAY		0x00000002
#define CONFIG_BOOTP_HOSTNAME		0x00000004
#define CONFIG_BOOTP_BOOTPATH		0x00000010

#endif /* CONFIG_CMD_NET */

/* Support for relocation */
#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE	0x800
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - \
					 GENERATED_GBL_DATA_SIZE)

/* -----------------------------------------------------------------------------
 * Board specific
 * -----------------------------------------------------------------------------
 */
#define CONFIG_SYS_NO_FLASH

/* Uncomment to define the board revision statically */
/* #define CONFIG_STATIC_BOARD_REV	OMAP3EVM_BOARD_GEN_2 */

/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE		0x40200800
#define CONFIG_SPL_MAX_SIZE		(SRAM_SCRATCH_SPACE_ADDR - \
					 CONFIG_SPL_TEXT_BASE)

#define CONFIG_SPL_BSS_START_ADDR	0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */

#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_OMAP3_ID_NAND
#define CONFIG_SPL_LDSCRIPT		"arch/arm/mach-omap2/u-boot-spl.lds"

/*
 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
 * 64 bytes before this address should be set aside for u-boot.img's
 * header. That is 0x800FFFC0--0x80100000 should not be used for any
 * other needs.
 */
#define CONFIG_SYS_TEXT_BASE		0x80100000
#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000

/* -----------------------------------------------------------------------------
 * Default environment
 * -----------------------------------------------------------------------------
 */

#define CONFIG_EXTRA_ENV_SETTINGS \
	"loadaddr=0x82000000\0" \
	"usbtty=cdc_acm\0" \
	"mmcdev=0\0" \
	"console=ttyO0,115200n8\0" \
	"mmcargs=setenv bootargs console=${console} " \
		"root=/dev/mmcblk0p2 rw " \
		"rootfstype=ext3 rootwait\0" \
	"nandargs=setenv bootargs console=${console} " \
		"root=/dev/mtdblock4 rw " \
		"rootfstype=jffs2\0" \
	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
	"bootscript=echo Running bootscript from mmc ...; " \
		"source ${loadaddr}\0" \
	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
	"mmcboot=echo Booting from mmc ...; " \
		"run mmcargs; " \
		"bootm ${loadaddr}\0" \
	"nandboot=echo Booting from nand ...; " \
		"run nandargs; " \
		"onenand read ${loadaddr} 280000 400000; " \
		"bootm ${loadaddr}\0" \

#define CONFIG_BOOTCOMMAND \
	"mmc dev ${mmcdev}; if mmc rescan; then " \
		"if run loadbootscript; then " \
			"run bootscript; " \
		"else " \
			"if run loaduimage; then " \
				"run mmcboot; " \
			"else run nandboot; " \
			"fi; " \
		"fi; " \
	"else run nandboot; fi"

#endif /* __OMAP3EVM_CONFIG_H */
Commit	Line	Data
ad9bc8e5	1	/*
741de266 SP	2	* Configuration settings for the TI OMAP3 EVM board.
	3	*
	4	* Copyright (C) 2006-2011 Texas Instruments Incorporated - http://www.ti.com/
	5	*
ad9bc8e5 DB	6	* Author :
	7	* Manikandan Pillai <mani.pillai@ti.com>
	8	* Derived from Beagle Board and 3430 SDP code by
	9	* Richard Woodruff <r-woodruff2@ti.com>
	10	* Syed Mohammed Khasim <khasim@ti.com>
	11	*
	12	* Manikandan Pillai <mani.pillai@ti.com>
	13	*
3765b3e7	14	* SPDX-License-Identifier: GPL-2.0+
ad9bc8e5 DB	15	*/
ad9bc8e5 DB	16
741de266 SP	17	#ifndef __OMAP3EVM_CONFIG_H
	18	#define __OMAP3EVM_CONFIG_H
	19
	20	#include <asm/arch/cpu.h>
987ec585	21	#include <asm/arch/omap.h>
741de266	22
741de266	23	/* ----------------------------------------------------------------------------
a187559e	24	* Supported U-Boot commands
741de266 SP	25	* ----------------------------------------------------------------------------
741de266 SP	26	*/
1ee6d31f	27
3970884c	28	#define CONFIG_CMD_JFFS2
741de266	29
3970884c	30	#define CONFIG_CMD_NAND
741de266	31
741de266	32	/* ----------------------------------------------------------------------------
a187559e	33	* Supported U-Boot features
741de266 SP	34	* ----------------------------------------------------------------------------
	35	*/
	36	#define CONFIG_SYS_LONGHELP
741de266	37
741de266 SP	38	/* Allow to overwrite serial and ethaddr */
	39	#define CONFIG_ENV_OVERWRITE
	40
	41	/* Add auto-completion support */
	42	#define CONFIG_AUTO_COMPLETE
	43
	44	/* ----------------------------------------------------------------------------
	45	* Supported hardware
	46	* ----------------------------------------------------------------------------
	47	*/
	48
673283f3	49	/* SPL */
e2ccdf89	50	#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
205b4f33	51	#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
673283f3 TR	52
673283f3 TR	53	/* Partition tables */
741de266 SP	54
	55	/* USB
	56	*
95de1e2f PK	57	* Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard
95de1e2f PK	58	* Enable CONFIG_USB_MUSB_UDD for Device functionalities.
741de266 SP	59	*/
741de266 SP	60	#define CONFIG_USB_OMAP3
95de1e2f PK	61	#define CONFIG_USB_MUSB_HCD
95de1e2f PK	62	/* #define CONFIG_USB_MUSB_UDC */
741de266	63
673283f3 TR	64	/* NAND SPL */
673283f3 TR	65	#define CONFIG_SPL_NAND_SIMPLE
6f2f01b9 SW	66	#define CONFIG_SPL_NAND_BASE
	67	#define CONFIG_SPL_NAND_DRIVERS
	68	#define CONFIG_SPL_NAND_ECC
673283f3 TR	69	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	70	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	71	#define CONFIG_SYS_NAND_PAGE_SIZE 2048
	72	#define CONFIG_SYS_NAND_OOBSIZE 64
	73	#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
	74	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
	75	#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
	76	10, 11, 12, 13}
	77	#define CONFIG_SYS_NAND_ECCSIZE 512
	78	#define CONFIG_SYS_NAND_ECCBYTES 3
3f719069	79	#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
673283f3 TR	80	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
	81	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
	82
584550d7 TR	83	/*
	84	* High level configuration options
	85	*/
	86	#define CONFIG_OMAP /* This is TI OMAP core */
	87	#define CONFIG_OMAP_GPIO
584550d7 TR	88	/* Common ARM Erratas */
	89	#define CONFIG_ARM_ERRATA_454179
	90	#define CONFIG_ARM_ERRATA_430973
	91	#define CONFIG_ARM_ERRATA_621766
	92
	93	#define CONFIG_SDRC /* The chip has SDRC controller */
	94
	95	#define CONFIG_OMAP3_EVM /* This is a OMAP3 EVM */
	96	#define CONFIG_TWL4030_POWER /* with TWL4030 PMIC */
	97
	98	/*
	99	* Clock related definitions
	100	*/
	101	#define V_OSCK 26000000 /* Clock output from T2 */
	102	#define V_SCLK (V_OSCK >> 1)
	103
	104	/*
	105	* OMAP3 has 12 GP timers, they can be driven by the system clock
	106	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
	107	* This rate is divided by a local divisor.
	108	*/
	109	#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
	110	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
	111
	112	/* Size of environment - 128KB */
	113	#define CONFIG_ENV_SIZE (128 << 10)
	114
	115	/* Size of malloc pool */
	116	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
	117
	118	/*
	119	* Physical Memory Map
	120	* Note 1: CS1 may or may not be populated
	121	* Note 2: SDRAM size is expected to be at least 32MB
	122	*/
	123	#define CONFIG_NR_DRAM_BANKS 2
	124	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
	125	#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
	126
	127	/* Limits for memtest */
	128	#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
	129	#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
	130	0x01F00000) /* 31MB */
	131
	132	/* Default load address */
	133	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
	134
741de266	135	/* -----------------------------------------------------------------------------
584550d7	136	* Hardware drivers
ee8e2254	137	* -----------------------------------------------------------------------------
ad9bc8e5	138	*/
584550d7 TR	139
	140	/*
	141	* NS16550 Configuration
	142	*/
	143	#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
	144
	145	#define CONFIG_SYS_NS16550_SERIAL
	146	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	147	#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
	148
	149	/*
	150	* select serial console configuration
	151	*/
	152	#define CONFIG_CONS_INDEX 1
	153	#define CONFIG_SERIAL1 1 /* UART1 on OMAP3 EVM */
	154	#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
	155	#define CONFIG_BAUDRATE 115200
	156	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
	157	115200}
	158
	159	/*
	160	* I2C
	161	*/
	162	#define CONFIG_SYS_I2C
	163	#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
	164	#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
	165	#define CONFIG_SYS_I2C_OMAP34XX
	166
	167	/*
	168	* PISMO support
	169	*/
	170	/* Monitor at start of flash - Reserve 2 sectors */
	171	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	172
	173	#define CONFIG_SYS_MONITOR_LEN (256 << 10)
	174
	175	/* Start location & size of environment */
	176	#define ONENAND_ENV_OFFSET 0x260000
	177	#define SMNAND_ENV_OFFSET 0x260000
	178
	179	#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
	180
	181	/*
	182	* NAND
	183	*/
	184	/* Physical address to access NAND */
	185	#define CONFIG_SYS_NAND_ADDR NAND_BASE
	186
	187	/* Physical address to access NAND at CS0 */
	188	#define CONFIG_SYS_NAND_BASE NAND_BASE
	189
	190	/* Max number of NAND devices */
	191	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	192	#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
	193	/* Timeout values (in ticks) */
	194	#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
	195	#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
	196
	197	/* Flash banks JFFS2 should use */
	198	#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
	199	CONFIG_SYS_MAX_NAND_DEVICE)
	200
	201	#define CONFIG_SYS_JFFS2_MEM_NAND
	202	#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
203	#define CONFIG_SYS_JFFS2_NUM_BANKS 1
204
205	#define CONFIG_JFFS2_NAND
206	/* nand device jffs2 lives on */
207	#define CONFIG_JFFS2_DEV "nand0"
208	/* Start of jffs2 partition */
209	#define CONFIG_JFFS2_PART_OFFSET 0x680000
210	/* Size of jffs2 partition */
211	#define CONFIG_JFFS2_PART_SIZE 0xf980000
212
213	/*
214	* USB
215	*/
216	#ifdef CONFIG_USB_OMAP3
217
218	#ifdef CONFIG_USB_MUSB_HCD
219
584550d7 TR	220	#define CONGIG_CMD_STORAGE
	221
	222	#ifdef CONFIG_USB_KEYBOARD
	223	#define CONFIG_SYS_USB_EVENT_POLL
	224	#define CONFIG_PREBOOT "usb start"
	225	#endif /* CONFIG_USB_KEYBOARD */
	226
	227	#endif /* CONFIG_USB_MUSB_HCD */
	228
	229	#ifdef CONFIG_USB_MUSB_UDC
	230	/* USB device configuration */
	231	#define CONFIG_USB_DEVICE
	232	#define CONFIG_USB_TTY
584550d7 TR	233
	234	/* Change these to suit your needs */
	235	#define CONFIG_USBD_VENDORID 0x0451
	236	#define CONFIG_USBD_PRODUCTID 0x5678
	237	#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
	238	#define CONFIG_USBD_PRODUCT_NAME "EVM"
	239	#endif /* CONFIG_USB_MUSB_UDC */
	240
	241	#endif /* CONFIG_USB_OMAP3 */
	242
	243	/* ----------------------------------------------------------------------------
	244	* U-Boot features
	245	* ----------------------------------------------------------------------------
	246	*/
	247	#define CONFIG_SYS_MAXARGS 16 /* max args for a command */
	248
	249	#define CONFIG_MISC_INIT_R
	250
	251	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	252	#define CONFIG_SETUP_MEMORY_TAGS
	253	#define CONFIG_INITRD_TAG
	254	#define CONFIG_REVISION_TAG
	255
	256	/* Size of Console IO buffer */
	257	#define CONFIG_SYS_CBSIZE 512
	258
	259	/* Size of print buffer */
	260	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	261	sizeof(CONFIG_SYS_PROMPT) + 16)
	262
	263	/* Size of bootarg buffer */
	264	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	265
	266	#define CONFIG_BOOTFILE "uImage"
	267
	268	/*
	269	* NAND / OneNAND
	270	*/
	271	#if defined(CONFIG_CMD_NAND)
	272	#define CONFIG_SYS_FLASH_BASE NAND_BASE
	273
	274	#define CONFIG_NAND_OMAP_GPMC
	275	#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
	276	#elif defined(CONFIG_CMD_ONENAND)
	277	#define CONFIG_SYS_FLASH_BASE ONENAND_MAP
	278	#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
	279	#endif
	280
	281	#if !defined(CONFIG_ENV_IS_NOWHERE)
	282	#if defined(CONFIG_CMD_NAND)
	283	#define CONFIG_ENV_IS_IN_NAND
	284	#elif defined(CONFIG_CMD_ONENAND)
	285	#define CONFIG_ENV_IS_IN_ONENAND
	286	#define CONFIG_ENV_OFFSET ONENAND_ENV_OFFSET
	287	#endif
	288	#endif /* CONFIG_ENV_IS_NOWHERE */
	289
	290	#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
	291
	292	#if defined(CONFIG_CMD_NET)
	293
	294	/* Ethernet (SMSC9115 from SMSC9118 family) */
	295	#define CONFIG_SMC911X
	296	#define CONFIG_SMC911X_32_BIT
297	#define CONFIG_SMC911X_BASE 0x2C000000
298
299	/* BOOTP fields */
300	#define CONFIG_BOOTP_SUBNETMASK 0x00000001
301	#define CONFIG_BOOTP_GATEWAY 0x00000002
302	#define CONFIG_BOOTP_HOSTNAME 0x00000004
303	#define CONFIG_BOOTP_BOOTPATH 0x00000010
304
305	#endif /* CONFIG_CMD_NET */
306
307	/* Support for relocation */
308	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
309	#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
310	#define CONFIG_SYS_INIT_RAM_SIZE 0x800
311	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
312	CONFIG_SYS_INIT_RAM_SIZE - \
313	GENERATED_GBL_DATA_SIZE)
314
315	/* -----------------------------------------------------------------------------
316	* Board specific
317	* -----------------------------------------------------------------------------
318	*/
319	#define CONFIG_SYS_NO_FLASH
320
321	/* Uncomment to define the board revision statically */
322	/* #define CONFIG_STATIC_BOARD_REV OMAP3EVM_BOARD_GEN_2 */
323
584550d7 TR	324	/* Defines for SPL */
	325	#define CONFIG_SPL_FRAMEWORK
	326	#define CONFIG_SPL_TEXT_BASE 0x40200800
fa2f81b0 TR	327	#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
fa2f81b0 TR	328	CONFIG_SPL_TEXT_BASE)
584550d7 TR	329
	330	#define CONFIG_SPL_BSS_START_ADDR 0x80000000
	331	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
	332
	333	#define CONFIG_SPL_BOARD_INIT
584550d7	334	#define CONFIG_SPL_OMAP3_ID_NAND
983e3700	335	#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
584550d7 TR	336
	337	/*
	338	* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
	339	* 64 bytes before this address should be set aside for u-boot.img's
	340	* header. That is 0x800FFFC0--0x80100000 should not be used for any
	341	* other needs.
	342	*/
	343	#define CONFIG_SYS_TEXT_BASE 0x80100000
	344	#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
	345	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
ad9bc8e5	346
ee8e2254 SP	347	/* -----------------------------------------------------------------------------
	348	* Default environment
	349	* -----------------------------------------------------------------------------
	350	*/
136cf92d	351
ad9bc8e5 DB	352	#define CONFIG_EXTRA_ENV_SETTINGS \
ad9bc8e5 DB	353	"loadaddr=0x82000000\0" \
73c8640e	354	"usbtty=cdc_acm\0" \
dcc4f38b	355	"mmcdev=0\0" \
effeda55	356	"console=ttyO0,115200n8\0" \
ad9bc8e5 DB	357	"mmcargs=setenv bootargs console=${console} " \
	358	"root=/dev/mmcblk0p2 rw " \
	359	"rootfstype=ext3 rootwait\0" \
	360	"nandargs=setenv bootargs console=${console} " \
	361	"root=/dev/mtdblock4 rw " \
	362	"rootfstype=jffs2\0" \
dcc4f38b	363	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
ad9bc8e5	364	"bootscript=echo Running bootscript from mmc ...; " \
74de7aef	365	"source ${loadaddr}\0" \
dcc4f38b	366	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
ad9bc8e5 DB	367	"mmcboot=echo Booting from mmc ...; " \
	368	"run mmcargs; " \
	369	"bootm ${loadaddr}\0" \
	370	"nandboot=echo Booting from nand ...; " \
	371	"run nandargs; " \
	372	"onenand read ${loadaddr} 280000 400000; " \
	373	"bootm ${loadaddr}\0" \
	374
	375	#define CONFIG_BOOTCOMMAND \
66968110	376	"mmc dev ${mmcdev}; if mmc rescan; then " \
ad9bc8e5 DB	377	"if run loadbootscript; then " \
	378	"run bootscript; " \
	379	"else " \
	380	"if run loaduimage; then " \
	381	"run mmcboot; " \
	382	"else run nandboot; " \
	383	"fi; " \
	384	"fi; " \
	385	"else run nandboot; fi"
	386
741de266	387	#endif /* __OMAP3EVM_CONFIG_H */