[people/ms/u-boot.git] / include / configs / omap3_evm.h

/*
 * (C) Copyright 2006-2008
 * Texas Instruments.
 * Author :
 *	Manikandan Pillai <mani.pillai@ti.com>
 * Derived from Beagle Board and 3430 SDP code by
 *	Richard Woodruff <r-woodruff2@ti.com>
 *	Syed Mohammed Khasim <khasim@ti.com>
 *
 * Manikandan Pillai <mani.pillai@ti.com>
 *
 * Configuration settings for the TI OMAP3 EVM board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_ARMV7		1	/* This is an ARM V7 CPU core */
#define CONFIG_OMAP		1	/* in a TI OMAP core */
#define CONFIG_OMAP34XX		1	/* which is a 34XX */
#define CONFIG_OMAP3430		1	/* which is in a 3430 */
#define CONFIG_OMAP3_EVM	1	/* working with EVM */

#define CONFIG_SDRC	/* The chip has SDRC controller */

#include <asm/arch/cpu.h>	/* get chip and board defs */
#include <asm/arch/omap3.h>

/*
 * Display CPU and Board information
 */
#define CONFIG_DISPLAY_CPUINFO		1
#define CONFIG_DISPLAY_BOARDINFO	1

/* Clock Defines */
#define V_OSCK			26000000	/* Clock output from T2 */
#define V_SCLK			(V_OSCK >> 1)

#undef CONFIG_USE_IRQ			/* no support for IRQs */
#define CONFIG_MISC_INIT_R

#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_INITRD_TAG		1
#define CONFIG_REVISION_TAG		1

/*
 * Size of malloc() pool
 */
#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
						/* Sector */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
#define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for */
						/* initial data */
/*
 * Hardware drivers
 */

/*
 * NS16550 Configuration
 */
#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */

#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK

/*
 * select serial console configuration
 */
#define CONFIG_CONS_INDEX		1
#define CONFIG_SYS_NS16550_COM1		OMAP34XX_UART1
#define CONFIG_SERIAL1			1	/* UART1 on OMAP3 EVM */

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
					115200}
#define CONFIG_MMC			1
#define CONFIG_OMAP3_MMC		1
#define CONFIG_DOS_PARTITION		1

/* DDR - I use Micron DDR */
#define CONFIG_OMAP3_MICRON_DDR		1

/* USB
 * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
 * Enable CONFIG_MUSB_UDD for Device functionalities.
 */
#define CONFIG_USB_OMAP3		1
#define CONFIG_MUSB_HCD			1
/* #define CONFIG_MUSB_UDC		1 */

#ifdef CONFIG_USB_OMAP3

#ifdef CONFIG_MUSB_HCD
#define CONFIG_CMD_USB

#define CONFIG_USB_STORAGE
#define CONGIG_CMD_STORAGE
#define CONFIG_CMD_FAT

#ifdef CONFIG_USB_KEYBOARD
#define CONFIG_SYS_USB_EVENT_POLL
#define CONFIG_PREBOOT "usb start"
#endif /* CONFIG_USB_KEYBOARD */

#endif /* CONFIG_MUSB_HCD */

#ifdef CONFIG_MUSB_UDC
/* USB device configuration */
#define CONFIG_USB_DEVICE		1
#define CONFIG_USB_TTY			1
#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
/* Change these to suit your needs */
#define CONFIG_USBD_VENDORID		0x0451
#define CONFIG_USBD_PRODUCTID		0x5678
#define CONFIG_USBD_MANUFACTURER	"Texas Instruments"
#define CONFIG_USBD_PRODUCT_NAME	"EVM"
#endif /* CONFIG_MUSB_UDC */

#endif /* CONFIG_USB_OMAP3 */

/* commands to include */
#include <config_cmd_default.h>

#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
#define CONFIG_CMD_FAT		/* FAT support			*/
#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/

#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
#define CONFIG_CMD_MMC		/* MMC support			*/
#define CONFIG_CMD_NAND		/* NAND support			*/
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING

#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
#undef CONFIG_CMD_IMI		/* iminfo			*/
#undef CONFIG_CMD_IMLS		/* List all found images	*/

#define CONFIG_SYS_NO_FLASH
#define CONFIG_HARD_I2C			1
#define CONFIG_SYS_I2C_SPEED		100000
#define CONFIG_SYS_I2C_SLAVE		1
#define CONFIG_SYS_I2C_BUS		0
#define CONFIG_SYS_I2C_BUS_SELECT	1
#define CONFIG_DRIVER_OMAP34XX_I2C	1

/*
 * TWL4030
 */
#define CONFIG_TWL4030_POWER		1

/*
 * Board NAND Info.
 */
#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
							/* to access nand */
#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
							/* to access */
							/* nand at CS0 */

#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
							/* NAND devices */
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV		"nand0"
/* start of jffs2 partition */
#define CONFIG_JFFS2_PART_OFFSET	0x680000
#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* sz of jffs2 part */

/* Environment information */
#define CONFIG_BOOTDELAY	10

#define CONFIG_BOOTFILE		uImage

#define CONFIG_EXTRA_ENV_SETTINGS \
	"loadaddr=0x82000000\0" \
	"usbtty=cdc_acm\0" \
	"console=ttyS2,115200n8\0" \
	"mmcargs=setenv bootargs console=${console} " \
		"root=/dev/mmcblk0p2 rw " \
		"rootfstype=ext3 rootwait\0" \
	"nandargs=setenv bootargs console=${console} " \
		"root=/dev/mtdblock4 rw " \
		"rootfstype=jffs2\0" \
	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
	"bootscript=echo Running bootscript from mmc ...; " \
		"source ${loadaddr}\0" \
	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
	"mmcboot=echo Booting from mmc ...; " \
		"run mmcargs; " \
		"bootm ${loadaddr}\0" \
	"nandboot=echo Booting from nand ...; " \
		"run nandargs; " \
		"onenand read ${loadaddr} 280000 400000; " \
		"bootm ${loadaddr}\0" \

#define CONFIG_BOOTCOMMAND \
	"if mmc init; then " \
		"if run loadbootscript; then " \
			"run bootscript; " \
		"else " \
			"if run loaduimage; then " \
				"run mmcboot; " \
			"else run nandboot; " \
			"fi; " \
		"fi; " \
	"else run nandboot; fi"

#define CONFIG_AUTO_COMPLETE	1
/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
#define CONFIG_SYS_PROMPT		"OMAP3_EVM # "
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16	/* max number of command */
						/* args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
					0x01F00000) /* 31MB */

#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
								/* address */

/*
 * OMAP3 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ			1000

/*-----------------------------------------------------------------------
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ	(4 << 10)	/* IRQ stack 4 KiB */
#define CONFIG_STACKSIZE_FIQ	(4 << 10)	/* FIQ stack 4 KiB */
#endif

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

/* SDRAM Bank Allocation method */
#define SDRC_R_B_C		1

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */

/* **** PISMO SUPPORT *** */

/* Configure the PISMO */
#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M

#define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors */
						/* on one chip */
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */

#define CONFIG_SYS_FLASH_BASE		boot_flash_base

/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP

#if defined(CONFIG_CMD_NAND)
#define CONFIG_NAND_OMAP_GPMC
#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
#define CONFIG_ENV_IS_IN_NAND
#elif defined(CONFIG_CMD_ONENAND)
#define CONFIG_ENV_IS_IN_ONENAND	1
#endif
#define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */

#define CONFIG_SYS_ENV_SECT_SIZE	boot_flash_sec
#define CONFIG_ENV_OFFSET		boot_flash_off
#define CONFIG_ENV_ADDR			boot_flash_env_addr

/*-----------------------------------------------------------------------
 * CFI FLASH driver setup
 */
/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)

/* Flash banks JFFS2 should use */
#define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
					CONFIG_SYS_MAX_NAND_DEVICE)
#define CONFIG_SYS_JFFS2_MEM_NAND
/* use flash_info[2] */
#define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
#define CONFIG_SYS_JFFS2_NUM_BANKS	1

#ifndef __ASSEMBLY__
extern unsigned int boot_flash_base;
extern volatile unsigned int boot_flash_env_addr;
extern unsigned int boot_flash_off;
extern unsigned int boot_flash_sec;
extern unsigned int boot_flash_type;
#endif

/*----------------------------------------------------------------------------
 * SMSC9115 Ethernet from SMSC9118 family
 *----------------------------------------------------------------------------
 */
#if defined(CONFIG_CMD_NET)

#define CONFIG_NET_MULTI
#define CONFIG_SMC911X
#define CONFIG_SMC911X_32_BIT
#define CONFIG_SMC911X_BASE	0x2C000000

#endif /* (CONFIG_CMD_NET) */

/*
 * BOOTP fields
 */

#define CONFIG_BOOTP_SUBNETMASK		0x00000001
#define CONFIG_BOOTP_GATEWAY		0x00000002
#define CONFIG_BOOTP_HOSTNAME		0x00000004
#define CONFIG_BOOTP_BOOTPATH		0x00000010

#endif /* __CONFIG_H */
Commit	Line	Data
ad9bc8e5 DB	1	/*
	2	* (C) Copyright 2006-2008
	3	* Texas Instruments.
	4	* Author :
	5	* Manikandan Pillai <mani.pillai@ti.com>
	6	* Derived from Beagle Board and 3430 SDP code by
	7	* Richard Woodruff <r-woodruff2@ti.com>
	8	* Syed Mohammed Khasim <khasim@ti.com>
	9	*
	10	* Manikandan Pillai <mani.pillai@ti.com>
	11	*
	12	* Configuration settings for the TI OMAP3 EVM board.
	13	*
	14	* See file CREDITS for list of people who contributed to this
	15	* project.
	16	*
	17	* This program is free software; you can redistribute it and/or
	18	* modify it under the terms of the GNU General Public License as
	19	* published by the Free Software Foundation; either version 2 of
	20	* the License, or (at your option) any later version.
	21	*
	22	* This program is distributed in the hope that it will be useful,
	23	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	24	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	25	* GNU General Public License for more details.
	26	*
	27	* You should have received a copy of the GNU General Public License
	28	* along with this program; if not, write to the Free Software
	29	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	30	* MA 02111-1307 USA
	31	*/
	32
	33	#ifndef __CONFIG_H
	34	#define __CONFIG_H
ad9bc8e5 DB	35
	36	/*
	37	* High Level Configuration Options
	38	*/
f56348af	39	#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
ad9bc8e5 DB	40	#define CONFIG_OMAP 1 /* in a TI OMAP core */
	41	#define CONFIG_OMAP34XX 1 /* which is a 34XX */
	42	#define CONFIG_OMAP3430 1 /* which is in a 3430 */
	43	#define CONFIG_OMAP3_EVM 1 /* working with EVM */
	44
cae377b5 VH	45	#define CONFIG_SDRC /* The chip has SDRC controller */
cae377b5 VH	46
ad9bc8e5 DB	47	#include <asm/arch/cpu.h> /* get chip and board defs */
	48	#include <asm/arch/omap3.h>
	49
6a6b62e3 SP	50	/*
	51	* Display CPU and Board information
	52	*/
	53	#define CONFIG_DISPLAY_CPUINFO 1
	54	#define CONFIG_DISPLAY_BOARDINFO 1
	55
ad9bc8e5 DB	56	/* Clock Defines */
	57	#define V_OSCK 26000000 /* Clock output from T2 */
	58	#define V_SCLK (V_OSCK >> 1)
	59
	60	#undef CONFIG_USE_IRQ /* no support for IRQs */
	61	#define CONFIG_MISC_INIT_R
	62
	63	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	64	#define CONFIG_SETUP_MEMORY_TAGS 1
	65	#define CONFIG_INITRD_TAG 1
	66	#define CONFIG_REVISION_TAG 1
	67
	68	/*
	69	* Size of malloc() pool
	70	*/
9c44ddcc	71	#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
ad9bc8e5	72	/* Sector */
9c44ddcc	73	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
ad9bc8e5 DB	74	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
ad9bc8e5 DB	75	/* initial data */
ad9bc8e5 DB	76	/*
	77	* Hardware drivers
	78	*/
	79
	80	/*
	81	* NS16550 Configuration
	82	*/
	83	#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
	84
	85	#define CONFIG_SYS_NS16550
	86	#define CONFIG_SYS_NS16550_SERIAL
	87	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	88	#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
	89
	90	/*
	91	* select serial console configuration
	92	*/
	93	#define CONFIG_CONS_INDEX 1
	94	#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
	95	#define CONFIG_SERIAL1 1 /* UART1 on OMAP3 EVM */
	96
	97	/* allow to overwrite serial and ethaddr */
	98	#define CONFIG_ENV_OVERWRITE
	99	#define CONFIG_BAUDRATE 115200
	100	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
	101	115200}
	102	#define CONFIG_MMC 1
	103	#define CONFIG_OMAP3_MMC 1
	104	#define CONFIG_DOS_PARTITION 1
	105
30563a04 NM	106	/* DDR - I use Micron DDR */
	107	#define CONFIG_OMAP3_MICRON_DDR 1
	108
73c8640e AKG	109	/* USB
	110	* Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
	111	* Enable CONFIG_MUSB_UDD for Device functionalities.
	112	*/
	113	#define CONFIG_USB_OMAP3 1
	114	#define CONFIG_MUSB_HCD 1
	115	/* #define CONFIG_MUSB_UDC 1 */
	116
	117	#ifdef CONFIG_USB_OMAP3
	118
	119	#ifdef CONFIG_MUSB_HCD
	120	#define CONFIG_CMD_USB
	121
	122	#define CONFIG_USB_STORAGE
	123	#define CONGIG_CMD_STORAGE
	124	#define CONFIG_CMD_FAT
	125
	126	#ifdef CONFIG_USB_KEYBOARD
	127	#define CONFIG_SYS_USB_EVENT_POLL
	128	#define CONFIG_PREBOOT "usb start"
	129	#endif /* CONFIG_USB_KEYBOARD */
	130
	131	#endif /* CONFIG_MUSB_HCD */
	132
	133	#ifdef CONFIG_MUSB_UDC
	134	/* USB device configuration */
	135	#define CONFIG_USB_DEVICE 1
	136	#define CONFIG_USB_TTY 1
	137	#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
	138	/* Change these to suit your needs */
	139	#define CONFIG_USBD_VENDORID 0x0451
	140	#define CONFIG_USBD_PRODUCTID 0x5678
	141	#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
	142	#define CONFIG_USBD_PRODUCT_NAME "EVM"
	143	#endif /* CONFIG_MUSB_UDC */
	144
	145	#endif /* CONFIG_USB_OMAP3 */
	146
ad9bc8e5 DB	147	/* commands to include */
	148	#include <config_cmd_default.h>
	149
	150	#define CONFIG_CMD_EXT2 /* EXT2 Support */
	151	#define CONFIG_CMD_FAT /* FAT support */
	152	#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
	153
	154	#define CONFIG_CMD_I2C /* I2C serial bus support */
	155	#define CONFIG_CMD_MMC /* MMC support */
675e0eaf	156	#define CONFIG_CMD_NAND /* NAND support */
ad9bc8e5 DB	157	#define CONFIG_CMD_DHCP
	158	#define CONFIG_CMD_PING
	159
	160	#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
	161	#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
	162	#undef CONFIG_CMD_IMI /* iminfo */
	163	#undef CONFIG_CMD_IMLS /* List all found images */
	164
	165	#define CONFIG_SYS_NO_FLASH
0297ec7e	166	#define CONFIG_HARD_I2C 1
ad9bc8e5 DB	167	#define CONFIG_SYS_I2C_SPEED 100000
	168	#define CONFIG_SYS_I2C_SLAVE 1
	169	#define CONFIG_SYS_I2C_BUS 0
	170	#define CONFIG_SYS_I2C_BUS_SELECT 1
	171	#define CONFIG_DRIVER_OMAP34XX_I2C 1
	172
fccc0fca TR	173	/*
	174	* TWL4030
	175	*/
	176	#define CONFIG_TWL4030_POWER 1
	177
ad9bc8e5 DB	178	/*
	179	* Board NAND Info.
	180	*/
	181	#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
	182	/* to access nand */
	183	#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
	184	/* to access */
	185	/* nand at CS0 */
	186
	187	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
	188	/* NAND devices */
ad9bc8e5 DB	189	#define CONFIG_JFFS2_NAND
	190	/* nand device jffs2 lives on */
	191	#define CONFIG_JFFS2_DEV "nand0"
	192	/* start of jffs2 partition */
	193	#define CONFIG_JFFS2_PART_OFFSET 0x680000
	194	#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
	195
	196	/* Environment information */
	197	#define CONFIG_BOOTDELAY 10
	198
136cf92d SP	199	#define CONFIG_BOOTFILE uImage
136cf92d SP	200
ad9bc8e5 DB	201	#define CONFIG_EXTRA_ENV_SETTINGS \
ad9bc8e5 DB	202	"loadaddr=0x82000000\0" \
73c8640e	203	"usbtty=cdc_acm\0" \
ad9bc8e5 DB	204	"console=ttyS2,115200n8\0" \
	205	"mmcargs=setenv bootargs console=${console} " \
	206	"root=/dev/mmcblk0p2 rw " \
	207	"rootfstype=ext3 rootwait\0" \
	208	"nandargs=setenv bootargs console=${console} " \
	209	"root=/dev/mtdblock4 rw " \
	210	"rootfstype=jffs2\0" \
	211	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
	212	"bootscript=echo Running bootscript from mmc ...; " \
74de7aef	213	"source ${loadaddr}\0" \
ad9bc8e5 DB	214	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
	215	"mmcboot=echo Booting from mmc ...; " \
	216	"run mmcargs; " \
	217	"bootm ${loadaddr}\0" \
	218	"nandboot=echo Booting from nand ...; " \
	219	"run nandargs; " \
	220	"onenand read ${loadaddr} 280000 400000; " \
	221	"bootm ${loadaddr}\0" \
	222
	223	#define CONFIG_BOOTCOMMAND \
a85693b3	224	"if mmc init; then " \
ad9bc8e5 DB	225	"if run loadbootscript; then " \
	226	"run bootscript; " \
	227	"else " \
	228	"if run loaduimage; then " \
	229	"run mmcboot; " \
	230	"else run nandboot; " \
	231	"fi; " \
	232	"fi; " \
	233	"else run nandboot; fi"
	234
	235	#define CONFIG_AUTO_COMPLETE 1
	236	/*
	237	* Miscellaneous configurable options
	238	*/
ad9bc8e5 DB	239	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	240	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
	241	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
1270ec13	242	#define CONFIG_SYS_PROMPT "OMAP3_EVM # "
ad9bc8e5 DB	243	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	244	/* Print Buffer Size */
	245	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	246	sizeof(CONFIG_SYS_PROMPT) + 16)
	247	#define CONFIG_SYS_MAXARGS 16 /* max number of command */
	248	/* args */
	249	/* Boot Argument Buffer Size */
	250	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	251	/* memtest works on */
	252	#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
	253	#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
	254	0x01F00000) /* 31MB */
	255
ad9bc8e5 DB	256	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
	257	/* address */
	258
	259	/*
d3a513c2 MP	260	* OMAP3 has 12 GP timers, they can be driven by the system clock
	261	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
	262	* This rate is divided by a local divisor.
ad9bc8e5	263	*/
ad9bc8e5	264	#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
d3a513c2 MP	265	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
d3a513c2 MP	266	#define CONFIG_SYS_HZ 1000
ad9bc8e5 DB	267
	268	/*-----------------------------------------------------------------------
	269	* Stack sizes
	270	*
	271	* The stack sizes are set up in start.S using the settings below
	272	*/
9c44ddcc	273	#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
ad9bc8e5	274	#ifdef CONFIG_USE_IRQ
9c44ddcc SP	275	#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
9c44ddcc SP	276	#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
ad9bc8e5 DB	277	#endif
	278
	279	/*-----------------------------------------------------------------------
	280	* Physical Memory Map
	281	*/
	282	#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
	283	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
9c44ddcc	284	#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
ad9bc8e5 DB	285	#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
	286
	287	/* SDRAM Bank Allocation method */
	288	#define SDRC_R_B_C 1
	289
	290	/*-----------------------------------------------------------------------
	291	* FLASH and environment organization
	292	*/
	293
	294	/* ** PISMO SUPPORT * */
	295
	296	/* Configure the PISMO */
	297	#define PISMO1_NAND_SIZE GPMC_SIZE_128M
	298	#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
	299
	300	#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
	301	/* on one chip */
	302	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
9c44ddcc	303	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
ad9bc8e5 DB	304
	305	#define CONFIG_SYS_FLASH_BASE boot_flash_base
	306
	307	/* Monitor at start of flash */
	308	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	309	#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
	310
675e0eaf VH	311	#if defined(CONFIG_CMD_NAND)
	312	#define CONFIG_NAND_OMAP_GPMC
	313	#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
	314	#define CONFIG_ENV_IS_IN_NAND
	315	#elif defined(CONFIG_CMD_ONENAND)
ad9bc8e5	316	#define CONFIG_ENV_IS_IN_ONENAND 1
675e0eaf	317	#endif
ad9bc8e5 DB	318	#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
	319	#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
	320
	321	#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
	322	#define CONFIG_ENV_OFFSET boot_flash_off
	323	#define CONFIG_ENV_ADDR boot_flash_env_addr
	324
	325	/*-----------------------------------------------------------------------
	326	* CFI FLASH driver setup
	327	*/
	328	/* timeout values are in ticks */
	329	#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
	330	#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
	331
	332	/* Flash banks JFFS2 should use */
	333	#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
	334	CONFIG_SYS_MAX_NAND_DEVICE)
	335	#define CONFIG_SYS_JFFS2_MEM_NAND
	336	/* use flash_info[2] */
	337	#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
	338	#define CONFIG_SYS_JFFS2_NUM_BANKS 1
	339
	340	#ifndef __ASSEMBLY__
ad9bc8e5 DB	341	extern unsigned int boot_flash_base;
	342	extern volatile unsigned int boot_flash_env_addr;
	343	extern unsigned int boot_flash_off;
	344	extern unsigned int boot_flash_sec;
	345	extern unsigned int boot_flash_type;
	346	#endif
	347
ad9bc8e5 DB	348	/*----------------------------------------------------------------------------
	349	* SMSC9115 Ethernet from SMSC9118 family
	350	*----------------------------------------------------------------------------
	351	*/
	352	#if defined(CONFIG_CMD_NET)
	353
736fead8 BW	354	#define CONFIG_NET_MULTI
	355	#define CONFIG_SMC911X
	356	#define CONFIG_SMC911X_32_BIT
	357	#define CONFIG_SMC911X_BASE 0x2C000000
ad9bc8e5 DB	358
	359	#endif /* (CONFIG_CMD_NET) */
	360
	361	/*
	362	* BOOTP fields
	363	*/
	364
	365	#define CONFIG_BOOTP_SUBNETMASK 0x00000001
	366	#define CONFIG_BOOTP_GATEWAY 0x00000002
	367	#define CONFIG_BOOTP_HOSTNAME 0x00000004
	368	#define CONFIG_BOOTP_BOOTPATH 0x00000010
	369
	370	#endif /* __CONFIG_H */