[people/ms/u-boot.git] / include / configs / omap3_evm.h

/*
 * (C) Copyright 2006-2008
 * Texas Instruments.
 * Author :
 *	Manikandan Pillai <mani.pillai@ti.com>
 * Derived from Beagle Board and 3430 SDP code by
 *	Richard Woodruff <r-woodruff2@ti.com>
 *	Syed Mohammed Khasim <khasim@ti.com>
 *
 * Manikandan Pillai <mani.pillai@ti.com>
 *
 * Configuration settings for the TI OMAP3 EVM board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/sizes.h>

/*
 * High Level Configuration Options
 */
#define CONFIG_ARMCORTEXA8	1	/* This is an ARM V7 CPU core */
#define CONFIG_OMAP		1	/* in a TI OMAP core */
#define CONFIG_OMAP34XX		1	/* which is a 34XX */
#define CONFIG_OMAP3430		1	/* which is in a 3430 */
#define CONFIG_OMAP3_EVM	1	/* working with EVM */

#include <asm/arch/cpu.h>	/* get chip and board defs */
#include <asm/arch/omap3.h>

/*
 * Display CPU and Board information
 */
#define CONFIG_DISPLAY_CPUINFO		1
#define CONFIG_DISPLAY_BOARDINFO	1

/* Clock Defines */
#define V_OSCK			26000000	/* Clock output from T2 */
#define V_SCLK			(V_OSCK >> 1)

#undef CONFIG_USE_IRQ			/* no support for IRQs */
#define CONFIG_MISC_INIT_R

#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_INITRD_TAG		1
#define CONFIG_REVISION_TAG		1

/*
 * Size of malloc() pool
 */
#define CONFIG_ENV_SIZE			SZ_128K	/* Total Size Environment */
						/* Sector */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + SZ_128K)
#define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for */
						/* initial data */
/*
 * Hardware drivers
 */

/*
 * NS16550 Configuration
 */
#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */

#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK

/*
 * select serial console configuration
 */
#define CONFIG_CONS_INDEX		1
#define CONFIG_SYS_NS16550_COM1		OMAP34XX_UART1
#define CONFIG_SERIAL1			1	/* UART1 on OMAP3 EVM */

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
					115200}
#define CONFIG_MMC			1
#define CONFIG_OMAP3_MMC		1
#define CONFIG_DOS_PARTITION		1

/* commands to include */
#include <config_cmd_default.h>

#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
#define CONFIG_CMD_FAT		/* FAT support			*/
#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/

#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
#define CONFIG_CMD_MMC		/* MMC support			*/
#define CONFIG_CMD_ONENAND	/* ONENAND support		*/
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING

#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
#undef CONFIG_CMD_IMI		/* iminfo			*/
#undef CONFIG_CMD_IMLS		/* List all found images	*/

#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_I2C_SPEED		100000
#define CONFIG_SYS_I2C_SLAVE		1
#define CONFIG_SYS_I2C_BUS		0
#define CONFIG_SYS_I2C_BUS_SELECT	1
#define CONFIG_DRIVER_OMAP34XX_I2C	1

/*
 * Board NAND Info.
 */
#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
							/* to access nand */
#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
							/* to access */
							/* nand at CS0 */

#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
							/* NAND devices */

#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV		"nand0"
/* start of jffs2 partition */
#define CONFIG_JFFS2_PART_OFFSET	0x680000
#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* sz of jffs2 part */

/* Environment information */
#define CONFIG_BOOTDELAY	10

#define CONFIG_BOOTFILE		uImage

#define CONFIG_EXTRA_ENV_SETTINGS \
	"loadaddr=0x82000000\0" \
	"console=ttyS2,115200n8\0" \
	"mmcargs=setenv bootargs console=${console} " \
		"root=/dev/mmcblk0p2 rw " \
		"rootfstype=ext3 rootwait\0" \
	"nandargs=setenv bootargs console=${console} " \
		"root=/dev/mtdblock4 rw " \
		"rootfstype=jffs2\0" \
	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
	"bootscript=echo Running bootscript from mmc ...; " \
		"source ${loadaddr}\0" \
	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
	"mmcboot=echo Booting from mmc ...; " \
		"run mmcargs; " \
		"bootm ${loadaddr}\0" \
	"nandboot=echo Booting from nand ...; " \
		"run nandargs; " \
		"onenand read ${loadaddr} 280000 400000; " \
		"bootm ${loadaddr}\0" \

#define CONFIG_BOOTCOMMAND \
	"if mmc init; then " \
		"if run loadbootscript; then " \
			"run bootscript; " \
		"else " \
			"if run loaduimage; then " \
				"run mmcboot; " \
			"else run nandboot; " \
			"fi; " \
		"fi; " \
	"else run nandboot; fi"

#define CONFIG_AUTO_COMPLETE	1
/*
 * Miscellaneous configurable options
 */
#define V_PROMPT		"OMAP3_EVM # "

#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
#define CONFIG_SYS_PROMPT		V_PROMPT
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16	/* max number of command */
						/* args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
					0x01F00000) /* 31MB */

#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
								/* address */

/*
 * OMAP3 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ			1000

/*-----------------------------------------------------------------------
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE	SZ_128K	/* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ	SZ_4K	/* IRQ stack */
#define CONFIG_STACKSIZE_FIQ	SZ_4K	/* FIQ stack */
#endif

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_1_SIZE	SZ_32M	/* at least 32 meg */
#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

/* SDRAM Bank Allocation method */
#define SDRC_R_B_C		1

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */

/* **** PISMO SUPPORT *** */

/* Configure the PISMO */
#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M

#define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors */
						/* on one chip */
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
#define CONFIG_SYS_MONITOR_LEN		SZ_256K	/* Reserve 2 sectors */

#define CONFIG_SYS_FLASH_BASE		boot_flash_base

/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP

#define CONFIG_ENV_IS_IN_ONENAND	1
#define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */

#define CONFIG_SYS_ENV_SECT_SIZE	boot_flash_sec
#define CONFIG_ENV_OFFSET		boot_flash_off
#define CONFIG_ENV_ADDR			boot_flash_env_addr

/*-----------------------------------------------------------------------
 * CFI FLASH driver setup
 */
/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)

/* Flash banks JFFS2 should use */
#define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
					CONFIG_SYS_MAX_NAND_DEVICE)
#define CONFIG_SYS_JFFS2_MEM_NAND
/* use flash_info[2] */
#define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
#define CONFIG_SYS_JFFS2_NUM_BANKS	1

#ifndef __ASSEMBLY__
extern gpmc_csx_t *nand_cs_base;
extern gpmc_t *gpmc_cfg_base;
extern unsigned int boot_flash_base;
extern volatile unsigned int boot_flash_env_addr;
extern unsigned int boot_flash_off;
extern unsigned int boot_flash_sec;
extern unsigned int boot_flash_type;
#endif

/*----------------------------------------------------------------------------
 * SMSC9115 Ethernet from SMSC9118 family
 *----------------------------------------------------------------------------
 */
#if defined(CONFIG_CMD_NET)

#define CONFIG_DRIVER_SMC911X
#define CONFIG_DRIVER_SMC911X_32_BIT
#define CONFIG_DRIVER_SMC911X_BASE	0x2C000000

#endif /* (CONFIG_CMD_NET) */

/*
 * BOOTP fields
 */

#define CONFIG_BOOTP_SUBNETMASK		0x00000001
#define CONFIG_BOOTP_GATEWAY		0x00000002
#define CONFIG_BOOTP_HOSTNAME		0x00000004
#define CONFIG_BOOTP_BOOTPATH		0x00000010

#endif /* __CONFIG_H */
Commit	Line	Data
ad9bc8e5 DB	1	/*
	2	* (C) Copyright 2006-2008
	3	* Texas Instruments.
	4	* Author :
	5	* Manikandan Pillai <mani.pillai@ti.com>
	6	* Derived from Beagle Board and 3430 SDP code by
	7	* Richard Woodruff <r-woodruff2@ti.com>
	8	* Syed Mohammed Khasim <khasim@ti.com>
	9	*
	10	* Manikandan Pillai <mani.pillai@ti.com>
	11	*
	12	* Configuration settings for the TI OMAP3 EVM board.
	13	*
	14	* See file CREDITS for list of people who contributed to this
	15	* project.
	16	*
	17	* This program is free software; you can redistribute it and/or
	18	* modify it under the terms of the GNU General Public License as
	19	* published by the Free Software Foundation; either version 2 of
	20	* the License, or (at your option) any later version.
	21	*
	22	* This program is distributed in the hope that it will be useful,
	23	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	24	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	25	* GNU General Public License for more details.
	26	*
	27	* You should have received a copy of the GNU General Public License
	28	* along with this program; if not, write to the Free Software
	29	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	30	* MA 02111-1307 USA
	31	*/
	32
	33	#ifndef __CONFIG_H
	34	#define __CONFIG_H
	35	#include <asm/sizes.h>
	36
	37	/*
	38	* High Level Configuration Options
	39	*/
	40	#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
	41	#define CONFIG_OMAP 1 /* in a TI OMAP core */
	42	#define CONFIG_OMAP34XX 1 /* which is a 34XX */
	43	#define CONFIG_OMAP3430 1 /* which is in a 3430 */
	44	#define CONFIG_OMAP3_EVM 1 /* working with EVM */
	45
	46	#include <asm/arch/cpu.h> /* get chip and board defs */
	47	#include <asm/arch/omap3.h>
	48
6a6b62e3 SP	49	/*
	50	* Display CPU and Board information
	51	*/
	52	#define CONFIG_DISPLAY_CPUINFO 1
	53	#define CONFIG_DISPLAY_BOARDINFO 1
	54
ad9bc8e5 DB	55	/* Clock Defines */
	56	#define V_OSCK 26000000 /* Clock output from T2 */
	57	#define V_SCLK (V_OSCK >> 1)
	58
	59	#undef CONFIG_USE_IRQ /* no support for IRQs */
	60	#define CONFIG_MISC_INIT_R
	61
	62	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	63	#define CONFIG_SETUP_MEMORY_TAGS 1
	64	#define CONFIG_INITRD_TAG 1
	65	#define CONFIG_REVISION_TAG 1
	66
	67	/*
	68	* Size of malloc() pool
	69	*/
	70	#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */
	71	/* Sector */
	72	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K)
	73	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
	74	/* initial data */
ad9bc8e5 DB	75	/*
	76	* Hardware drivers
	77	*/
	78
	79	/*
	80	* NS16550 Configuration
	81	*/
	82	#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
	83
	84	#define CONFIG_SYS_NS16550
	85	#define CONFIG_SYS_NS16550_SERIAL
	86	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	87	#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
	88
	89	/*
	90	* select serial console configuration
	91	*/
	92	#define CONFIG_CONS_INDEX 1
	93	#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
	94	#define CONFIG_SERIAL1 1 /* UART1 on OMAP3 EVM */
	95
	96	/* allow to overwrite serial and ethaddr */
	97	#define CONFIG_ENV_OVERWRITE
	98	#define CONFIG_BAUDRATE 115200
	99	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
	100	115200}
	101	#define CONFIG_MMC 1
	102	#define CONFIG_OMAP3_MMC 1
	103	#define CONFIG_DOS_PARTITION 1
	104
	105	/* commands to include */
	106	#include <config_cmd_default.h>
	107
	108	#define CONFIG_CMD_EXT2 /* EXT2 Support */
	109	#define CONFIG_CMD_FAT /* FAT support */
	110	#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
	111
	112	#define CONFIG_CMD_I2C /* I2C serial bus support */
	113	#define CONFIG_CMD_MMC /* MMC support */
	114	#define CONFIG_CMD_ONENAND /* ONENAND support */
	115	#define CONFIG_CMD_DHCP
	116	#define CONFIG_CMD_PING
	117
	118	#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
	119	#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
	120	#undef CONFIG_CMD_IMI /* iminfo */
	121	#undef CONFIG_CMD_IMLS /* List all found images */
	122
	123	#define CONFIG_SYS_NO_FLASH
	124	#define CONFIG_SYS_I2C_SPEED 100000
	125	#define CONFIG_SYS_I2C_SLAVE 1
	126	#define CONFIG_SYS_I2C_BUS 0
	127	#define CONFIG_SYS_I2C_BUS_SELECT 1
	128	#define CONFIG_DRIVER_OMAP34XX_I2C 1
	129
	130	/*
	131	* Board NAND Info.
	132	*/
	133	#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
	134	/* to access nand */
	135	#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
	136	/* to access */
	137	/* nand at CS0 */
	138
139	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
140	/* NAND devices */
ad9bc8e5 DB	141
	142	#define CONFIG_JFFS2_NAND
	143	/* nand device jffs2 lives on */
	144	#define CONFIG_JFFS2_DEV "nand0"
	145	/* start of jffs2 partition */
	146	#define CONFIG_JFFS2_PART_OFFSET 0x680000
	147	#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
	148
	149	/* Environment information */
	150	#define CONFIG_BOOTDELAY 10
	151
136cf92d SP	152	#define CONFIG_BOOTFILE uImage
136cf92d SP	153
ad9bc8e5 DB	154	#define CONFIG_EXTRA_ENV_SETTINGS \
	155	"loadaddr=0x82000000\0" \
	156	"console=ttyS2,115200n8\0" \
	157	"mmcargs=setenv bootargs console=${console} " \
	158	"root=/dev/mmcblk0p2 rw " \
	159	"rootfstype=ext3 rootwait\0" \
	160	"nandargs=setenv bootargs console=${console} " \
	161	"root=/dev/mtdblock4 rw " \
	162	"rootfstype=jffs2\0" \
	163	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
	164	"bootscript=echo Running bootscript from mmc ...; " \
74de7aef	165	"source ${loadaddr}\0" \
ad9bc8e5 DB	166	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
	167	"mmcboot=echo Booting from mmc ...; " \
	168	"run mmcargs; " \
	169	"bootm ${loadaddr}\0" \
	170	"nandboot=echo Booting from nand ...; " \
	171	"run nandargs; " \
	172	"onenand read ${loadaddr} 280000 400000; " \
	173	"bootm ${loadaddr}\0" \
	174
	175	#define CONFIG_BOOTCOMMAND \
a85693b3	176	"if mmc init; then " \
ad9bc8e5 DB	177	"if run loadbootscript; then " \
	178	"run bootscript; " \
	179	"else " \
	180	"if run loaduimage; then " \
	181	"run mmcboot; " \
	182	"else run nandboot; " \
	183	"fi; " \
	184	"fi; " \
	185	"else run nandboot; fi"
	186
	187	#define CONFIG_AUTO_COMPLETE 1
	188	/*
	189	* Miscellaneous configurable options
	190	*/
	191	#define V_PROMPT "OMAP3_EVM # "
	192
	193	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	194	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
	195	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
	196	#define CONFIG_SYS_PROMPT V_PROMPT
	197	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	198	/* Print Buffer Size */
	199	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	200	sizeof(CONFIG_SYS_PROMPT) + 16)
	201	#define CONFIG_SYS_MAXARGS 16 /* max number of command */
	202	/* args */
	203	/* Boot Argument Buffer Size */
	204	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	205	/* memtest works on */
	206	#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
	207	#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
	208	0x01F00000) /* 31MB */
	209
ad9bc8e5 DB	210	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
	211	/* address */
	212
	213	/*
d3a513c2 MP	214	* OMAP3 has 12 GP timers, they can be driven by the system clock
	215	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
	216	* This rate is divided by a local divisor.
ad9bc8e5	217	*/
ad9bc8e5	218	#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
d3a513c2 MP	219	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
d3a513c2 MP	220	#define CONFIG_SYS_HZ 1000
ad9bc8e5 DB	221
	222	/*-----------------------------------------------------------------------
	223	* Stack sizes
	224	*
	225	* The stack sizes are set up in start.S using the settings below
	226	*/
	227	#define CONFIG_STACKSIZE SZ_128K /* regular stack */
	228	#ifdef CONFIG_USE_IRQ
	229	#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */
	230	#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */
	231	#endif
	232
	233	/*-----------------------------------------------------------------------
	234	* Physical Memory Map
	235	*/
	236	#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
	237	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
	238	#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */
	239	#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
	240
	241	/* SDRAM Bank Allocation method */
	242	#define SDRC_R_B_C 1
	243
	244	/*-----------------------------------------------------------------------
	245	* FLASH and environment organization
	246	*/
	247
	248	/* ** PISMO SUPPORT * */
	249
	250	/* Configure the PISMO */
	251	#define PISMO1_NAND_SIZE GPMC_SIZE_128M
	252	#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
	253
	254	#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
	255	/* on one chip */
	256	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
	257	#define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */
	258
	259	#define CONFIG_SYS_FLASH_BASE boot_flash_base
	260
	261	/* Monitor at start of flash */
	262	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	263	#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
	264
	265	#define CONFIG_ENV_IS_IN_ONENAND 1
	266	#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
	267	#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
	268
	269	#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
	270	#define CONFIG_ENV_OFFSET boot_flash_off
	271	#define CONFIG_ENV_ADDR boot_flash_env_addr
	272
	273	/*-----------------------------------------------------------------------
	274	* CFI FLASH driver setup
	275	*/
	276	/* timeout values are in ticks */
	277	#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
	278	#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
	279
	280	/* Flash banks JFFS2 should use */
	281	#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
	282	CONFIG_SYS_MAX_NAND_DEVICE)
	283	#define CONFIG_SYS_JFFS2_MEM_NAND
	284	/* use flash_info[2] */
285	#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
286	#define CONFIG_SYS_JFFS2_NUM_BANKS 1
287
288	#ifndef __ASSEMBLY__
289	extern gpmc_csx_t *nand_cs_base;
290	extern gpmc_t *gpmc_cfg_base;
291	extern unsigned int boot_flash_base;
292	extern volatile unsigned int boot_flash_env_addr;
293	extern unsigned int boot_flash_off;
294	extern unsigned int boot_flash_sec;
295	extern unsigned int boot_flash_type;
296	#endif
297
ad9bc8e5 DB	298	/*----------------------------------------------------------------------------
	299	* SMSC9115 Ethernet from SMSC9118 family
	300	*----------------------------------------------------------------------------
	301	*/
	302	#if defined(CONFIG_CMD_NET)
	303
	304	#define CONFIG_DRIVER_SMC911X
	305	#define CONFIG_DRIVER_SMC911X_32_BIT
	306	#define CONFIG_DRIVER_SMC911X_BASE 0x2C000000
	307
	308	#endif /* (CONFIG_CMD_NET) */
	309
	310	/*
	311	* BOOTP fields
	312	*/
	313
	314	#define CONFIG_BOOTP_SUBNETMASK 0x00000001
	315	#define CONFIG_BOOTP_GATEWAY 0x00000002
	316	#define CONFIG_BOOTP_HOSTNAME 0x00000004
	317	#define CONFIG_BOOTP_BOOTPATH 0x00000010
	318
	319	#endif /* __CONFIG_H */