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ad9bc8e5 DB |
1 | /* |
2 | * (C) Copyright 2006-2008 | |
3 | * Texas Instruments. | |
4 | * Author : | |
5 | * Manikandan Pillai <mani.pillai@ti.com> | |
6 | * Derived from Beagle Board and 3430 SDP code by | |
7 | * Richard Woodruff <r-woodruff2@ti.com> | |
8 | * Syed Mohammed Khasim <khasim@ti.com> | |
9 | * | |
10 | * Manikandan Pillai <mani.pillai@ti.com> | |
11 | * | |
12 | * Configuration settings for the TI OMAP3 EVM board. | |
13 | * | |
14 | * See file CREDITS for list of people who contributed to this | |
15 | * project. | |
16 | * | |
17 | * This program is free software; you can redistribute it and/or | |
18 | * modify it under the terms of the GNU General Public License as | |
19 | * published by the Free Software Foundation; either version 2 of | |
20 | * the License, or (at your option) any later version. | |
21 | * | |
22 | * This program is distributed in the hope that it will be useful, | |
23 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
24 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
25 | * GNU General Public License for more details. | |
26 | * | |
27 | * You should have received a copy of the GNU General Public License | |
28 | * along with this program; if not, write to the Free Software | |
29 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
30 | * MA 02111-1307 USA | |
31 | */ | |
32 | ||
33 | #ifndef __CONFIG_H | |
34 | #define __CONFIG_H | |
ad9bc8e5 DB |
35 | |
36 | /* | |
37 | * High Level Configuration Options | |
38 | */ | |
f56348af | 39 | #define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ |
ad9bc8e5 DB |
40 | #define CONFIG_OMAP 1 /* in a TI OMAP core */ |
41 | #define CONFIG_OMAP34XX 1 /* which is a 34XX */ | |
42 | #define CONFIG_OMAP3430 1 /* which is in a 3430 */ | |
43 | #define CONFIG_OMAP3_EVM 1 /* working with EVM */ | |
44 | ||
cae377b5 VH |
45 | #define CONFIG_SDRC /* The chip has SDRC controller */ |
46 | ||
ad9bc8e5 DB |
47 | #include <asm/arch/cpu.h> /* get chip and board defs */ |
48 | #include <asm/arch/omap3.h> | |
49 | ||
6a6b62e3 SP |
50 | /* |
51 | * Display CPU and Board information | |
52 | */ | |
53 | #define CONFIG_DISPLAY_CPUINFO 1 | |
54 | #define CONFIG_DISPLAY_BOARDINFO 1 | |
55 | ||
ad9bc8e5 DB |
56 | /* Clock Defines */ |
57 | #define V_OSCK 26000000 /* Clock output from T2 */ | |
58 | #define V_SCLK (V_OSCK >> 1) | |
59 | ||
60 | #undef CONFIG_USE_IRQ /* no support for IRQs */ | |
61 | #define CONFIG_MISC_INIT_R | |
62 | ||
63 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ | |
64 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
65 | #define CONFIG_INITRD_TAG 1 | |
66 | #define CONFIG_REVISION_TAG 1 | |
67 | ||
68 | /* | |
69 | * Size of malloc() pool | |
70 | */ | |
9c44ddcc | 71 | #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ |
ad9bc8e5 | 72 | /* Sector */ |
9c44ddcc | 73 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) |
ad9bc8e5 | 74 | /* initial data */ |
ad9bc8e5 DB |
75 | /* |
76 | * Hardware drivers | |
77 | */ | |
78 | ||
79 | /* | |
80 | * NS16550 Configuration | |
81 | */ | |
82 | #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ | |
83 | ||
84 | #define CONFIG_SYS_NS16550 | |
85 | #define CONFIG_SYS_NS16550_SERIAL | |
86 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) | |
87 | #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK | |
88 | ||
89 | /* | |
90 | * select serial console configuration | |
91 | */ | |
92 | #define CONFIG_CONS_INDEX 1 | |
93 | #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 | |
94 | #define CONFIG_SERIAL1 1 /* UART1 on OMAP3 EVM */ | |
95 | ||
96 | /* allow to overwrite serial and ethaddr */ | |
97 | #define CONFIG_ENV_OVERWRITE | |
98 | #define CONFIG_BAUDRATE 115200 | |
99 | #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ | |
100 | 115200} | |
101 | #define CONFIG_MMC 1 | |
102 | #define CONFIG_OMAP3_MMC 1 | |
103 | #define CONFIG_DOS_PARTITION 1 | |
104 | ||
30563a04 NM |
105 | /* DDR - I use Micron DDR */ |
106 | #define CONFIG_OMAP3_MICRON_DDR 1 | |
107 | ||
73c8640e AKG |
108 | /* USB |
109 | * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard | |
110 | * Enable CONFIG_MUSB_UDD for Device functionalities. | |
111 | */ | |
112 | #define CONFIG_USB_OMAP3 1 | |
113 | #define CONFIG_MUSB_HCD 1 | |
114 | /* #define CONFIG_MUSB_UDC 1 */ | |
115 | ||
116 | #ifdef CONFIG_USB_OMAP3 | |
117 | ||
118 | #ifdef CONFIG_MUSB_HCD | |
119 | #define CONFIG_CMD_USB | |
120 | ||
121 | #define CONFIG_USB_STORAGE | |
122 | #define CONGIG_CMD_STORAGE | |
123 | #define CONFIG_CMD_FAT | |
124 | ||
125 | #ifdef CONFIG_USB_KEYBOARD | |
126 | #define CONFIG_SYS_USB_EVENT_POLL | |
127 | #define CONFIG_PREBOOT "usb start" | |
128 | #endif /* CONFIG_USB_KEYBOARD */ | |
129 | ||
130 | #endif /* CONFIG_MUSB_HCD */ | |
131 | ||
132 | #ifdef CONFIG_MUSB_UDC | |
133 | /* USB device configuration */ | |
134 | #define CONFIG_USB_DEVICE 1 | |
135 | #define CONFIG_USB_TTY 1 | |
136 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 | |
137 | /* Change these to suit your needs */ | |
138 | #define CONFIG_USBD_VENDORID 0x0451 | |
139 | #define CONFIG_USBD_PRODUCTID 0x5678 | |
140 | #define CONFIG_USBD_MANUFACTURER "Texas Instruments" | |
141 | #define CONFIG_USBD_PRODUCT_NAME "EVM" | |
142 | #endif /* CONFIG_MUSB_UDC */ | |
143 | ||
144 | #endif /* CONFIG_USB_OMAP3 */ | |
145 | ||
ad9bc8e5 DB |
146 | /* commands to include */ |
147 | #include <config_cmd_default.h> | |
148 | ||
149 | #define CONFIG_CMD_EXT2 /* EXT2 Support */ | |
150 | #define CONFIG_CMD_FAT /* FAT support */ | |
151 | #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ | |
152 | ||
153 | #define CONFIG_CMD_I2C /* I2C serial bus support */ | |
154 | #define CONFIG_CMD_MMC /* MMC support */ | |
675e0eaf | 155 | #define CONFIG_CMD_NAND /* NAND support */ |
ad9bc8e5 DB |
156 | #define CONFIG_CMD_DHCP |
157 | #define CONFIG_CMD_PING | |
158 | ||
159 | #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ | |
160 | #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ | |
161 | #undef CONFIG_CMD_IMI /* iminfo */ | |
162 | #undef CONFIG_CMD_IMLS /* List all found images */ | |
163 | ||
164 | #define CONFIG_SYS_NO_FLASH | |
0297ec7e | 165 | #define CONFIG_HARD_I2C 1 |
ad9bc8e5 DB |
166 | #define CONFIG_SYS_I2C_SPEED 100000 |
167 | #define CONFIG_SYS_I2C_SLAVE 1 | |
168 | #define CONFIG_SYS_I2C_BUS 0 | |
169 | #define CONFIG_SYS_I2C_BUS_SELECT 1 | |
170 | #define CONFIG_DRIVER_OMAP34XX_I2C 1 | |
171 | ||
fccc0fca TR |
172 | /* |
173 | * TWL4030 | |
174 | */ | |
175 | #define CONFIG_TWL4030_POWER 1 | |
176 | ||
ad9bc8e5 DB |
177 | /* |
178 | * Board NAND Info. | |
179 | */ | |
180 | #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ | |
181 | /* to access nand */ | |
182 | #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ | |
183 | /* to access */ | |
184 | /* nand at CS0 */ | |
185 | ||
186 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ | |
187 | /* NAND devices */ | |
ad9bc8e5 DB |
188 | #define CONFIG_JFFS2_NAND |
189 | /* nand device jffs2 lives on */ | |
190 | #define CONFIG_JFFS2_DEV "nand0" | |
191 | /* start of jffs2 partition */ | |
192 | #define CONFIG_JFFS2_PART_OFFSET 0x680000 | |
193 | #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ | |
194 | ||
195 | /* Environment information */ | |
196 | #define CONFIG_BOOTDELAY 10 | |
197 | ||
136cf92d SP |
198 | #define CONFIG_BOOTFILE uImage |
199 | ||
ad9bc8e5 DB |
200 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
201 | "loadaddr=0x82000000\0" \ | |
73c8640e | 202 | "usbtty=cdc_acm\0" \ |
ad9bc8e5 DB |
203 | "console=ttyS2,115200n8\0" \ |
204 | "mmcargs=setenv bootargs console=${console} " \ | |
205 | "root=/dev/mmcblk0p2 rw " \ | |
206 | "rootfstype=ext3 rootwait\0" \ | |
207 | "nandargs=setenv bootargs console=${console} " \ | |
208 | "root=/dev/mtdblock4 rw " \ | |
209 | "rootfstype=jffs2\0" \ | |
210 | "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ | |
211 | "bootscript=echo Running bootscript from mmc ...; " \ | |
74de7aef | 212 | "source ${loadaddr}\0" \ |
ad9bc8e5 DB |
213 | "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ |
214 | "mmcboot=echo Booting from mmc ...; " \ | |
215 | "run mmcargs; " \ | |
216 | "bootm ${loadaddr}\0" \ | |
217 | "nandboot=echo Booting from nand ...; " \ | |
218 | "run nandargs; " \ | |
219 | "onenand read ${loadaddr} 280000 400000; " \ | |
220 | "bootm ${loadaddr}\0" \ | |
221 | ||
222 | #define CONFIG_BOOTCOMMAND \ | |
a85693b3 | 223 | "if mmc init; then " \ |
ad9bc8e5 DB |
224 | "if run loadbootscript; then " \ |
225 | "run bootscript; " \ | |
226 | "else " \ | |
227 | "if run loaduimage; then " \ | |
228 | "run mmcboot; " \ | |
229 | "else run nandboot; " \ | |
230 | "fi; " \ | |
231 | "fi; " \ | |
232 | "else run nandboot; fi" | |
233 | ||
234 | #define CONFIG_AUTO_COMPLETE 1 | |
235 | /* | |
236 | * Miscellaneous configurable options | |
237 | */ | |
ad9bc8e5 DB |
238 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
239 | #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ | |
240 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
1270ec13 | 241 | #define CONFIG_SYS_PROMPT "OMAP3_EVM # " |
ad9bc8e5 DB |
242 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
243 | /* Print Buffer Size */ | |
244 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
245 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
246 | #define CONFIG_SYS_MAXARGS 16 /* max number of command */ | |
247 | /* args */ | |
248 | /* Boot Argument Buffer Size */ | |
249 | #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) | |
250 | /* memtest works on */ | |
251 | #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) | |
252 | #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ | |
253 | 0x01F00000) /* 31MB */ | |
254 | ||
ad9bc8e5 DB |
255 | #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ |
256 | /* address */ | |
257 | ||
258 | /* | |
d3a513c2 MP |
259 | * OMAP3 has 12 GP timers, they can be driven by the system clock |
260 | * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). | |
261 | * This rate is divided by a local divisor. | |
ad9bc8e5 | 262 | */ |
ad9bc8e5 | 263 | #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 |
d3a513c2 MP |
264 | #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ |
265 | #define CONFIG_SYS_HZ 1000 | |
ad9bc8e5 DB |
266 | |
267 | /*----------------------------------------------------------------------- | |
268 | * Stack sizes | |
269 | * | |
270 | * The stack sizes are set up in start.S using the settings below | |
271 | */ | |
9c44ddcc | 272 | #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ |
ad9bc8e5 | 273 | #ifdef CONFIG_USE_IRQ |
9c44ddcc SP |
274 | #define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ |
275 | #define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ | |
ad9bc8e5 DB |
276 | #endif |
277 | ||
278 | /*----------------------------------------------------------------------- | |
279 | * Physical Memory Map | |
280 | */ | |
281 | #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ | |
282 | #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 | |
9c44ddcc | 283 | #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ |
ad9bc8e5 DB |
284 | #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 |
285 | ||
286 | /* SDRAM Bank Allocation method */ | |
287 | #define SDRC_R_B_C 1 | |
288 | ||
289 | /*----------------------------------------------------------------------- | |
290 | * FLASH and environment organization | |
291 | */ | |
292 | ||
293 | /* **** PISMO SUPPORT *** */ | |
294 | ||
295 | /* Configure the PISMO */ | |
296 | #define PISMO1_NAND_SIZE GPMC_SIZE_128M | |
297 | #define PISMO1_ONEN_SIZE GPMC_SIZE_128M | |
298 | ||
9c44ddcc | 299 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ |
ad9bc8e5 | 300 | |
6cbec7b3 LC |
301 | #if defined(CONFIG_CMD_NAND) |
302 | #define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE | |
303 | #elif defined(CONFIG_CMD_ONENAND) | |
304 | #define CONFIG_SYS_FLASH_BASE PISMO1_ONEN_BASE | |
305 | #endif | |
ad9bc8e5 DB |
306 | |
307 | /* Monitor at start of flash */ | |
308 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
309 | #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP | |
310 | ||
6cbec7b3 LC |
311 | #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ |
312 | #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ | |
313 | ||
675e0eaf VH |
314 | #if defined(CONFIG_CMD_NAND) |
315 | #define CONFIG_NAND_OMAP_GPMC | |
316 | #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 | |
317 | #define CONFIG_ENV_IS_IN_NAND | |
6cbec7b3 | 318 | #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET |
675e0eaf | 319 | #elif defined(CONFIG_CMD_ONENAND) |
ad9bc8e5 | 320 | #define CONFIG_ENV_IS_IN_ONENAND 1 |
6cbec7b3 | 321 | #define CONFIG_ENV_OFFSET ONENAND_ENV_OFFSET |
675e0eaf | 322 | #endif |
ad9bc8e5 | 323 | |
6cbec7b3 LC |
324 | #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ |
325 | #define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET | |
ad9bc8e5 | 326 | |
6a1e58eb SP |
327 | /* |
328 | * Support for relocation | |
329 | */ | |
330 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | |
f899198a SP |
331 | #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 |
332 | #define CONFIG_SYS_INIT_RAM_SIZE 0x800 | |
333 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ | |
334 | CONFIG_SYS_INIT_RAM_SIZE - \ | |
335 | GENERATED_GBL_DATA_SIZE) | |
6a1e58eb | 336 | |
76ee9a2c SP |
337 | /* |
338 | * Define the board revision statically | |
339 | */ | |
340 | /* #define CONFIG_STATIC_BOARD_REV OMAP3EVM_BOARD_GEN_2 */ | |
341 | ||
ad9bc8e5 DB |
342 | /*---------------------------------------------------------------------------- |
343 | * SMSC9115 Ethernet from SMSC9118 family | |
344 | *---------------------------------------------------------------------------- | |
345 | */ | |
346 | #if defined(CONFIG_CMD_NET) | |
347 | ||
736fead8 BW |
348 | #define CONFIG_NET_MULTI |
349 | #define CONFIG_SMC911X | |
350 | #define CONFIG_SMC911X_32_BIT | |
351 | #define CONFIG_SMC911X_BASE 0x2C000000 | |
ad9bc8e5 DB |
352 | |
353 | #endif /* (CONFIG_CMD_NET) */ | |
354 | ||
355 | /* | |
356 | * BOOTP fields | |
357 | */ | |
358 | ||
359 | #define CONFIG_BOOTP_SUBNETMASK 0x00000001 | |
360 | #define CONFIG_BOOTP_GATEWAY 0x00000002 | |
361 | #define CONFIG_BOOTP_HOSTNAME 0x00000004 | |
362 | #define CONFIG_BOOTP_BOOTPATH 0x00000010 | |
363 | ||
364 | #endif /* __CONFIG_H */ |