[people/ms/u-boot.git] / include / configs / omap3_pandora.h

/*
 * (C) Copyright 2008
 * Grazvydas Ignotas <notasas@gmail.com>
 *
 * Configuration settings for the OMAP3 Pandora.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_ARMV7		1	/* This is an ARM V7 CPU core */
#define CONFIG_OMAP		1	/* in a TI OMAP core */
#define CONFIG_OMAP34XX		1	/* which is a 34XX */
#define CONFIG_OMAP3430		1	/* which is in a 3430 */
#define CONFIG_OMAP3_PANDORA	1	/* working with pandora */

#define CONFIG_SDRC	/* The chip has SDRC controller */

#include <asm/arch/cpu.h>	/* get chip and board defs */
#include <asm/arch/omap3.h>

/*
 * Display CPU and Board information
 */
#define CONFIG_DISPLAY_CPUINFO		1
#define CONFIG_DISPLAY_BOARDINFO	1

/* Clock Defines */
#define V_OSCK			26000000	/* Clock output from T2 */
#define V_SCLK			(V_OSCK >> 1)

#undef CONFIG_USE_IRQ		/* no support for IRQs */
#define CONFIG_MISC_INIT_R

#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_INITRD_TAG		1
#define CONFIG_REVISION_TAG		1

/*
 * Size of malloc() pool
 */
#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
						/* Sector */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
#define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for */
						/* initial data */

/*
 * Hardware drivers
 */

/*
 * NS16550 Configuration
 */
#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */

#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK

/*
 * select serial console configuration
 */
#define CONFIG_CONS_INDEX		3
#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
#define CONFIG_SERIAL3			3

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600, \
					115200}
#define CONFIG_MMC			1
#define CONFIG_OMAP3_MMC		1
#define CONFIG_DOS_PARTITION		1

/* DDR - I use Micron DDR */
#define CONFIG_OMAP3_MICRON_DDR		1

/* commands to include */
#include <config_cmd_default.h>

#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
#define CONFIG_CMD_FAT		/* FAT support			*/
#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/

#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
#define CONFIG_CMD_MMC		/* MMC support			*/
#define CONFIG_CMD_NAND		/* NAND support			*/

#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
#undef CONFIG_CMD_IMI		/* iminfo			*/
#undef CONFIG_CMD_IMLS		/* List all found images	*/
#undef CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
#undef CONFIG_CMD_NFS		/* NFS support			*/

#define CONFIG_SYS_NO_FLASH
#define CONFIG_HARD_I2C			1
#define CONFIG_SYS_I2C_SPEED		100000
#define CONFIG_SYS_I2C_SLAVE		1
#define CONFIG_SYS_I2C_BUS		0
#define CONFIG_SYS_I2C_BUS_SELECT	1
#define CONFIG_DRIVER_OMAP34XX_I2C	1

/*
 * TWL4030
 */
#define CONFIG_TWL4030_POWER		1
#define CONFIG_TWL4030_LED		1

/*
 * Board NAND Info.
 */
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
							/* to access nand */
#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
							/* to access nand */
							/* at CS0 */
#define GPMC_NAND_ECC_LP_x16_LAYOUT	1

#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND */
						/* devices */
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV		"nand0"
/* start of jffs2 partition */
#define CONFIG_JFFS2_PART_OFFSET	0x680000
#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* size of jffs2 */
							/* partition */

/* Environment information */
#define CONFIG_BOOTDELAY		1

#define CONFIG_EXTRA_ENV_SETTINGS \
	"loadaddr=0x82000000\0" \
	"console=ttyS0,115200n8\0" \
	"videospec=omapfb:vram:2M,vram:4M\0" \
	"mmcargs=setenv bootargs console=${console} " \
		"video=${videospec} " \
		"root=/dev/mmcblk0p2 rw " \
		"rootfstype=ext3 rootwait\0" \
	"nandargs=setenv bootargs console=${console} " \
		"video=${videospec} " \
		"root=/dev/mtdblock4 rw " \
		"rootfstype=jffs2\0" \
	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
	"bootscript=echo Running bootscript from mmc ...; " \
		"source ${loadaddr}\0" \
	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
	"mmcboot=echo Booting from mmc ...; " \
		"run mmcargs; " \
		"bootm ${loadaddr}\0" \
	"nandboot=echo Booting from nand ...; " \
		"run nandargs; " \
		"nand read ${loadaddr} 280000 400000; " \
		"bootm ${loadaddr}\0" \

#define CONFIG_BOOTCOMMAND \
	"if mmc init; then " \
		"if run loadbootscript; then " \
			"run bootscript; " \
		"else " \
			"if run loaduimage; then " \
				"run mmcboot; " \
			"else run nandboot; " \
			"fi; " \
		"fi; " \
	"else run nandboot; fi"

#define CONFIG_AUTO_COMPLETE	1
/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
#define CONFIG_SYS_PROMPT		"Pandora # "
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16	/* max number of command */
						/* args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
					0x01F00000) /* 31MB */

#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
								/* address */

/*
 * OMAP3 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ			1000

/*-----------------------------------------------------------------------
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ	(4 << 10)	/* IRQ stack 4 KiB */
#define CONFIG_STACKSIZE_FIQ	(4 << 10)	/* FIQ stack 4 KiB */
#endif

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

/* SDRAM Bank Allocation method */
#define SDRC_R_B_C		1

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */

/* **** PISMO SUPPORT *** */

/* Configure the PISMO */
#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M

#define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors on */
						/* one chip */
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */

#define CONFIG_SYS_FLASH_BASE		boot_flash_base

/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP

#define CONFIG_ENV_IS_IN_NAND		1
#define ONENAND_ENV_OFFSET		0x240000 /* environment starts here */
#define SMNAND_ENV_OFFSET		0x240000 /* environment starts here */

#define CONFIG_SYS_ENV_SECT_SIZE	boot_flash_sec
#define CONFIG_ENV_OFFSET		boot_flash_off
#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET

/*-----------------------------------------------------------------------
 * CFI FLASH driver setup
 */
/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)

/* Flash banks JFFS2 should use */
#define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
					CONFIG_SYS_MAX_NAND_DEVICE)
#define CONFIG_SYS_JFFS2_MEM_NAND
/* use flash_info[2] */
#define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
#define CONFIG_SYS_JFFS2_NUM_BANKS	1

#ifndef __ASSEMBLY__
extern unsigned int boot_flash_base;
extern volatile unsigned int boot_flash_env_addr;
extern unsigned int boot_flash_off;
extern unsigned int boot_flash_sec;
extern unsigned int boot_flash_type;
#endif

#endif				/* __CONFIG_H */
Commit	Line	Data
2be2c6cc DB	1	/*
	2	* (C) Copyright 2008
	3	* Grazvydas Ignotas <notasas@gmail.com>
	4	*
	5	* Configuration settings for the OMAP3 Pandora.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
	22
	23	#ifndef __CONFIG_H
	24	#define __CONFIG_H
2be2c6cc DB	25
	26	/*
	27	* High Level Configuration Options
	28	*/
f56348af	29	#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
2be2c6cc DB	30	#define CONFIG_OMAP 1 /* in a TI OMAP core */
	31	#define CONFIG_OMAP34XX 1 /* which is a 34XX */
	32	#define CONFIG_OMAP3430 1 /* which is in a 3430 */
	33	#define CONFIG_OMAP3_PANDORA 1 /* working with pandora */
	34
cae377b5 VH	35	#define CONFIG_SDRC /* The chip has SDRC controller */
cae377b5 VH	36
2be2c6cc DB	37	#include <asm/arch/cpu.h> /* get chip and board defs */
	38	#include <asm/arch/omap3.h>
	39
6a6b62e3 SP	40	/*
	41	* Display CPU and Board information
	42	*/
	43	#define CONFIG_DISPLAY_CPUINFO 1
	44	#define CONFIG_DISPLAY_BOARDINFO 1
	45
2be2c6cc DB	46	/* Clock Defines */
	47	#define V_OSCK 26000000 /* Clock output from T2 */
	48	#define V_SCLK (V_OSCK >> 1)
	49
	50	#undef CONFIG_USE_IRQ /* no support for IRQs */
	51	#define CONFIG_MISC_INIT_R
	52
	53	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	54	#define CONFIG_SETUP_MEMORY_TAGS 1
	55	#define CONFIG_INITRD_TAG 1
	56	#define CONFIG_REVISION_TAG 1
	57
	58	/*
	59	* Size of malloc() pool
	60	*/
9c44ddcc	61	#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
2be2c6cc	62	/* Sector */
9c44ddcc	63	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
2be2c6cc DB	64	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
	65	/* initial data */
	66
	67	/*
	68	* Hardware drivers
	69	*/
	70
	71	/*
	72	* NS16550 Configuration
	73	*/
	74	#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
	75
	76	#define CONFIG_SYS_NS16550
	77	#define CONFIG_SYS_NS16550_SERIAL
	78	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	79	#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
	80
	81	/*
	82	* select serial console configuration
	83	*/
	84	#define CONFIG_CONS_INDEX 3
	85	#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
	86	#define CONFIG_SERIAL3 3
	87
	88	/* allow to overwrite serial and ethaddr */
	89	#define CONFIG_ENV_OVERWRITE
	90	#define CONFIG_BAUDRATE 115200
	91	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
	92	115200}
	93	#define CONFIG_MMC 1
	94	#define CONFIG_OMAP3_MMC 1
	95	#define CONFIG_DOS_PARTITION 1
	96
30563a04 NM	97	/* DDR - I use Micron DDR */
	98	#define CONFIG_OMAP3_MICRON_DDR 1
	99
2be2c6cc DB	100	/* commands to include */
	101	#include <config_cmd_default.h>
	102
	103	#define CONFIG_CMD_EXT2 /* EXT2 Support */
	104	#define CONFIG_CMD_FAT /* FAT support */
	105	#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
	106
	107	#define CONFIG_CMD_I2C /* I2C serial bus support */
	108	#define CONFIG_CMD_MMC /* MMC support */
	109	#define CONFIG_CMD_NAND /* NAND support */
	110
	111	#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
	112	#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
	113	#undef CONFIG_CMD_IMI /* iminfo */
	114	#undef CONFIG_CMD_IMLS /* List all found images */
	115	#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
	116	#undef CONFIG_CMD_NFS /* NFS support */
	117
	118	#define CONFIG_SYS_NO_FLASH
0297ec7e	119	#define CONFIG_HARD_I2C 1
2be2c6cc DB	120	#define CONFIG_SYS_I2C_SPEED 100000
	121	#define CONFIG_SYS_I2C_SLAVE 1
	122	#define CONFIG_SYS_I2C_BUS 0
	123	#define CONFIG_SYS_I2C_BUS_SELECT 1
	124	#define CONFIG_DRIVER_OMAP34XX_I2C 1
	125
2c155130 TR	126	/*
	127	* TWL4030
	128	*/
	129	#define CONFIG_TWL4030_POWER 1
	130	#define CONFIG_TWL4030_LED 1
	131
2be2c6cc DB	132	/*
	133	* Board NAND Info.
	134	*/
	135	#define CONFIG_NAND_OMAP_GPMC
	136	#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
	137	/* to access nand */
	138	#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
	139	/* to access nand */
	140	/* at CS0 */
	141	#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
	142
	143	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
	144	/* devices */
2be2c6cc DB	145	#define CONFIG_JFFS2_NAND
	146	/* nand device jffs2 lives on */
	147	#define CONFIG_JFFS2_DEV "nand0"
	148	/* start of jffs2 partition */
	149	#define CONFIG_JFFS2_PART_OFFSET 0x680000
	150	#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
	151	/* partition */
	152
	153	/* Environment information */
	154	#define CONFIG_BOOTDELAY 1
	155
	156	#define CONFIG_EXTRA_ENV_SETTINGS \
	157	"loadaddr=0x82000000\0" \
	158	"console=ttyS0,115200n8\0" \
	159	"videospec=omapfb:vram:2M,vram:4M\0" \
	160	"mmcargs=setenv bootargs console=${console} " \
	161	"video=${videospec} " \
	162	"root=/dev/mmcblk0p2 rw " \
	163	"rootfstype=ext3 rootwait\0" \
	164	"nandargs=setenv bootargs console=${console} " \
	165	"video=${videospec} " \
	166	"root=/dev/mtdblock4 rw " \
	167	"rootfstype=jffs2\0" \
	168	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
	169	"bootscript=echo Running bootscript from mmc ...; " \
74de7aef	170	"source ${loadaddr}\0" \
2be2c6cc DB	171	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
	172	"mmcboot=echo Booting from mmc ...; " \
	173	"run mmcargs; " \
	174	"bootm ${loadaddr}\0" \
	175	"nandboot=echo Booting from nand ...; " \
	176	"run nandargs; " \
	177	"nand read ${loadaddr} 280000 400000; " \
	178	"bootm ${loadaddr}\0" \
	179
	180	#define CONFIG_BOOTCOMMAND \
a85693b3	181	"if mmc init; then " \
2be2c6cc DB	182	"if run loadbootscript; then " \
	183	"run bootscript; " \
	184	"else " \
	185	"if run loaduimage; then " \
	186	"run mmcboot; " \
	187	"else run nandboot; " \
	188	"fi; " \
	189	"fi; " \
	190	"else run nandboot; fi"
	191
	192	#define CONFIG_AUTO_COMPLETE 1
	193	/*
	194	* Miscellaneous configurable options
	195	*/
2be2c6cc DB	196	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	197	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
	198	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
1270ec13	199	#define CONFIG_SYS_PROMPT "Pandora # "
2be2c6cc DB	200	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	201	/* Print Buffer Size */
	202	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	203	sizeof(CONFIG_SYS_PROMPT) + 16)
	204	#define CONFIG_SYS_MAXARGS 16 /* max number of command */
	205	/* args */
	206	/* Boot Argument Buffer Size */
	207	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	208	/* memtest works on */
	209	#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
	210	#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
	211	0x01F00000) /* 31MB */
	212
2be2c6cc DB	213	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
	214	/* address */
	215
	216	/*
d3a513c2 MP	217	* OMAP3 has 12 GP timers, they can be driven by the system clock
	218	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
	219	* This rate is divided by a local divisor.
2be2c6cc	220	*/
d3a513c2 MP	221	#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
	222	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
	223	#define CONFIG_SYS_HZ 1000
2be2c6cc DB	224
	225	/*-----------------------------------------------------------------------
	226	* Stack sizes
	227	*
	228	* The stack sizes are set up in start.S using the settings below
	229	*/
9c44ddcc	230	#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
2be2c6cc	231	#ifdef CONFIG_USE_IRQ
9c44ddcc SP	232	#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
9c44ddcc SP	233	#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
2be2c6cc DB	234	#endif
	235
	236	/*-----------------------------------------------------------------------
	237	* Physical Memory Map
	238	*/
	239	#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
	240	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
9c44ddcc	241	#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
2be2c6cc DB	242	#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
	243
	244	/* SDRAM Bank Allocation method */
	245	#define SDRC_R_B_C 1
	246
	247	/*-----------------------------------------------------------------------
	248	* FLASH and environment organization
	249	*/
	250
	251	/* ** PISMO SUPPORT * */
	252
	253	/* Configure the PISMO */
	254	#define PISMO1_NAND_SIZE GPMC_SIZE_128M
	255	#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
	256
	257	#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */
	258	/* one chip */
	259	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
9c44ddcc	260	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
2be2c6cc DB	261
	262	#define CONFIG_SYS_FLASH_BASE boot_flash_base
	263
	264	/* Monitor at start of flash */
	265	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	266	#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
	267
	268	#define CONFIG_ENV_IS_IN_NAND 1
	269	#define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */
	270	#define SMNAND_ENV_OFFSET 0x240000 /* environment starts here */
	271
	272	#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
	273	#define CONFIG_ENV_OFFSET boot_flash_off
	274	#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
	275
	276	/*-----------------------------------------------------------------------
	277	* CFI FLASH driver setup
	278	*/
	279	/* timeout values are in ticks */
	280	#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
	281	#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
	282
	283	/* Flash banks JFFS2 should use */
	284	#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
	285	CONFIG_SYS_MAX_NAND_DEVICE)
	286	#define CONFIG_SYS_JFFS2_MEM_NAND
	287	/* use flash_info[2] */
	288	#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
	289	#define CONFIG_SYS_JFFS2_NUM_BANKS 1
	290
	291	#ifndef __ASSEMBLY__
2be2c6cc DB	292	extern unsigned int boot_flash_base;
	293	extern volatile unsigned int boot_flash_env_addr;
	294	extern unsigned int boot_flash_off;
	295	extern unsigned int boot_flash_sec;
	296	extern unsigned int boot_flash_type;
	297	#endif
	298
2be2c6cc	299	#endif /* __CONFIG_H */