[people/ms/u-boot.git] / include / configs / omap3_sdp3430.h

/*
 * (C) Copyright 2006-2009
 * Texas Instruments Incorporated.
 * Richard Woodruff <r-woodruff2@ti.com>
 * Syed Mohammed Khasim <x0khasim@ti.com>
 * Nishanth Menon <nm@ti.com>
 *
 * Configuration settings for the 3430 TI SDP3430 board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* TODO: REMOVE THE FOLLOWING
 * Retained the following till size.h is removed in u-boot
 */
#include <asm/sizes.h>
/*
 * High Level Configuration Options
 */
#define CONFIG_ARMCORTEXA8	1	/* This is an ARM V7 CPU core */
#define CONFIG_OMAP		1	/* in a TI OMAP core */
#define CONFIG_OMAP34XX		1	/* which is a 34XX */
#define CONFIG_OMAP3430		1	/* which is in a 3430 */
#define CONFIG_OMAP3_3430SDP	1	/* working with SDP Rev2 */

#define CONFIG_SDRC	/* The chip has SDRC controller */

#include <asm/arch/cpu.h>		/* get chip and board defs */
#include <asm/arch/omap3.h>

/*
 * NOTE:  these #defines presume standard SDP jumper settings.
 * In particular:
 *  - 26 MHz clock (not 19.2 or 38.4 MHz)
 *  - Boot from 128MB NOR, not NAND or OneNAND
 *
 * At this writing, OMAP3 U-Boot support doesn't permit concurrent
 * support for all the flash types the board supports.
 */
#define CONFIG_DISPLAY_CPUINFO		1
#define CONFIG_DISPLAY_BOARDINFO	1

/* Clock Defines */
#define V_OSCK			26000000	/* Clock output from T2 */
#define V_SCLK			(V_OSCK >> 1)

#undef CONFIG_USE_IRQ			/* no support for IRQs */
#define CONFIG_MISC_INIT_R

#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_INITRD_TAG		1
#define CONFIG_REVISION_TAG		1

/*
 * Size of malloc() pool
 * Total Size Environment - 256k
 * Malloc - add 256k
 */
#define CONFIG_ENV_SIZE			(256 << 10)
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (256 << 10))
#define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for */
						/* initial data */

/*--------------------------------------------------------------------------*/

/*
 * Hardware drivers
 */

/*
 * TWL4030
 */
#define CONFIG_TWL4030_POWER		1

/*
 * serial port - NS16550 compatible
 */
#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */

#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK

/* Original SDP u-boot used UART1 and thus J8 (innermost); that can be
 * swapped with UART2 via jumpering.  Downsides of using J8:  it doesn't
 * support UART boot (that's only for UART3); it prevents sharing a Linux
 * kernel (LL_DEBUG_UART3) or filesystem (getty ttyS2) with most boards.
 *
 * UART boot uses UART3 on J9, and the SDP user's guide says to use
 * that for console.  Downsides of using J9:  you can't use IRDA too;
 * since UART3 isn't in the CORE power domain, it may be a bit less
 * usable in certain PM-sensitive debug scenarios.
 */
#undef CONSOLE_J9			/* else J8/UART1 (innermost) */

#ifdef CONSOLE_J9
#define CONFIG_CONS_INDEX		3
#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
#define CONFIG_SERIAL3			3	/* UART3 */
#else
#define CONFIG_CONS_INDEX		1
#define CONFIG_SYS_NS16550_COM1		OMAP34XX_UART1
#define CONFIG_SERIAL1			1	/* UART1 */
#endif

#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
					115200}

/*
 * I2C for power management setup
 */
#define CONFIG_HARD_I2C			1
#define CONFIG_SYS_I2C_SPEED		100000
#define CONFIG_SYS_I2C_SLAVE		1
#define CONFIG_SYS_I2C_BUS		0
#define CONFIG_SYS_I2C_BUS_SELECT	1
#define CONFIG_DRIVER_OMAP34XX_I2C	1

/* DDR - I use Infineon DDR */
#define CONFIG_OMAP3_INFINEON_DDR	1

/* OMITTED:  single 1 Gbit MT29F1G NAND flash */

/*
 * NOR boot support - single 1 Gbit PF48F6000M0 Strataflash
 */
#define CONFIG_SYS_FLASH_BASE		0x10000000
#define CONFIG_FLASH_CFI_DRIVER		1	/* Use drivers/cfi_flash.c */
#define CONFIG_SYS_FLASH_CFI		1	/* use CFI geometry data */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* ~10x faster writes */
#define CONFIG_SYS_FLASH_PROTECTION	1	/* hardware sector protection */
#define CONFIG_SYS_FLASH_EMPTY_INFO	1	/* flinfo 'E' for empty */
#define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE}
#define CONFIG_SYS_MAX_FLASH_BANKS      1	/* max number of flash banks */

#define CONFIG_SYS_FLASH_CFI_WIDTH	2
#define PHYS_FLASH_SIZE			(128 << 20)
#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max sectors on one chip */

/* timeout values are in milliseconds */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)

/* OMITTED:  single 2 Gbit KFM2G16 OneNAND flash */

#define CONFIG_ENV_IS_IN_FLASH		1
#define CONFIG_SYS_ENV_SECT_SIZE	(256 << 10)
#define CONFIG_ENV_OFFSET		CONFIG_SYS_ENV_SECT_SIZE
#define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_ENV_SECT_SIZE)
/*--------------------------------------------------------------------------*/

/* commands to include */
#include <config_cmd_default.h>

/* Enabled commands */
#define CONFIG_CMD_DHCP		/* DHCP Support			*/
#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
#define CONFIG_CMD_FAT		/* FAT support			*/
#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
#define CONFIG_CMD_MMC		/* MMC support			*/
#define CONFIG_CMD_NET

/* Disabled commands */
#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
#undef CONFIG_CMD_IMLS		/* List all found images	*/

/*--------------------------------------------------------------------------*/
/*
 * MMC boot support
 */

#if defined(CONFIG_CMD_MMC)
#define CONFIG_MMC			1
#define CONFIG_OMAP3_MMC		1
#define CONFIG_DOS_PARTITION		1
#endif

/*----------------------------------------------------------------------------
 * SMSC9115 Ethernet from SMSC9118 family
 *----------------------------------------------------------------------------
 */
#if defined(CONFIG_CMD_NET)

#define CONFIG_NET_MULTI
#define CONFIG_LAN91C96
#define CONFIG_LAN91C96_BASE	DEBUG_BASE
#define CONFIG_LAN91C96_EXT_PHY

#define CONFIG_BOOTP_SEND_HOSTNAME
/*
 * BOOTP fields
 */
#define CONFIG_BOOTP_SUBNETMASK		0x00000001
#define CONFIG_BOOTP_GATEWAY		0x00000002
#define CONFIG_BOOTP_HOSTNAME		0x00000004
#define CONFIG_BOOTP_BOOTPATH		0x00000010
#endif /* (CONFIG_CMD_NET) */

/*
 * Environment setup
 *
 * Default boot order:  mmc bootscript, MMC uImage, NOR image.
 * Network booting environment must be configured at site.
 */

/* allow overwriting serial config and ethaddr */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_EXTRA_ENV_SETTINGS \
	"loadaddr=0x82000000\0" \
	"console=ttyS0,115200n8\0" \
	"mmcargs=setenv bootargs console=${console} " \
		"root=/dev/mmcblk0p2 rw " \
		"rootfstype=ext3 rootwait\0" \
	"norargs=setenv bootargs console=${console} " \
		"root=/dev/mtdblock3 rw " \
		"rootfstype=jffs2\0" \
	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
	"bootscript=echo Running bootscript from MMC/SD ...; " \
		"autoscr ${loadaddr}\0" \
	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
	"mmcboot=echo Booting from MMC/SD ...; " \
		"run mmcargs; " \
		"bootm ${loadaddr}\0" \
	"norboot=echo Booting from NOR ...; " \
		"run norargs; " \
		"bootm 0x80000\0" \

#define CONFIG_BOOTCOMMAND \
	"if mmcinit; then " \
		"if run loadbootscript; then " \
			"run bootscript; " \
		"else " \
			"if run loaduimage; then " \
				"run mmcboot; " \
			"else run norboot; " \
			"fi; " \
		"fi; " \
	"else run norboot; fi"

#define CONFIG_AUTO_COMPLETE		1

/*--------------------------------------------------------------------------*/

/*
 * Miscellaneous configurable options
 */

#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
#define CONFIG_SYS_PROMPT		"OMAP34XX SDP # "
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)

/* SDRAM Test range - start at 16 meg boundary -ends at 32Meg -
 * a basic sanity check ONLY
 * IF you would like to increase coverage, increase the end address
 * or run the test with custom options
 */
#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0 + 0x01000000)
#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + (32 << 20))

/* Default load address */
#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)

/*--------------------------------------------------------------------------*/

/*
 * 3430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
 * 32KHz clk, or from external sig. This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ			1000

/*
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE	(128 << 10) /* Regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ	(4 << 10) /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ	(4 << 10) /* FIQ stack */
#endif

/*
 * SDRAM Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_1_SIZE	(32 << 20) /* at least 32 meg */
#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

/* SDRAM Bank Allocation method */
#define SDRC_R_B_C		1

/*--------------------------------------------------------------------------*/

/*
 * NOR FLASH usage ... default nCS0:
 *  - one 256KB sector for U-Boot
 *  - one 256KB sector for its parameters (not all used)
 *  - eight sectors (2 MB) for kernel
 *  - rest for JFFS2
 */

/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)

#define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
#define CONFIG_SYS_JFFS2_NUM_BANKS	1

/*
 * NAND FLASH usage ... default nCS1:
 *  - four 128KB sectors for X-Loader
 *  - four 128KB sectors for U-Boot
 *  - two 128KB sector for its parameters
 *  - 32 sectors (4 MB) for kernel
 *  - rest for filesystem
 */

/*
 * OneNAND FLASH usage ... default nCS2:
 *  - four 128KB sectors for X-Loader
 *  - two 128KB sectors for U-Boot
 *  - one 128KB sector for its parameters
 *  - sixteen sectors (2 MB) for kernel
 *  - rest for filesystem
 */

/*--------------------------------------------------------------------------*/

#ifndef __ASSEMBLY__
extern unsigned int boot_flash_base;
extern volatile unsigned int boot_flash_env_addr;
extern unsigned int boot_flash_off;
extern unsigned int boot_flash_sec;
extern unsigned int boot_flash_type;
#endif

#endif				/* __CONFIG_H */
Commit	Line	Data
e63e5904 TR	1	/*
	2	* (C) Copyright 2006-2009
	3	* Texas Instruments Incorporated.
	4	* Richard Woodruff <r-woodruff2@ti.com>
	5	* Syed Mohammed Khasim <x0khasim@ti.com>
	6	* Nishanth Menon <nm@ti.com>
	7	*
	8	* Configuration settings for the 3430 TI SDP3430 board.
	9	*
	10	* See file CREDITS for list of people who contributed to this
	11	* project.
	12	*
	13	* This program is free software; you can redistribute it and/or
	14	* modify it under the terms of the GNU General Public License as
	15	* published by the Free Software Foundation; either version 2 of
	16	* the License, or (at your option) any later version.
	17	*
	18	* This program is distributed in the hope that it will be useful,
	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	21	* GNU General Public License for more details.
	22	*
	23	* You should have received a copy of the GNU General Public License
	24	* along with this program; if not, write to the Free Software
	25	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	26	* MA 02111-1307 USA
	27	*/
	28
	29	#ifndef __CONFIG_H
	30	#define __CONFIG_H
	31
	32	/* TODO: REMOVE THE FOLLOWING
	33	* Retained the following till size.h is removed in u-boot
	34	*/
	35	#include <asm/sizes.h>
	36	/*
	37	* High Level Configuration Options
	38	*/
	39	#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
	40	#define CONFIG_OMAP 1 /* in a TI OMAP core */
	41	#define CONFIG_OMAP34XX 1 /* which is a 34XX */
	42	#define CONFIG_OMAP3430 1 /* which is in a 3430 */
	43	#define CONFIG_OMAP3_3430SDP 1 /* working with SDP Rev2 */
	44
cae377b5 VH	45	#define CONFIG_SDRC /* The chip has SDRC controller */
cae377b5 VH	46
e63e5904 TR	47	#include <asm/arch/cpu.h> /* get chip and board defs */
	48	#include <asm/arch/omap3.h>
	49
	50	/*
	51	* NOTE: these #defines presume standard SDP jumper settings.
	52	* In particular:
	53	* - 26 MHz clock (not 19.2 or 38.4 MHz)
	54	* - Boot from 128MB NOR, not NAND or OneNAND
	55	*
	56	* At this writing, OMAP3 U-Boot support doesn't permit concurrent
	57	* support for all the flash types the board supports.
	58	*/
	59	#define CONFIG_DISPLAY_CPUINFO 1
	60	#define CONFIG_DISPLAY_BOARDINFO 1
	61
	62	/* Clock Defines */
	63	#define V_OSCK 26000000 /* Clock output from T2 */
	64	#define V_SCLK (V_OSCK >> 1)
	65
	66	#undef CONFIG_USE_IRQ /* no support for IRQs */
	67	#define CONFIG_MISC_INIT_R
	68
	69	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	70	#define CONFIG_SETUP_MEMORY_TAGS 1
	71	#define CONFIG_INITRD_TAG 1
	72	#define CONFIG_REVISION_TAG 1
	73
	74	/*
	75	* Size of malloc() pool
	76	* Total Size Environment - 256k
	77	* Malloc - add 256k
	78	*/
	79	#define CONFIG_ENV_SIZE (256 << 10)
	80	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10))
	81	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
	82	/* initial data */
	83
	84	/--------------------------------------------------------------------------/
	85
	86	/*
	87	* Hardware drivers
	88	*/
	89
	90	/*
	91	* TWL4030
	92	*/
	93	#define CONFIG_TWL4030_POWER 1
	94
	95	/*
	96	* serial port - NS16550 compatible
	97	*/
	98	#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
	99
	100	#define CONFIG_SYS_NS16550
	101	#define CONFIG_SYS_NS16550_SERIAL
	102	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	103	#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
	104
	105	/* Original SDP u-boot used UART1 and thus J8 (innermost); that can be
	106	* swapped with UART2 via jumpering. Downsides of using J8: it doesn't
	107	* support UART boot (that's only for UART3); it prevents sharing a Linux
	108	* kernel (LL_DEBUG_UART3) or filesystem (getty ttyS2) with most boards.
	109	*
	110	* UART boot uses UART3 on J9, and the SDP user's guide says to use
111	* that for console. Downsides of using J9: you can't use IRDA too;
112	* since UART3 isn't in the CORE power domain, it may be a bit less
113	* usable in certain PM-sensitive debug scenarios.
114	*/
115	#undef CONSOLE_J9 /* else J8/UART1 (innermost) */
116
117	#ifdef CONSOLE_J9
118	#define CONFIG_CONS_INDEX 3
119	#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
120	#define CONFIG_SERIAL3 3 /* UART3 */
121	#else
122	#define CONFIG_CONS_INDEX 1
123	#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
124	#define CONFIG_SERIAL1 1 /* UART1 */
125	#endif
126
127	#define CONFIG_ENV_OVERWRITE
128	#define CONFIG_BAUDRATE 115200
129	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
130	115200}
131
132	/*
133	* I2C for power management setup
134	*/
135	#define CONFIG_HARD_I2C 1
136	#define CONFIG_SYS_I2C_SPEED 100000
137	#define CONFIG_SYS_I2C_SLAVE 1
138	#define CONFIG_SYS_I2C_BUS 0
139	#define CONFIG_SYS_I2C_BUS_SELECT 1
140	#define CONFIG_DRIVER_OMAP34XX_I2C 1
141
30563a04 NM	142	/* DDR - I use Infineon DDR */
	143	#define CONFIG_OMAP3_INFINEON_DDR 1
	144
e63e5904 TR	145	/* OMITTED: single 1 Gbit MT29F1G NAND flash */
	146
	147	/*
	148	* NOR boot support - single 1 Gbit PF48F6000M0 Strataflash
	149	*/
	150	#define CONFIG_SYS_FLASH_BASE 0x10000000
	151	#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
	152	#define CONFIG_SYS_FLASH_CFI 1 /* use CFI geometry data */
	153	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* ~10x faster writes */
	154	#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware sector protection */
	155	#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* flinfo 'E' for empty */
	156	#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
	157	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
	158
	159	#define CONFIG_SYS_FLASH_CFI_WIDTH 2
	160	#define PHYS_FLASH_SIZE (128 << 20)
	161	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors on one chip */
	162
	163	/* timeout values are in milliseconds */
	164	#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
	165	#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
	166
	167	/* OMITTED: single 2 Gbit KFM2G16 OneNAND flash */
	168
	169	#define CONFIG_ENV_IS_IN_FLASH 1
	170	#define CONFIG_SYS_ENV_SECT_SIZE (256 << 10)
	171	#define CONFIG_ENV_OFFSET CONFIG_SYS_ENV_SECT_SIZE
	172	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_ENV_SECT_SIZE)
	173	/--------------------------------------------------------------------------/
	174
	175	/* commands to include */
	176	#include <config_cmd_default.h>
	177
	178	/* Enabled commands */
	179	#define CONFIG_CMD_DHCP /* DHCP Support */
	180	#define CONFIG_CMD_EXT2 /* EXT2 Support */
	181	#define CONFIG_CMD_FAT /* FAT support */
	182	#define CONFIG_CMD_I2C /* I2C serial bus support */
	183	#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
	184	#define CONFIG_CMD_MMC /* MMC support */
	185	#define CONFIG_CMD_NET
	186
	187	/* Disabled commands */
	188	#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
	189	#undef CONFIG_CMD_IMLS /* List all found images */
	190
	191	/--------------------------------------------------------------------------/
	192	/*
	193	* MMC boot support
	194	*/
	195
	196	#if defined(CONFIG_CMD_MMC)
	197	#define CONFIG_MMC 1
	198	#define CONFIG_OMAP3_MMC 1
	199	#define CONFIG_DOS_PARTITION 1
	200	#endif
	201
	202	/*----------------------------------------------------------------------------
	203	* SMSC9115 Ethernet from SMSC9118 family
	204	*----------------------------------------------------------------------------
	205	*/
	206	#if defined(CONFIG_CMD_NET)
	207
a1725999 NM	208	#define CONFIG_NET_MULTI
a1725999 NM	209	#define CONFIG_LAN91C96
e63e5904 TR	210	#define CONFIG_LAN91C96_BASE DEBUG_BASE
	211	#define CONFIG_LAN91C96_EXT_PHY
	212
	213	#define CONFIG_BOOTP_SEND_HOSTNAME
	214	/*
	215	* BOOTP fields
	216	*/
	217	#define CONFIG_BOOTP_SUBNETMASK 0x00000001
	218	#define CONFIG_BOOTP_GATEWAY 0x00000002
	219	#define CONFIG_BOOTP_HOSTNAME 0x00000004
	220	#define CONFIG_BOOTP_BOOTPATH 0x00000010
	221	#endif /* (CONFIG_CMD_NET) */
	222
	223	/*
	224	* Environment setup
	225	*
	226	* Default boot order: mmc bootscript, MMC uImage, NOR image.
	227	* Network booting environment must be configured at site.
	228	*/
	229
	230	/* allow overwriting serial config and ethaddr */
	231	#define CONFIG_ENV_OVERWRITE
	232
	233	#define CONFIG_EXTRA_ENV_SETTINGS \
	234	"loadaddr=0x82000000\0" \
	235	"console=ttyS0,115200n8\0" \
	236	"mmcargs=setenv bootargs console=${console} " \
	237	"root=/dev/mmcblk0p2 rw " \
	238	"rootfstype=ext3 rootwait\0" \
	239	"norargs=setenv bootargs console=${console} " \
	240	"root=/dev/mtdblock3 rw " \
	241	"rootfstype=jffs2\0" \
	242	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
	243	"bootscript=echo Running bootscript from MMC/SD ...; " \
	244	"autoscr ${loadaddr}\0" \
	245	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
	246	"mmcboot=echo Booting from MMC/SD ...; " \
	247	"run mmcargs; " \
	248	"bootm ${loadaddr}\0" \
	249	"norboot=echo Booting from NOR ...; " \
	250	"run norargs; " \
	251	"bootm 0x80000\0" \
	252
	253	#define CONFIG_BOOTCOMMAND \
	254	"if mmcinit; then " \
	255	"if run loadbootscript; then " \
	256	"run bootscript; " \
	257	"else " \
	258	"if run loaduimage; then " \
	259	"run mmcboot; " \
	260	"else run norboot; " \
	261	"fi; " \
	262	"fi; " \
	263	"else run norboot; fi"
	264
	265	#define CONFIG_AUTO_COMPLETE 1
	266
	267	/--------------------------------------------------------------------------/
	268
	269	/*
	270	* Miscellaneous configurable options
	271	*/
e63e5904 TR	272
	273	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	274	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
	275	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
1270ec13	276	#define CONFIG_SYS_PROMPT "OMAP34XX SDP # "
e63e5904 TR	277	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	278	/* Print Buffer Size */
	279	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	280	sizeof(CONFIG_SYS_PROMPT) + 16)
	281	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	282	/* Boot Argument Buffer Size */
	283	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	284
	285	/* SDRAM Test range - start at 16 meg boundary -ends at 32Meg -
	286	* a basic sanity check ONLY
	287	* IF you would like to increase coverage, increase the end address
	288	* or run the test with custom options
	289	*/
	290	#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x01000000)
	291	#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + (32 << 20))
	292
	293	/* Default load address */
	294	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
	295
	296	/--------------------------------------------------------------------------/
	297
	298	/*
	299	* 3430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
	300	* 32KHz clk, or from external sig. This rate is divided by a local divisor.
	301	*/
	302	#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
	303	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
	304	#define CONFIG_SYS_HZ 1000
	305
	306	/*
	307	* Stack sizes
	308	*
	309	* The stack sizes are set up in start.S using the settings below
	310	*/
	311	#define CONFIG_STACKSIZE (128 << 10) /* Regular stack */
	312	#ifdef CONFIG_USE_IRQ
	313	#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack */
	314	#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack */
	315	#endif
	316
	317	/*
	318	* SDRAM Memory Map
	319	*/
	320	#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
	321	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
	322	#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 meg */
	323	#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
	324
	325	/* SDRAM Bank Allocation method */
	326	#define SDRC_R_B_C 1
	327
	328	/--------------------------------------------------------------------------/
	329
	330	/*
	331	* NOR FLASH usage ... default nCS0:
	332	* - one 256KB sector for U-Boot
	333	* - one 256KB sector for its parameters (not all used)
	334	* - eight sectors (2 MB) for kernel
	335	* - rest for JFFS2
	336	*/
	337
	338	/* Monitor at start of flash */
	339	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	340	#define CONFIG_SYS_MONITOR_LEN (256 << 10)
341
342	#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
343	#define CONFIG_SYS_JFFS2_NUM_BANKS 1
344
345	/*
346	* NAND FLASH usage ... default nCS1:
347	* - four 128KB sectors for X-Loader
348	* - four 128KB sectors for U-Boot
349	* - two 128KB sector for its parameters
350	* - 32 sectors (4 MB) for kernel
351	* - rest for filesystem
352	*/
353
354	/*
355	* OneNAND FLASH usage ... default nCS2:
356	* - four 128KB sectors for X-Loader
357	* - two 128KB sectors for U-Boot
358	* - one 128KB sector for its parameters
359	* - sixteen sectors (2 MB) for kernel
360	* - rest for filesystem
361	*/
362
363	/--------------------------------------------------------------------------/
364
365	#ifndef __ASSEMBLY__
e63e5904 TR	366	extern unsigned int boot_flash_base;
	367	extern volatile unsigned int boot_flash_env_addr;
	368	extern unsigned int boot_flash_off;
	369	extern unsigned int boot_flash_sec;
	370	extern unsigned int boot_flash_type;
	371	#endif
	372
	373	#endif /* __CONFIG_H */