[thirdparty/u-boot.git] / include / configs / omap3_sdp3430.h

/*
 * (C) Copyright 2006-2009
 * Texas Instruments Incorporated.
 * Richard Woodruff <r-woodruff2@ti.com>
 * Syed Mohammed Khasim <x0khasim@ti.com>
 * Nishanth Menon <nm@ti.com>
 *
 * Configuration settings for the 3430 TI SDP3430 board.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* TODO: REMOVE THE FOLLOWING
 * Retained the following till size.h is removed in u-boot
 */
#include <linux/sizes.h>
/*
 * High Level Configuration Options
 */
#define CONFIG_OMAP		1	/* in a TI OMAP core */
#define CONFIG_OMAP3_3430SDP	1	/* working with SDP Rev2 */
#define CONFIG_OMAP_COMMON
/* Common ARM Erratas */
#define CONFIG_ARM_ERRATA_454179
#define CONFIG_ARM_ERRATA_430973
#define CONFIG_ARM_ERRATA_621766

#define CONFIG_SDRC	/* The chip has SDRC controller */

#include <asm/arch/cpu.h>		/* get chip and board defs */
#include <asm/arch/omap.h>

/*
 * NOTE:  these #defines presume standard SDP jumper settings.
 * In particular:
 *  - 26 MHz clock (not 19.2 or 38.4 MHz)
 *  - Boot from 128MB NOR, not NAND or OneNAND
 *
 * At this writing, OMAP3 U-Boot support doesn't permit concurrent
 * support for all the flash types the board supports.
 */
#define CONFIG_DISPLAY_CPUINFO		1
#define CONFIG_DISPLAY_BOARDINFO	1

/* Clock Defines */
#define V_OSCK			26000000	/* Clock output from T2 */
#define V_SCLK			(V_OSCK >> 1)

#define CONFIG_MISC_INIT_R

#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_INITRD_TAG		1
#define CONFIG_REVISION_TAG		1

#define CONFIG_OF_LIBFDT		1

/*
 * Size of malloc() pool
 * Total Size Environment - 256k
 * Malloc - add 256k
 */
#define CONFIG_ENV_SIZE			(256 << 10)
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (256 << 10))

/*--------------------------------------------------------------------------*/

/*
 * Hardware drivers
 */

/*
 * TWL4030
 */
#define CONFIG_TWL4030_POWER		1

/*
 * serial port - NS16550 compatible
 */
#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */

#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK

/* Original SDP u-boot used UART1 and thus J8 (innermost); that can be
 * swapped with UART2 via jumpering.  Downsides of using J8:  it doesn't
 * support UART boot (that's only for UART3); it prevents sharing a Linux
 * kernel (LL_DEBUG_UART3) or filesystem (getty ttyS2) with most boards.
 *
 * UART boot uses UART3 on J9, and the SDP user's guide says to use
 * that for console.  Downsides of using J9:  you can't use IRDA too;
 * since UART3 isn't in the CORE power domain, it may be a bit less
 * usable in certain PM-sensitive debug scenarios.
 */
#undef CONSOLE_J9			/* else J8/UART1 (innermost) */

#ifdef CONSOLE_J9
#define CONFIG_CONS_INDEX		3
#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
#define CONFIG_SERIAL3			3	/* UART3 */
#else
#define CONFIG_CONS_INDEX		1
#define CONFIG_SYS_NS16550_COM1		OMAP34XX_UART1
#define CONFIG_SERIAL1			1	/* UART1 */
#endif

#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
					115200}

/*
 * I2C for power management setup
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
#define CONFIG_SYS_I2C_OMAP34XX

/* OMITTED:  single 1 Gbit MT29F1G NAND flash */

/*
 * NOR boot support - single 1 Gbit PF48F6000M0 Strataflash
 */
#define CONFIG_SYS_FLASH_BASE		0x10000000
#define CONFIG_FLASH_CFI_DRIVER		1	/* Use drivers/cfi_flash.c */
#define CONFIG_SYS_FLASH_CFI		1	/* use CFI geometry data */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* ~10x faster writes */
#define CONFIG_SYS_FLASH_PROTECTION	1	/* hardware sector protection */
#define CONFIG_SYS_FLASH_EMPTY_INFO	1	/* flinfo 'E' for empty */
#define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE}
#define CONFIG_SYS_MAX_FLASH_BANKS      1	/* max number of flash banks */

#define CONFIG_SYS_FLASH_CFI_WIDTH	2
#define PHYS_FLASH_SIZE			(128 << 20)
#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max sectors on one chip */

/* OMITTED:  single 2 Gbit KFM2G16 OneNAND flash */

#define CONFIG_ENV_IS_IN_FLASH		1
#define CONFIG_SYS_ENV_SECT_SIZE	(256 << 10)
#define CONFIG_ENV_OFFSET		CONFIG_SYS_ENV_SECT_SIZE
#define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_ENV_SECT_SIZE)
/*--------------------------------------------------------------------------*/

/* Enabled commands */
#define CONFIG_CMD_DHCP		/* DHCP Support			*/
#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
#define CONFIG_CMD_FAT		/* FAT support			*/
#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
#define CONFIG_CMD_MMC		/* MMC support			*/

/*--------------------------------------------------------------------------*/
/*
 * MMC boot support
 */

#if defined(CONFIG_CMD_MMC)
#define CONFIG_GENERIC_MMC		1
#define CONFIG_MMC			1
#define CONFIG_OMAP_HSMMC		1
#define CONFIG_DOS_PARTITION		1
#endif

/*----------------------------------------------------------------------------
 * SMSC9115 Ethernet from SMSC9118 family
 *----------------------------------------------------------------------------
 */
#if defined(CONFIG_CMD_NET)

#define CONFIG_LAN91C96
#define CONFIG_LAN91C96_BASE	DEBUG_BASE
#define CONFIG_LAN91C96_EXT_PHY

#define CONFIG_BOOTP_SEND_HOSTNAME
/*
 * BOOTP fields
 */
#define CONFIG_BOOTP_SUBNETMASK		0x00000001
#define CONFIG_BOOTP_GATEWAY		0x00000002
#define CONFIG_BOOTP_HOSTNAME		0x00000004
#define CONFIG_BOOTP_BOOTPATH		0x00000010
#endif /* (CONFIG_CMD_NET) */

/*
 * Environment setup
 *
 * Default boot order:  mmc bootscript, MMC uImage, NOR image.
 * Network booting environment must be configured at site.
 */

/* allow overwriting serial config and ethaddr */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_EXTRA_ENV_SETTINGS \
	"loadaddr=0x82000000\0" \
	"console=ttyS0,115200n8\0" \
	"mmcargs=setenv bootargs console=${console} " \
		"root=/dev/mmcblk0p2 rw " \
		"rootfstype=ext3 rootwait\0" \
	"norargs=setenv bootargs console=${console} " \
		"root=/dev/mtdblock3 rw " \
		"rootfstype=jffs2\0" \
	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
	"bootscript=echo Running bootscript from MMC/SD ...; " \
		"autoscr ${loadaddr}\0" \
	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
	"mmcboot=echo Booting from MMC/SD ...; " \
		"run mmcargs; " \
		"bootm ${loadaddr}\0" \
	"norboot=echo Booting from NOR ...; " \
		"run norargs; " \
		"bootm 0x80000\0" \

#define CONFIG_BOOTCOMMAND \
	"if mmcinit; then " \
		"if run loadbootscript; then " \
			"run bootscript; " \
		"else " \
			"if run loaduimage; then " \
				"run mmcboot; " \
			"else run norboot; " \
			"fi; " \
		"fi; " \
	"else run norboot; fi"

#define CONFIG_AUTO_COMPLETE		1

/*--------------------------------------------------------------------------*/

/*
 * Miscellaneous configurable options
 */

#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)

/* SDRAM Test range - start at 16 meg boundary -ends at 32Meg -
 * a basic sanity check ONLY
 * IF you would like to increase coverage, increase the end address
 * or run the test with custom options
 */
#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0 + 0x01000000)
#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + (32 << 20))

/* Default load address */
#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)

/*--------------------------------------------------------------------------*/

/*
 * 3430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
 * 32KHz clk, or from external sig. This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE	0x800
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - \
					 GENERATED_GBL_DATA_SIZE)
/*
 * SDRAM Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

/*--------------------------------------------------------------------------*/

/*
 * NOR FLASH usage ... default nCS0:
 *  - one 256KB sector for U-Boot
 *  - one 256KB sector for its parameters (not all used)
 *  - eight sectors (2 MB) for kernel
 *  - rest for JFFS2
 */

/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)

/*
 * NAND FLASH usage ... default nCS1:
 *  - four 128KB sectors for X-Loader
 *  - four 128KB sectors for U-Boot
 *  - two 128KB sector for its parameters
 *  - 32 sectors (4 MB) for kernel
 *  - rest for filesystem
 */

/*
 * OneNAND FLASH usage ... default nCS2:
 *  - four 128KB sectors for X-Loader
 *  - two 128KB sectors for U-Boot
 *  - one 128KB sector for its parameters
 *  - sixteen sectors (2 MB) for kernel
 *  - rest for filesystem
 */

#define CONFIG_SYS_CACHELINE_SIZE	64

#endif				/* __CONFIG_H */
Commit	Line	Data
e63e5904 TR	1	/*
	2	* (C) Copyright 2006-2009
	3	* Texas Instruments Incorporated.
	4	* Richard Woodruff <r-woodruff2@ti.com>
	5	* Syed Mohammed Khasim <x0khasim@ti.com>
	6	* Nishanth Menon <nm@ti.com>
	7	*
	8	* Configuration settings for the 3430 TI SDP3430 board.
	9	*
3765b3e7	10	* SPDX-License-Identifier: GPL-2.0+
e63e5904 TR	11	*/
	12
	13	#ifndef __CONFIG_H
	14	#define __CONFIG_H
	15
	16	/* TODO: REMOVE THE FOLLOWING
	17	* Retained the following till size.h is removed in u-boot
	18	*/
1ace4022	19	#include <linux/sizes.h>
e63e5904 TR	20	/*
	21	* High Level Configuration Options
	22	*/
e63e5904	23	#define CONFIG_OMAP 1 /* in a TI OMAP core */
e63e5904	24	#define CONFIG_OMAP3_3430SDP 1 /* working with SDP Rev2 */
806d2792	25	#define CONFIG_OMAP_COMMON
c6f90e14 NM	26	/* Common ARM Erratas */
	27	#define CONFIG_ARM_ERRATA_454179
	28	#define CONFIG_ARM_ERRATA_430973
	29	#define CONFIG_ARM_ERRATA_621766
e63e5904	30
cae377b5 VH	31	#define CONFIG_SDRC /* The chip has SDRC controller */
cae377b5 VH	32
e63e5904	33	#include <asm/arch/cpu.h> /* get chip and board defs */
987ec585	34	#include <asm/arch/omap.h>
e63e5904 TR	35
	36	/*
	37	* NOTE: these #defines presume standard SDP jumper settings.
	38	* In particular:
	39	* - 26 MHz clock (not 19.2 or 38.4 MHz)
	40	* - Boot from 128MB NOR, not NAND or OneNAND
	41	*
	42	* At this writing, OMAP3 U-Boot support doesn't permit concurrent
	43	* support for all the flash types the board supports.
	44	*/
	45	#define CONFIG_DISPLAY_CPUINFO 1
	46	#define CONFIG_DISPLAY_BOARDINFO 1
	47
	48	/* Clock Defines */
	49	#define V_OSCK 26000000 /* Clock output from T2 */
	50	#define V_SCLK (V_OSCK >> 1)
	51
e63e5904 TR	52	#define CONFIG_MISC_INIT_R
	53
	54	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	55	#define CONFIG_SETUP_MEMORY_TAGS 1
	56	#define CONFIG_INITRD_TAG 1
	57	#define CONFIG_REVISION_TAG 1
	58
2fa8ca98 GL	59	#define CONFIG_OF_LIBFDT 1
2fa8ca98 GL	60
e63e5904 TR	61	/*
	62	* Size of malloc() pool
	63	* Total Size Environment - 256k
	64	* Malloc - add 256k
	65	*/
	66	#define CONFIG_ENV_SIZE (256 << 10)
	67	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10))
e63e5904 TR	68
	69	/--------------------------------------------------------------------------/
	70
	71	/*
	72	* Hardware drivers
	73	*/
	74
	75	/*
	76	* TWL4030
	77	*/
	78	#define CONFIG_TWL4030_POWER 1
	79
	80	/*
	81	* serial port - NS16550 compatible
	82	*/
	83	#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
	84
	85	#define CONFIG_SYS_NS16550
	86	#define CONFIG_SYS_NS16550_SERIAL
	87	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	88	#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
	89
	90	/* Original SDP u-boot used UART1 and thus J8 (innermost); that can be
	91	* swapped with UART2 via jumpering. Downsides of using J8: it doesn't
	92	* support UART boot (that's only for UART3); it prevents sharing a Linux
	93	* kernel (LL_DEBUG_UART3) or filesystem (getty ttyS2) with most boards.
	94	*
	95	* UART boot uses UART3 on J9, and the SDP user's guide says to use
	96	* that for console. Downsides of using J9: you can't use IRDA too;
	97	* since UART3 isn't in the CORE power domain, it may be a bit less
	98	* usable in certain PM-sensitive debug scenarios.
	99	*/
	100	#undef CONSOLE_J9 /* else J8/UART1 (innermost) */
	101
	102	#ifdef CONSOLE_J9
	103	#define CONFIG_CONS_INDEX 3
	104	#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
	105	#define CONFIG_SERIAL3 3 /* UART3 */
	106	#else
	107	#define CONFIG_CONS_INDEX 1
	108	#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
	109	#define CONFIG_SERIAL1 1 /* UART1 */
	110	#endif
	111
	112	#define CONFIG_ENV_OVERWRITE
	113	#define CONFIG_BAUDRATE 115200
	114	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
	115	115200}
	116
	117	/*
	118	* I2C for power management setup
	119	*/
6789e84e HS	120	#define CONFIG_SYS_I2C
	121	#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
	122	#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
	123	#define CONFIG_SYS_I2C_OMAP34XX
e63e5904 TR	124
	125	/* OMITTED: single 1 Gbit MT29F1G NAND flash */
	126
	127	/*
	128	* NOR boot support - single 1 Gbit PF48F6000M0 Strataflash
	129	*/
	130	#define CONFIG_SYS_FLASH_BASE 0x10000000
	131	#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
	132	#define CONFIG_SYS_FLASH_CFI 1 /* use CFI geometry data */
	133	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* ~10x faster writes */
	134	#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware sector protection */
	135	#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* flinfo 'E' for empty */
	136	#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
	137	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
	138
	139	#define CONFIG_SYS_FLASH_CFI_WIDTH 2
	140	#define PHYS_FLASH_SIZE (128 << 20)
	141	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors on one chip */
	142
e63e5904 TR	143	/* OMITTED: single 2 Gbit KFM2G16 OneNAND flash */
	144
	145	#define CONFIG_ENV_IS_IN_FLASH 1
	146	#define CONFIG_SYS_ENV_SECT_SIZE (256 << 10)
	147	#define CONFIG_ENV_OFFSET CONFIG_SYS_ENV_SECT_SIZE
	148	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_ENV_SECT_SIZE)
	149	/--------------------------------------------------------------------------/
	150
e63e5904 TR	151	/* Enabled commands */
	152	#define CONFIG_CMD_DHCP /* DHCP Support */
	153	#define CONFIG_CMD_EXT2 /* EXT2 Support */
	154	#define CONFIG_CMD_FAT /* FAT support */
	155	#define CONFIG_CMD_I2C /* I2C serial bus support */
	156	#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
	157	#define CONFIG_CMD_MMC /* MMC support */
e63e5904	158
e63e5904 TR	159	/--------------------------------------------------------------------------/
	160	/*
	161	* MMC boot support
	162	*/
	163
	164	#if defined(CONFIG_CMD_MMC)
7cc862be	165	#define CONFIG_GENERIC_MMC 1
e63e5904	166	#define CONFIG_MMC 1
7cc862be	167	#define CONFIG_OMAP_HSMMC 1
e63e5904 TR	168	#define CONFIG_DOS_PARTITION 1
	169	#endif
	170
	171	/*----------------------------------------------------------------------------
	172	* SMSC9115 Ethernet from SMSC9118 family
	173	*----------------------------------------------------------------------------
	174	*/
	175	#if defined(CONFIG_CMD_NET)
	176
a1725999	177	#define CONFIG_LAN91C96
e63e5904 TR	178	#define CONFIG_LAN91C96_BASE DEBUG_BASE
	179	#define CONFIG_LAN91C96_EXT_PHY
	180
	181	#define CONFIG_BOOTP_SEND_HOSTNAME
	182	/*
	183	* BOOTP fields
	184	*/
	185	#define CONFIG_BOOTP_SUBNETMASK 0x00000001
	186	#define CONFIG_BOOTP_GATEWAY 0x00000002
	187	#define CONFIG_BOOTP_HOSTNAME 0x00000004
	188	#define CONFIG_BOOTP_BOOTPATH 0x00000010
	189	#endif /* (CONFIG_CMD_NET) */
	190
	191	/*
	192	* Environment setup
	193	*
	194	* Default boot order: mmc bootscript, MMC uImage, NOR image.
	195	* Network booting environment must be configured at site.
	196	*/
	197
	198	/* allow overwriting serial config and ethaddr */
	199	#define CONFIG_ENV_OVERWRITE
	200
	201	#define CONFIG_EXTRA_ENV_SETTINGS \
	202	"loadaddr=0x82000000\0" \
	203	"console=ttyS0,115200n8\0" \
	204	"mmcargs=setenv bootargs console=${console} " \
	205	"root=/dev/mmcblk0p2 rw " \
	206	"rootfstype=ext3 rootwait\0" \
	207	"norargs=setenv bootargs console=${console} " \
	208	"root=/dev/mtdblock3 rw " \
	209	"rootfstype=jffs2\0" \
	210	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
	211	"bootscript=echo Running bootscript from MMC/SD ...; " \
	212	"autoscr ${loadaddr}\0" \
	213	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
	214	"mmcboot=echo Booting from MMC/SD ...; " \
	215	"run mmcargs; " \
	216	"bootm ${loadaddr}\0" \
	217	"norboot=echo Booting from NOR ...; " \
	218	"run norargs; " \
	219	"bootm 0x80000\0" \
	220
	221	#define CONFIG_BOOTCOMMAND \
	222	"if mmcinit; then " \
	223	"if run loadbootscript; then " \
	224	"run bootscript; " \
	225	"else " \
	226	"if run loaduimage; then " \
	227	"run mmcboot; " \
	228	"else run norboot; " \
	229	"fi; " \
	230	"fi; " \
	231	"else run norboot; fi"
	232
	233	#define CONFIG_AUTO_COMPLETE 1
	234
	235	/--------------------------------------------------------------------------/
	236
	237	/*
	238	* Miscellaneous configurable options
	239	*/
e63e5904 TR	240
	241	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	242	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
f62b1257	243	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
e63e5904 TR	244	/* Print Buffer Size */
	245	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	246	sizeof(CONFIG_SYS_PROMPT) + 16)
	247	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	248	/* Boot Argument Buffer Size */
	249	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	250
	251	/* SDRAM Test range - start at 16 meg boundary -ends at 32Meg -
	252	* a basic sanity check ONLY
	253	* IF you would like to increase coverage, increase the end address
	254	* or run the test with custom options
	255	*/
	256	#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x01000000)
	257	#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + (32 << 20))
	258
	259	/* Default load address */
	260	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
	261
	262	/--------------------------------------------------------------------------/
	263
	264	/*
	265	* 3430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
	266	* 32KHz clk, or from external sig. This rate is divided by a local divisor.
	267	*/
	268	#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
	269	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
e63e5904	270
5ec789f6 DB	271	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	272	#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
	273	#define CONFIG_SYS_INIT_RAM_SIZE 0x800
	274	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	275	CONFIG_SYS_INIT_RAM_SIZE - \
	276	GENERATED_GBL_DATA_SIZE)
e63e5904 TR	277	/*
	278	* SDRAM Memory Map
	279	*/
	280	#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
	281	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
e63e5904 TR	282	#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
e63e5904 TR	283
e63e5904 TR	284	/--------------------------------------------------------------------------/
	285
	286	/*
	287	* NOR FLASH usage ... default nCS0:
	288	* - one 256KB sector for U-Boot
	289	* - one 256KB sector for its parameters (not all used)
	290	* - eight sectors (2 MB) for kernel
	291	* - rest for JFFS2
	292	*/
	293
	294	/* Monitor at start of flash */
	295	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	296	#define CONFIG_SYS_MONITOR_LEN (256 << 10)
	297
e63e5904 TR	298	/*
	299	* NAND FLASH usage ... default nCS1:
	300	* - four 128KB sectors for X-Loader
	301	* - four 128KB sectors for U-Boot
	302	* - two 128KB sector for its parameters
	303	* - 32 sectors (4 MB) for kernel
	304	* - rest for filesystem
	305	*/
	306
	307	/*
	308	* OneNAND FLASH usage ... default nCS2:
	309	* - four 128KB sectors for X-Loader
	310	* - two 128KB sectors for U-Boot
	311	* - one 128KB sector for its parameters
	312	* - sixteen sectors (2 MB) for kernel
	313	* - rest for filesystem
	314	*/
	315
8e40852f A	316	#define CONFIG_SYS_CACHELINE_SIZE 64
8e40852f A	317
e63e5904	318	#endif /* __CONFIG_H */