[people/ms/u-boot.git] / include / configs / omap3_zoom1.h

/*
 * (C) Copyright 2006-2008
 * Texas Instruments.
 * Richard Woodruff <r-woodruff2@ti.com>
 * Syed Mohammed Khasim <x0khasim@ti.com>
 * Nishanth Menon <nm@ti.com>
 *
 * Configuration settings for the TI OMAP3430 Zoom MDK board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/sizes.h>

/*
 * High Level Configuration Options
 */
#define CONFIG_ARMCORTEXA8	1	/* This is an ARM V7 CPU core */
#define CONFIG_OMAP		1	/* in a TI OMAP core */
#define CONFIG_OMAP34XX		1	/* which is a 34XX */
#define CONFIG_OMAP3430		1	/* which is in a 3430 */
#define CONFIG_OMAP3_ZOOM1	1	/* working with Zoom MDK Rev1 */

#include <asm/arch/cpu.h>		/* get chip and board defs */
#include <asm/arch/omap3.h>

/*
 * Display CPU and Board information
 */
#define CONFIG_DISPLAY_CPUINFO		1
#define CONFIG_DISPLAY_BOARDINFO	1

/* Clock Defines */
#define V_OSCK			26000000	/* Clock output from T2 */
#define V_SCLK			(V_OSCK >> 1)

#undef CONFIG_USE_IRQ				/* no support for IRQs */
#define CONFIG_MISC_INIT_R

#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_INITRD_TAG		1
#define CONFIG_REVISION_TAG		1

/*
 * Size of malloc() pool
 */
#define CONFIG_ENV_SIZE			SZ_128K	/* Total Size Environment */
						/* Sector */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + SZ_128K)
#define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for */
						/* initial data */

/*
 * Hardware drivers
 */

/*
 * NS16550 Configuration
 */
#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */

#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK

/*
 * select serial console configuration
 */
#define CONFIG_CONS_INDEX		3
#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
#define CONFIG_SERIAL3			3	/* UART3 */

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
					115200}
#define CONFIG_MMC			1
#define CONFIG_OMAP3_MMC		1
#define CONFIG_DOS_PARTITION		1

/* commands to include */
#include <config_cmd_default.h>

#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
#define CONFIG_CMD_FAT		/* FAT support			*/
#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/

#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
#define CONFIG_CMD_MMC		/* MMC support			*/
#define CONFIG_CMD_NAND		/* NAND support			*/
#define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */

#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
#undef CONFIG_CMD_IMI		/* iminfo			*/
#undef CONFIG_CMD_IMLS		/* List all found images	*/
#undef CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
#undef CONFIG_CMD_NFS		/* NFS support			*/

#define CONFIG_SYS_NO_FLASH
#define CONFIG_HARD_I2C			1
#define CONFIG_SYS_I2C_SPEED		100000
#define CONFIG_SYS_I2C_SLAVE		1
#define CONFIG_SYS_I2C_BUS		0
#define CONFIG_SYS_I2C_BUS_SELECT	1
#define CONFIG_DRIVER_OMAP34XX_I2C	1

/*
 * TWL4030
 */
#define CONFIG_TWL4030_POWER		1
#define CONFIG_TWL4030_LED		1

/*
 * Board NAND Info.
 */
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
							/* to access nand */
#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
							/* to access nand at */
							/* CS0 */
#define GPMC_NAND_ECC_LP_x16_LAYOUT	1

#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
							/* devices */

#define CONFIG_SYS_64BIT_VSPRINTF		/* needed for nand_util.c */

#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV		"nand0"
/* start of jffs2 partition */
#define CONFIG_JFFS2_PART_OFFSET	0x680000
#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* size of jffs2 */
							/* partition */

/* Environment information */
#define CONFIG_BOOTDELAY		10

#define CONFIG_EXTRA_ENV_SETTINGS \
	"loadaddr=0x82000000\0" \
	"console=ttyS2,115200n8\0" \
	"videomode=1024x768@60,vxres=1024,vyres=768\0" \
	"videospec=omapfb:vram:2M,vram:4M\0" \
	"mmcargs=setenv bootargs console=${console} " \
		"video=${videospec},mode:${videomode} " \
		"root=/dev/mmcblk0p2 rw " \
		"rootfstype=ext3 rootwait\0" \
	"nandargs=setenv bootargs console=${console} " \
		"video=${videospec},mode:${videomode} " \
		"root=/dev/mtdblock4 rw " \
		"rootfstype=jffs2\0" \
	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
	"bootscript=echo Running bootscript from mmc ...; " \
		"source ${loadaddr}\0" \
	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
	"mmcboot=echo Booting from mmc ...; " \
		"run mmcargs; " \
		"bootm ${loadaddr}\0" \
	"nandboot=echo Booting from nand ...; " \
		"run nandargs; " \
		"nand read ${loadaddr} 280000 400000; " \
		"bootm ${loadaddr}\0" \

#define CONFIG_BOOTCOMMAND \
	"if mmc init; then " \
		"if run loadbootscript; then " \
			"run bootscript; " \
		"else " \
			"if run loaduimage; then " \
				"run mmcboot; " \
			"else run nandboot; " \
			"fi; " \
		"fi; " \
	"else run nandboot; fi"

#define CONFIG_AUTO_COMPLETE		1
/*
 * Miscellaneous configurable options
 */
#define V_PROMPT			"OMAP3 Zoom1# "

#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
#define CONFIG_SYS_PROMPT		V_PROMPT
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)

#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)	/* memtest */
								/* works on */
#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
					0x01F00000) /* 31MB */

#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)	/* default */
							/* load address */

/*
 * OMAP3 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ			1000

/*-----------------------------------------------------------------------
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE	SZ_128K	/* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ	SZ_4K	/* IRQ stack */
#define CONFIG_STACKSIZE_FIQ	SZ_4K	/* FIQ stack */
#endif

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_1_SIZE	SZ_32M	/* at least 32 meg */
#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

/* SDRAM Bank Allocation method */
#define SDRC_R_B_C		1

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */

/* **** PISMO SUPPORT *** */

/* Configure the PISMO */
#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M

#define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors on */
						/* one chip */
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
#define CONFIG_SYS_MONITOR_LEN		SZ_256K	/* Reserve 2 sectors */

#define CONFIG_SYS_FLASH_BASE		boot_flash_base

/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP

#define CONFIG_ENV_IS_IN_NAND		1
#define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */

#define CONFIG_SYS_ENV_SECT_SIZE	boot_flash_sec
#define CONFIG_ENV_OFFSET		boot_flash_off
#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET

/*-----------------------------------------------------------------------
 * CFI FLASH driver setup
 */
/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)

/* Flash banks JFFS2 should use */
#define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
					CONFIG_SYS_MAX_NAND_DEVICE)
#define CONFIG_SYS_JFFS2_MEM_NAND
/* use flash_info[2] */
#define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
#define CONFIG_SYS_JFFS2_NUM_BANKS	1

#ifndef __ASSEMBLY__
extern struct gpmc *gpmc_cfg;
extern unsigned int boot_flash_base;
extern volatile unsigned int boot_flash_env_addr;
extern unsigned int boot_flash_off;
extern unsigned int boot_flash_sec;
extern unsigned int boot_flash_type;
#endif

#endif				/* __CONFIG_H */
Commit	Line	Data
7379f45a DB	1	/*
	2	* (C) Copyright 2006-2008
	3	* Texas Instruments.
	4	* Richard Woodruff <r-woodruff2@ti.com>
	5	* Syed Mohammed Khasim <x0khasim@ti.com>
	6	* Nishanth Menon <nm@ti.com>
	7	*
	8	* Configuration settings for the TI OMAP3430 Zoom MDK board.
	9	*
	10	* See file CREDITS for list of people who contributed to this
	11	* project.
	12	*
	13	* This program is free software; you can redistribute it and/or
	14	* modify it under the terms of the GNU General Public License as
	15	* published by the Free Software Foundation; either version 2 of
	16	* the License, or (at your option) any later version.
	17	*
	18	* This program is distributed in the hope that it will be useful,
	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	21	* GNU General Public License for more details.
	22	*
	23	* You should have received a copy of the GNU General Public License
	24	* along with this program; if not, write to the Free Software
	25	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	26	* MA 02111-1307 USA
	27	*/
	28
	29	#ifndef __CONFIG_H
	30	#define __CONFIG_H
	31	#include <asm/sizes.h>
	32
	33	/*
	34	* High Level Configuration Options
	35	*/
	36	#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
	37	#define CONFIG_OMAP 1 /* in a TI OMAP core */
	38	#define CONFIG_OMAP34XX 1 /* which is a 34XX */
	39	#define CONFIG_OMAP3430 1 /* which is in a 3430 */
	40	#define CONFIG_OMAP3_ZOOM1 1 /* working with Zoom MDK Rev1 */
	41
	42	#include <asm/arch/cpu.h> /* get chip and board defs */
	43	#include <asm/arch/omap3.h>
	44
6a6b62e3 SP	45	/*
	46	* Display CPU and Board information
	47	*/
	48	#define CONFIG_DISPLAY_CPUINFO 1
	49	#define CONFIG_DISPLAY_BOARDINFO 1
	50
7379f45a DB	51	/* Clock Defines */
	52	#define V_OSCK 26000000 /* Clock output from T2 */
	53	#define V_SCLK (V_OSCK >> 1)
	54
	55	#undef CONFIG_USE_IRQ /* no support for IRQs */
	56	#define CONFIG_MISC_INIT_R
	57
	58	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	59	#define CONFIG_SETUP_MEMORY_TAGS 1
	60	#define CONFIG_INITRD_TAG 1
	61	#define CONFIG_REVISION_TAG 1
	62
	63	/*
	64	* Size of malloc() pool
	65	*/
	66	#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */
	67	/* Sector */
	68	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K)
	69	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
	70	/* initial data */
	71
	72	/*
	73	* Hardware drivers
	74	*/
	75
	76	/*
	77	* NS16550 Configuration
	78	*/
	79	#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
	80
	81	#define CONFIG_SYS_NS16550
	82	#define CONFIG_SYS_NS16550_SERIAL
	83	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	84	#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
	85
	86	/*
	87	* select serial console configuration
	88	*/
	89	#define CONFIG_CONS_INDEX 3
	90	#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
	91	#define CONFIG_SERIAL3 3 /* UART3 */
	92
	93	/* allow to overwrite serial and ethaddr */
	94	#define CONFIG_ENV_OVERWRITE
	95	#define CONFIG_BAUDRATE 115200
	96	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
	97	115200}
	98	#define CONFIG_MMC 1
	99	#define CONFIG_OMAP3_MMC 1
	100	#define CONFIG_DOS_PARTITION 1
	101
	102	/* commands to include */
	103	#include <config_cmd_default.h>
	104
	105	#define CONFIG_CMD_EXT2 /* EXT2 Support */
	106	#define CONFIG_CMD_FAT /* FAT support */
	107	#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
	108
	109	#define CONFIG_CMD_I2C /* I2C serial bus support */
	110	#define CONFIG_CMD_MMC /* MMC support */
	111	#define CONFIG_CMD_NAND /* NAND support */
e7deec1b	112	#define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */
7379f45a DB	113
	114	#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
	115	#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
	116	#undef CONFIG_CMD_IMI /* iminfo */
	117	#undef CONFIG_CMD_IMLS /* List all found images */
	118	#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
	119	#undef CONFIG_CMD_NFS /* NFS support */
	120
	121	#define CONFIG_SYS_NO_FLASH
0297ec7e	122	#define CONFIG_HARD_I2C 1
7379f45a DB	123	#define CONFIG_SYS_I2C_SPEED 100000
	124	#define CONFIG_SYS_I2C_SLAVE 1
	125	#define CONFIG_SYS_I2C_BUS 0
	126	#define CONFIG_SYS_I2C_BUS_SELECT 1
	127	#define CONFIG_DRIVER_OMAP34XX_I2C 1
	128
cd782635 TR	129	/*
	130	* TWL4030
	131	*/
	132	#define CONFIG_TWL4030_POWER 1
2c155130	133	#define CONFIG_TWL4030_LED 1
cd782635	134
7379f45a DB	135	/*
	136	* Board NAND Info.
	137	*/
	138	#define CONFIG_NAND_OMAP_GPMC
	139	#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
	140	/* to access nand */
	141	#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
	142	/* to access nand at */
	143	/* CS0 */
	144	#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
	145
	146	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
	147	/* devices */
2eb99ca8 WD	148
	149	#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
	150
7379f45a DB	151	#define CONFIG_JFFS2_NAND
	152	/* nand device jffs2 lives on */
	153	#define CONFIG_JFFS2_DEV "nand0"
	154	/* start of jffs2 partition */
	155	#define CONFIG_JFFS2_PART_OFFSET 0x680000
	156	#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
	157	/* partition */
	158
	159	/* Environment information */
	160	#define CONFIG_BOOTDELAY 10
	161
	162	#define CONFIG_EXTRA_ENV_SETTINGS \
	163	"loadaddr=0x82000000\0" \
	164	"console=ttyS2,115200n8\0" \
	165	"videomode=1024x768@60,vxres=1024,vyres=768\0" \
	166	"videospec=omapfb:vram:2M,vram:4M\0" \
	167	"mmcargs=setenv bootargs console=${console} " \
	168	"video=${videospec},mode:${videomode} " \
	169	"root=/dev/mmcblk0p2 rw " \
	170	"rootfstype=ext3 rootwait\0" \
	171	"nandargs=setenv bootargs console=${console} " \
	172	"video=${videospec},mode:${videomode} " \
	173	"root=/dev/mtdblock4 rw " \
	174	"rootfstype=jffs2\0" \
	175	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
	176	"bootscript=echo Running bootscript from mmc ...; " \
74de7aef	177	"source ${loadaddr}\0" \
7379f45a DB	178	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
	179	"mmcboot=echo Booting from mmc ...; " \
	180	"run mmcargs; " \
	181	"bootm ${loadaddr}\0" \
	182	"nandboot=echo Booting from nand ...; " \
	183	"run nandargs; " \
	184	"nand read ${loadaddr} 280000 400000; " \
	185	"bootm ${loadaddr}\0" \
	186
	187	#define CONFIG_BOOTCOMMAND \
a85693b3	188	"if mmc init; then " \
7379f45a DB	189	"if run loadbootscript; then " \
	190	"run bootscript; " \
	191	"else " \
	192	"if run loaduimage; then " \
	193	"run mmcboot; " \
	194	"else run nandboot; " \
	195	"fi; " \
	196	"fi; " \
	197	"else run nandboot; fi"
	198
	199	#define CONFIG_AUTO_COMPLETE 1
	200	/*
	201	* Miscellaneous configurable options
	202	*/
	203	#define V_PROMPT "OMAP3 Zoom1# "
	204
	205	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	206	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
	207	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
	208	#define CONFIG_SYS_PROMPT V_PROMPT
	209	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	210	/* Print Buffer Size */
	211	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	212	sizeof(CONFIG_SYS_PROMPT) + 16)
	213	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	214	/* Boot Argument Buffer Size */
	215	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	216
	217	#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
	218	/* works on */
	219	#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
	220	0x01F00000) /* 31MB */
	221
7379f45a DB	222	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
	223	/* load address */
	224
	225	/*
d3a513c2 MP	226	* OMAP3 has 12 GP timers, they can be driven by the system clock
	227	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
	228	* This rate is divided by a local divisor.
7379f45a	229	*/
d3a513c2 MP	230	#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
	231	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
	232	#define CONFIG_SYS_HZ 1000
7379f45a DB	233
	234	/*-----------------------------------------------------------------------
	235	* Stack sizes
	236	*
	237	* The stack sizes are set up in start.S using the settings below
	238	*/
	239	#define CONFIG_STACKSIZE SZ_128K /* regular stack */
	240	#ifdef CONFIG_USE_IRQ
	241	#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */
	242	#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */
	243	#endif
	244
	245	/*-----------------------------------------------------------------------
	246	* Physical Memory Map
	247	*/
	248	#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
	249	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
	250	#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */
	251	#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
	252
	253	/* SDRAM Bank Allocation method */
	254	#define SDRC_R_B_C 1
	255
	256	/*-----------------------------------------------------------------------
	257	* FLASH and environment organization
	258	*/
	259
	260	/* ** PISMO SUPPORT * */
	261
	262	/* Configure the PISMO */
	263	#define PISMO1_NAND_SIZE GPMC_SIZE_128M
	264	#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
	265
	266	#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */
	267	/* one chip */
	268	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
	269	#define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */
	270
	271	#define CONFIG_SYS_FLASH_BASE boot_flash_base
	272
	273	/* Monitor at start of flash */
	274	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	275	#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
	276
	277	#define CONFIG_ENV_IS_IN_NAND 1
	278	#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
	279	#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
	280
	281	#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
	282	#define CONFIG_ENV_OFFSET boot_flash_off
	283	#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
	284
	285	/*-----------------------------------------------------------------------
	286	* CFI FLASH driver setup
	287	*/
	288	/* timeout values are in ticks */
	289	#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
	290	#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
	291
	292	/* Flash banks JFFS2 should use */
	293	#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
	294	CONFIG_SYS_MAX_NAND_DEVICE)
	295	#define CONFIG_SYS_JFFS2_MEM_NAND
	296	/* use flash_info[2] */
297	#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
298	#define CONFIG_SYS_JFFS2_NUM_BANKS 1
299
300	#ifndef __ASSEMBLY__
97a099ea	301	extern struct gpmc *gpmc_cfg;
7379f45a DB	302	extern unsigned int boot_flash_base;
	303	extern volatile unsigned int boot_flash_env_addr;
	304	extern unsigned int boot_flash_off;
	305	extern unsigned int boot_flash_sec;
	306	extern unsigned int boot_flash_type;
	307	#endif
	308
7379f45a	309	#endif /* __CONFIG_H */