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7379f45a DB |
1 | /* |
2 | * (C) Copyright 2006-2008 | |
3 | * Texas Instruments. | |
4 | * Richard Woodruff <r-woodruff2@ti.com> | |
5 | * Syed Mohammed Khasim <x0khasim@ti.com> | |
6 | * Nishanth Menon <nm@ti.com> | |
7 | * | |
8 | * Configuration settings for the TI OMAP3430 Zoom MDK board. | |
9 | * | |
3765b3e7 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
7379f45a DB |
11 | */ |
12 | ||
13 | #ifndef __CONFIG_H | |
14 | #define __CONFIG_H | |
7379f45a DB |
15 | |
16 | /* | |
17 | * High Level Configuration Options | |
18 | */ | |
7379f45a DB |
19 | #define CONFIG_OMAP 1 /* in a TI OMAP core */ |
20 | #define CONFIG_OMAP34XX 1 /* which is a 34XX */ | |
7379f45a | 21 | #define CONFIG_OMAP3_ZOOM1 1 /* working with Zoom MDK Rev1 */ |
806d2792 | 22 | #define CONFIG_OMAP_COMMON |
ae3248a3 | 23 | #define CONFIG_SYS_GENERIC_BOARD |
7379f45a | 24 | |
cae377b5 VH |
25 | #define CONFIG_SDRC /* The chip has SDRC controller */ |
26 | ||
7379f45a DB |
27 | #include <asm/arch/cpu.h> /* get chip and board defs */ |
28 | #include <asm/arch/omap3.h> | |
29 | ||
6a6b62e3 SP |
30 | /* |
31 | * Display CPU and Board information | |
32 | */ | |
33 | #define CONFIG_DISPLAY_CPUINFO 1 | |
34 | #define CONFIG_DISPLAY_BOARDINFO 1 | |
35 | ||
7379f45a DB |
36 | /* Clock Defines */ |
37 | #define V_OSCK 26000000 /* Clock output from T2 */ | |
38 | #define V_SCLK (V_OSCK >> 1) | |
39 | ||
7379f45a DB |
40 | #define CONFIG_MISC_INIT_R |
41 | ||
42 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ | |
43 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
44 | #define CONFIG_INITRD_TAG 1 | |
45 | #define CONFIG_REVISION_TAG 1 | |
46 | ||
2fa8ca98 | 47 | #define CONFIG_OF_LIBFDT 1 |
c2e7c7b2 | 48 | #define CONFIG_CMD_BOOTZ 1 |
2fa8ca98 | 49 | |
7379f45a DB |
50 | /* |
51 | * Size of malloc() pool | |
52 | */ | |
9c44ddcc | 53 | #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ |
7379f45a | 54 | /* Sector */ |
9c44ddcc | 55 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) |
7379f45a DB |
56 | |
57 | /* | |
58 | * Hardware drivers | |
59 | */ | |
60 | ||
61 | /* | |
62 | * NS16550 Configuration | |
63 | */ | |
64 | #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ | |
65 | ||
66 | #define CONFIG_SYS_NS16550 | |
67 | #define CONFIG_SYS_NS16550_SERIAL | |
68 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) | |
69 | #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK | |
70 | ||
71 | /* | |
72 | * select serial console configuration | |
73 | */ | |
74 | #define CONFIG_CONS_INDEX 3 | |
75 | #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 | |
76 | #define CONFIG_SERIAL3 3 /* UART3 */ | |
77 | ||
78 | /* allow to overwrite serial and ethaddr */ | |
79 | #define CONFIG_ENV_OVERWRITE | |
80 | #define CONFIG_BAUDRATE 115200 | |
81 | #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ | |
82 | 115200} | |
d6906cb8 | 83 | #define CONFIG_GENERIC_MMC 1 |
7379f45a | 84 | #define CONFIG_MMC 1 |
d6906cb8 | 85 | #define CONFIG_OMAP_HSMMC 1 |
7379f45a DB |
86 | #define CONFIG_DOS_PARTITION 1 |
87 | ||
05be5a60 TR |
88 | /* USB */ |
89 | #define CONFIG_MUSB_UDC 1 | |
90 | #define CONFIG_USB_OMAP3 1 | |
91 | #define CONFIG_TWL4030_USB 1 | |
92 | ||
93 | /* USB device configuration */ | |
94 | #define CONFIG_USB_DEVICE 1 | |
95 | #define CONFIG_USB_TTY 1 | |
96 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 | |
97 | /* Change these to suit your needs */ | |
98 | #define CONFIG_USBD_VENDORID 0x0451 | |
99 | #define CONFIG_USBD_PRODUCTID 0x5678 | |
100 | #define CONFIG_USBD_MANUFACTURER "Texas Instruments" | |
101 | #define CONFIG_USBD_PRODUCT_NAME "Zoom1" | |
102 | ||
7379f45a DB |
103 | /* commands to include */ |
104 | #include <config_cmd_default.h> | |
105 | ||
106 | #define CONFIG_CMD_EXT2 /* EXT2 Support */ | |
107 | #define CONFIG_CMD_FAT /* FAT support */ | |
4e8183b7 NM |
108 | #define CONFIG_CMD_FS_GENERIC /* Generic FS support */ |
109 | #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ | |
110 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ | |
111 | #define MTDIDS_DEFAULT "nand0=nand" | |
112 | #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ | |
113 | "1920k(u-boot),128k(u-boot-env),"\ | |
114 | "4m(kernel),-(fs)" | |
7379f45a DB |
115 | |
116 | #define CONFIG_CMD_I2C /* I2C serial bus support */ | |
117 | #define CONFIG_CMD_MMC /* MMC support */ | |
118 | #define CONFIG_CMD_NAND /* NAND support */ | |
e7deec1b | 119 | #define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */ |
7379f45a DB |
120 | |
121 | #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ | |
122 | #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ | |
123 | #undef CONFIG_CMD_IMI /* iminfo */ | |
124 | #undef CONFIG_CMD_IMLS /* List all found images */ | |
9d70e772 | 125 | #define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ |
d71dd042 NM |
126 | #define CONFIG_CMD_NFS /* NFS support */ |
127 | #define CONFIG_CMD_PING | |
128 | #define CONFIG_CMD_DHCP | |
7379f45a DB |
129 | |
130 | #define CONFIG_SYS_NO_FLASH | |
6789e84e HS |
131 | #define CONFIG_SYS_I2C |
132 | #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 | |
133 | #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 | |
134 | #define CONFIG_SYS_I2C_OMAP34XX | |
7379f45a | 135 | |
cd782635 TR |
136 | /* |
137 | * TWL4030 | |
138 | */ | |
139 | #define CONFIG_TWL4030_POWER 1 | |
2c155130 | 140 | #define CONFIG_TWL4030_LED 1 |
cd782635 | 141 | |
7379f45a DB |
142 | /* |
143 | * Board NAND Info. | |
144 | */ | |
145 | #define CONFIG_NAND_OMAP_GPMC | |
146 | #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ | |
147 | /* to access nand */ | |
148 | #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ | |
149 | /* to access nand at */ | |
150 | /* CS0 */ | |
7379f45a DB |
151 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ |
152 | /* devices */ | |
7379f45a DB |
153 | |
154 | /* Environment information */ | |
155 | #define CONFIG_BOOTDELAY 10 | |
156 | ||
157 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
158 | "loadaddr=0x82000000\0" \ | |
c2e7c7b2 | 159 | "fdtaddr=0x80f80000\0" \ |
4e8183b7 | 160 | "bootfile=uImage\0" \ |
c2e7c7b2 | 161 | "fdtfile=omap3-ldp.dtb\0" \ |
4e8183b7 NM |
162 | "bootdir=/\0" \ |
163 | "bootpart=0:1\0" \ | |
05be5a60 | 164 | "usbtty=cdc_acm\0" \ |
7379f45a | 165 | "console=ttyS2,115200n8\0" \ |
d6906cb8 | 166 | "mmcdev=0\0" \ |
7379f45a DB |
167 | "videomode=1024x768@60,vxres=1024,vyres=768\0" \ |
168 | "videospec=omapfb:vram:2M,vram:4M\0" \ | |
169 | "mmcargs=setenv bootargs console=${console} " \ | |
170 | "video=${videospec},mode:${videomode} " \ | |
171 | "root=/dev/mmcblk0p2 rw " \ | |
172 | "rootfstype=ext3 rootwait\0" \ | |
173 | "nandargs=setenv bootargs console=${console} " \ | |
174 | "video=${videospec},mode:${videomode} " \ | |
175 | "root=/dev/mtdblock4 rw " \ | |
176 | "rootfstype=jffs2\0" \ | |
d6906cb8 | 177 | "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ |
7379f45a | 178 | "bootscript=echo Running bootscript from mmc ...; " \ |
74de7aef | 179 | "source ${loadaddr}\0" \ |
4e8183b7 | 180 | "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ |
c2e7c7b2 NM |
181 | "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ |
182 | "loadzimage=setenv bootfile zImage; if run loadimage; then run loadfdt;fi\0"\ | |
7379f45a DB |
183 | "mmcboot=echo Booting from mmc ...; " \ |
184 | "run mmcargs; " \ | |
185 | "bootm ${loadaddr}\0" \ | |
c2e7c7b2 NM |
186 | "mmczboot=echo Booting from mmc ...; " \ |
187 | "run mmcargs; " \ | |
188 | "bootz ${loadaddr} - ${fdtaddr}\0" \ | |
7379f45a DB |
189 | "nandboot=echo Booting from nand ...; " \ |
190 | "run nandargs; " \ | |
191 | "nand read ${loadaddr} 280000 400000; " \ | |
192 | "bootm ${loadaddr}\0" \ | |
193 | ||
194 | #define CONFIG_BOOTCOMMAND \ | |
66968110 | 195 | "mmc dev ${mmcdev}; if mmc rescan; then " \ |
7379f45a DB |
196 | "if run loadbootscript; then " \ |
197 | "run bootscript; " \ | |
198 | "else " \ | |
4e8183b7 | 199 | "if run loadimage; then " \ |
7379f45a | 200 | "run mmcboot; " \ |
c2e7c7b2 NM |
201 | "else if run loadzimage; then " \ |
202 | "run mmczboot; " \ | |
7379f45a | 203 | "else run nandboot; " \ |
c2e7c7b2 | 204 | "fi; fi;" \ |
7379f45a DB |
205 | "fi; " \ |
206 | "else run nandboot; fi" | |
207 | ||
208 | #define CONFIG_AUTO_COMPLETE 1 | |
209 | /* | |
210 | * Miscellaneous configurable options | |
211 | */ | |
7379f45a DB |
212 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
213 | #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ | |
1270ec13 | 214 | #define CONFIG_SYS_PROMPT "OMAP3 Zoom1 # " |
f62b1257 | 215 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ |
7379f45a DB |
216 | /* Print Buffer Size */ |
217 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
218 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
219 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
220 | /* Boot Argument Buffer Size */ | |
221 | #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) | |
222 | ||
223 | #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ | |
224 | /* works on */ | |
225 | #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ | |
226 | 0x01F00000) /* 31MB */ | |
227 | ||
7379f45a DB |
228 | #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ |
229 | /* load address */ | |
230 | ||
25435c6c DB |
231 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
232 | #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 | |
233 | #define CONFIG_SYS_INIT_RAM_SIZE 0x800 | |
234 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ | |
235 | CONFIG_SYS_INIT_RAM_SIZE - \ | |
236 | GENERATED_GBL_DATA_SIZE) | |
7379f45a | 237 | /* |
d3a513c2 MP |
238 | * OMAP3 has 12 GP timers, they can be driven by the system clock |
239 | * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). | |
240 | * This rate is divided by a local divisor. | |
7379f45a | 241 | */ |
d3a513c2 MP |
242 | #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 |
243 | #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ | |
7379f45a | 244 | |
7379f45a DB |
245 | /*----------------------------------------------------------------------- |
246 | * Physical Memory Map | |
247 | */ | |
248 | #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ | |
249 | #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 | |
7379f45a DB |
250 | #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 |
251 | ||
7379f45a DB |
252 | /*----------------------------------------------------------------------- |
253 | * FLASH and environment organization | |
254 | */ | |
255 | ||
256 | /* **** PISMO SUPPORT *** */ | |
257 | ||
258 | /* Configure the PISMO */ | |
259 | #define PISMO1_NAND_SIZE GPMC_SIZE_128M | |
260 | #define PISMO1_ONEN_SIZE GPMC_SIZE_128M | |
261 | ||
9c44ddcc | 262 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ |
7379f45a | 263 | |
6cbec7b3 LC |
264 | #if defined(CONFIG_CMD_NAND) |
265 | #define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE | |
266 | #endif | |
7379f45a DB |
267 | |
268 | /* Monitor at start of flash */ | |
269 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
270 | #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP | |
271 | ||
272 | #define CONFIG_ENV_IS_IN_NAND 1 | |
273 | #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ | |
274 | #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ | |
275 | ||
6cbec7b3 LC |
276 | #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ |
277 | #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET | |
7379f45a DB |
278 | #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET |
279 | ||
8e40852f A |
280 | #define CONFIG_SYS_CACHELINE_SIZE 64 |
281 | ||
9d70e772 NM |
282 | #ifdef CONFIG_CMD_NET |
283 | /* Ethernet (LAN9211 from SMSC9118 family) */ | |
284 | #define CONFIG_SMC911X | |
285 | #define CONFIG_SMC911X_32_BIT | |
286 | #define CONFIG_SMC911X_BASE DEBUG_BASE | |
287 | ||
288 | #endif | |
289 | ||
7379f45a | 290 | #endif /* __CONFIG_H */ |