[people/ms/u-boot.git] / include / configs / omap3_zoom2.h

/*
 * (C) Copyright 2006-2009
 * Texas Instruments.
 * Richard Woodruff <r-woodruff2@ti.com>
 * Syed Mohammed Khasim <x0khasim@ti.com>
 * Nishanth Menon <nm@ti.com>
 * Tom Rix <Tom.Rix@windriver.com>
 *
 * Configuration settings for the TI OMAP3430 Zoom II board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_ARMCORTEXA8	1	/* This is an ARM V7 CPU core */
#define CONFIG_OMAP		1	/* in a TI OMAP core */
#define CONFIG_OMAP34XX		1	/* which is a 34XX */
#define CONFIG_OMAP3430		1	/* which is in a 3430 */
#define CONFIG_OMAP3_ZOOM2	1	/* working with Zoom II */

#include <asm/arch/cpu.h>	/* get chip and board defs */
#include <asm/arch/omap3.h>

/*
 * Display CPU and Board information
 */
#define CONFIG_DISPLAY_CPUINFO		1
#define CONFIG_DISPLAY_BOARDINFO	1

/* Clock Defines */
#define V_OSCK			26000000	/* Clock output from T2 */
#define V_SCLK			(V_OSCK >> 1)

#undef CONFIG_USE_IRQ		/* no support for IRQs */
#define CONFIG_MISC_INIT_R

#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_INITRD_TAG		1
#define CONFIG_REVISION_TAG		1

/*
 * Size of malloc() pool
 */
#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
						/* Sector */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
#define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for */
						/* initial data */
/*
 * Hardware drivers
 */

/*
 * NS16550 Configuration
 * Zoom2 uses the TL16CP754C on the debug board
 */
#define CONFIG_SERIAL_MULTI		1
/*
 * 0 - 1 : first  USB with respect to the left edge of the debug board
 * 2 - 3 : second USB with respect to the left edge of the debug board
 */
#define ZOOM2_DEFAULT_SERIAL_DEVICE	(&zoom2_serial_device0)

#define V_NS16550_CLK			(1843200)	/* 1.8432 Mhz */

#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_REG_SIZE	(-2)
#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{115200}

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_MMC			1
#define CONFIG_OMAP3_MMC		1
#define CONFIG_DOS_PARTITION		1

/* DDR - I use Micron DDR */
#define CONFIG_OMAP3_MICRON_DDR		1

/* Status LED */
#define CONFIG_STATUS_LED		1 /* Status LED enabled	*/
#define CONFIG_BOARD_SPECIFIC_LED	1
#define STATUS_LED_BLUE			0
#define STATUS_LED_RED			1
/* Blue */
#define STATUS_LED_BIT			STATUS_LED_BLUE
#define STATUS_LED_STATE		STATUS_LED_ON
#define STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 2)
/* Red */
#define STATUS_LED_BIT1			STATUS_LED_RED
#define STATUS_LED_STATE1		STATUS_LED_OFF
#define STATUS_LED_PERIOD1		(CONFIG_SYS_HZ / 2)
/* Optional value */
#define STATUS_LED_BOOT			STATUS_LED_BIT

/* GPIO banks */
#ifdef CONFIG_STATUS_LED
#define CONFIG_OMAP3_GPIO_2 /* ZOOM2_LED_BLUE2 */
#define CONFIG_OMAP3_GPIO_6 /* ZOOM2_LED_RED */
#endif
#define CONFIG_OMAP3_GPIO_3 /* board revision */
#define CONFIG_OMAP3_GPIO_5 /* debug board detection, ZOOM2_LED_BLUE */

/* USB */
#define CONFIG_MUSB_UDC			1
#define CONFIG_USB_OMAP3		1
#define CONFIG_TWL4030_USB		1

/* USB device configuration */
#define CONFIG_USB_DEVICE		1
#define CONFIG_USB_TTY			1
/* Change these to suit your needs */
#define CONFIG_USBD_VENDORID		0x0451
#define CONFIG_USBD_PRODUCTID		0x5678
#define CONFIG_USBD_MANUFACTURER	"Texas Instruments"
#define CONFIG_USBD_PRODUCT_NAME	"Zoom2"

/* commands to include */
#include <config_cmd_default.h>

#define CONFIG_CMD_FAT			/* FAT support			*/
#define CONFIG_CMD_I2C			/* I2C serial bus support	*/
#define CONFIG_CMD_MMC			/* MMC support			*/
#define CONFIG_CMD_NAND			/* NAND support			*/
#define CONFIG_CMD_NAND_LOCK_UNLOCK	/* Enable lock/unlock support	*/

#undef CONFIG_CMD_FLASH			/* flinfo, erase, protect	*/
#undef CONFIG_CMD_FPGA			/* FPGA configuration Support	*/
#undef CONFIG_CMD_IMI			/* iminfo			*/
#undef CONFIG_CMD_IMLS			/* List all found images	*/
#undef CONFIG_CMD_NET			/* bootp, tftpboot, rarpboot	*/
#undef CONFIG_CMD_NFS			/* NFS support			*/

#define CONFIG_SYS_NO_FLASH
#define CONFIG_HARD_I2C			1
#define CONFIG_SYS_I2C_SPEED		100000
#define CONFIG_SYS_I2C_SLAVE		1
#define CONFIG_SYS_I2C_BUS		0
#define CONFIG_SYS_I2C_BUS_SELECT	1
#define CONFIG_DRIVER_OMAP34XX_I2C	1

/*
 * TWL4030
 */
#define CONFIG_TWL4030_POWER		1
#define CONFIG_TWL4030_LED		1

/*
 * Board NAND Info.
 */
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
							/* to access nand */
#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
							/* to access nand at */
							/* CS0 */
#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
#define CONFIG_SYS_MAX_NAND_DEVICE	1

/* Environment information */
#define CONFIG_BOOTDELAY		10

#define CONFIG_EXTRA_ENV_SETTINGS \
	"usbtty=cdc_acm\0" \

/*
 * Miscellaneous configurable options
 */

#define CONFIG_SYS_PROMPT		"OMAP3 Zoom2 # "
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_CBSIZE		256
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					 sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
/* Memtest from start of memory to 31MB */
#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + 0x01F00000)
/* The default load address is the start of memory */
#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)
/* everything, incl board info, in Hz */
#undef CONFIG_SYS_CLKS_IN_HZ
/*
 * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
 * 32KHz clk, or from external sig. This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
#define CONFIG_SYS_PTV			7	/* 2^(PTV+1) */
#define CONFIG_SYS_HZ			((V_SCLK) / (2 << CONFIG_SYS_PTV))

/*-----------------------------------------------------------------------
 * Stack sizes
 *
 * The stack sizes are set up in start.S using these settings
 */
#define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ	(4 << 10)	/* IRQ stack 4 KiB */
#define CONFIG_STACKSIZE_FIQ	(4 << 10)	/* FIQ stack 4 KiB */
#endif

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

/* SDRAM Bank Allocation method */
#define SDRC_R_B_C		1

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */

/* **** PISMO SUPPORT *** */

/* Configure the PISMO */
#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M

#define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors on */
						/* one chip */
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */

#define CONFIG_SYS_FLASH_BASE		boot_flash_base

/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE

#define CONFIG_ENV_IS_IN_NAND		1
#define SMNAND_ENV_OFFSET		0x0c0000 /* environment starts here */

#define CONFIG_SYS_ENV_SECT_SIZE	boot_flash_sec
#define CONFIG_ENV_OFFSET		boot_flash_off
#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET

/*-----------------------------------------------------------------------
 * CFI FLASH driver setup
 */
/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)

#ifndef __ASSEMBLY__
extern unsigned int boot_flash_base;
extern volatile unsigned int boot_flash_env_addr;
extern unsigned int boot_flash_off;
extern unsigned int boot_flash_sec;
extern unsigned int boot_flash_type;
#endif

#endif /* __CONFIG_H */
Commit	Line	Data
376aee78 TR	1	/*
	2	* (C) Copyright 2006-2009
	3	* Texas Instruments.
	4	* Richard Woodruff <r-woodruff2@ti.com>
	5	* Syed Mohammed Khasim <x0khasim@ti.com>
	6	* Nishanth Menon <nm@ti.com>
	7	* Tom Rix <Tom.Rix@windriver.com>
	8	*
	9	* Configuration settings for the TI OMAP3430 Zoom II board.
	10	*
	11	* See file CREDITS for list of people who contributed to this
	12	* project.
	13	*
	14	* This program is free software; you can redistribute it and/or
	15	* modify it under the terms of the GNU General Public License as
	16	* published by the Free Software Foundation; either version 2 of
	17	* the License, or (at your option) any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	27	* MA 02111-1307 USA
	28	*/
	29
	30	#ifndef __CONFIG_H
	31	#define __CONFIG_H
376aee78 TR	32
	33	/*
	34	* High Level Configuration Options
	35	*/
	36	#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
	37	#define CONFIG_OMAP 1 /* in a TI OMAP core */
	38	#define CONFIG_OMAP34XX 1 /* which is a 34XX */
	39	#define CONFIG_OMAP3430 1 /* which is in a 3430 */
	40	#define CONFIG_OMAP3_ZOOM2 1 /* working with Zoom II */
	41
	42	#include <asm/arch/cpu.h> /* get chip and board defs */
	43	#include <asm/arch/omap3.h>
	44
3962c4f9 DB	45	/*
	46	* Display CPU and Board information
	47	*/
	48	#define CONFIG_DISPLAY_CPUINFO 1
	49	#define CONFIG_DISPLAY_BOARDINFO 1
	50
376aee78 TR	51	/* Clock Defines */
	52	#define V_OSCK 26000000 /* Clock output from T2 */
	53	#define V_SCLK (V_OSCK >> 1)
	54
	55	#undef CONFIG_USE_IRQ /* no support for IRQs */
	56	#define CONFIG_MISC_INIT_R
	57
	58	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	59	#define CONFIG_SETUP_MEMORY_TAGS 1
	60	#define CONFIG_INITRD_TAG 1
	61	#define CONFIG_REVISION_TAG 1
	62
	63	/*
	64	* Size of malloc() pool
	65	*/
9c44ddcc	66	#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
376aee78	67	/* Sector */
9c44ddcc	68	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
376aee78 TR	69	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
	70	/* initial data */
	71	/*
	72	* Hardware drivers
	73	*/
	74
	75	/*
	76	* NS16550 Configuration
660888b7	77	* Zoom2 uses the TL16CP754C on the debug board
376aee78	78	*/
660888b7 TR	79	#define CONFIG_SERIAL_MULTI 1
	80	/*
	81	* 0 - 1 : first USB with respect to the left edge of the debug board
	82	* 2 - 3 : second USB with respect to the left edge of the debug board
	83	*/
	84	#define ZOOM2_DEFAULT_SERIAL_DEVICE (&zoom2_serial_device0)
	85
	86	#define V_NS16550_CLK (1843200) /* 1.8432 Mhz */
376aee78 TR	87
376aee78 TR	88	#define CONFIG_SYS_NS16550
660888b7	89	#define CONFIG_SYS_NS16550_REG_SIZE (-2)
376aee78	90	#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
660888b7 TR	91	#define CONFIG_BAUDRATE 115200
660888b7 TR	92	#define CONFIG_SYS_BAUDRATE_TABLE {115200}
376aee78 TR	93
	94	/* allow to overwrite serial and ethaddr */
	95	#define CONFIG_ENV_OVERWRITE
660888b7	96
376aee78 TR	97	#define CONFIG_MMC 1
	98	#define CONFIG_OMAP3_MMC 1
	99	#define CONFIG_DOS_PARTITION 1
	100
30563a04 NM	101	/* DDR - I use Micron DDR */
	102	#define CONFIG_OMAP3_MICRON_DDR 1
	103
83ae698f TR	104	/* Status LED */
	105	#define CONFIG_STATUS_LED 1 /* Status LED enabled */
	106	#define CONFIG_BOARD_SPECIFIC_LED 1
	107	#define STATUS_LED_BLUE 0
	108	#define STATUS_LED_RED 1
	109	/* Blue */
	110	#define STATUS_LED_BIT STATUS_LED_BLUE
	111	#define STATUS_LED_STATE STATUS_LED_ON
	112	#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
	113	/* Red */
	114	#define STATUS_LED_BIT1 STATUS_LED_RED
	115	#define STATUS_LED_STATE1 STATUS_LED_OFF
	116	#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
	117	/* Optional value */
	118	#define STATUS_LED_BOOT STATUS_LED_BIT
	119
0c9520ef TR	120	/* GPIO banks */
	121	#ifdef CONFIG_STATUS_LED
	122	#define CONFIG_OMAP3_GPIO_2 /* ZOOM2_LED_BLUE2 */
	123	#define CONFIG_OMAP3_GPIO_6 /* ZOOM2_LED_RED */
	124	#endif
	125	#define CONFIG_OMAP3_GPIO_3 /* board revision */
	126	#define CONFIG_OMAP3_GPIO_5 /* debug board detection, ZOOM2_LED_BLUE */
	127
2ec1abea TR	128	/* USB */
	129	#define CONFIG_MUSB_UDC 1
	130	#define CONFIG_USB_OMAP3 1
	131	#define CONFIG_TWL4030_USB 1
	132
	133	/* USB device configuration */
	134	#define CONFIG_USB_DEVICE 1
	135	#define CONFIG_USB_TTY 1
	136	/* Change these to suit your needs */
	137	#define CONFIG_USBD_VENDORID 0x0451
	138	#define CONFIG_USBD_PRODUCTID 0x5678
	139	#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
	140	#define CONFIG_USBD_PRODUCT_NAME "Zoom2"
	141
376aee78 TR	142	/* commands to include */
	143	#include <config_cmd_default.h>
	144
	145	#define CONFIG_CMD_FAT /* FAT support */
	146	#define CONFIG_CMD_I2C /* I2C serial bus support */
	147	#define CONFIG_CMD_MMC /* MMC support */
	148	#define CONFIG_CMD_NAND /* NAND support */
	149	#define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */
	150
	151	#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
	152	#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
	153	#undef CONFIG_CMD_IMI /* iminfo */
	154	#undef CONFIG_CMD_IMLS /* List all found images */
	155	#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
	156	#undef CONFIG_CMD_NFS /* NFS support */
	157
	158	#define CONFIG_SYS_NO_FLASH
0297ec7e	159	#define CONFIG_HARD_I2C 1
376aee78 TR	160	#define CONFIG_SYS_I2C_SPEED 100000
	161	#define CONFIG_SYS_I2C_SLAVE 1
	162	#define CONFIG_SYS_I2C_BUS 0
	163	#define CONFIG_SYS_I2C_BUS_SELECT 1
	164	#define CONFIG_DRIVER_OMAP34XX_I2C 1
	165
cd782635 TR	166	/*
	167	* TWL4030
	168	*/
	169	#define CONFIG_TWL4030_POWER 1
2c155130	170	#define CONFIG_TWL4030_LED 1
cd782635	171
376aee78 TR	172	/*
	173	* Board NAND Info.
	174	*/
	175	#define CONFIG_NAND_OMAP_GPMC
	176	#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
	177	/* to access nand */
	178	#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
	179	/* to access nand at */
	180	/* CS0 */
	181	#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
	182	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	183
	184	/* Environment information */
	185	#define CONFIG_BOOTDELAY 10
	186
2ec1abea TR	187	#define CONFIG_EXTRA_ENV_SETTINGS \
	188	"usbtty=cdc_acm\0" \
	189
376aee78 TR	190	/*
	191	* Miscellaneous configurable options
	192	*/
	193
	194	#define CONFIG_SYS_PROMPT "OMAP3 Zoom2 # "
	195	#define CONFIG_SYS_LONGHELP
	196	#define CONFIG_SYS_CBSIZE 256
	197	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	198	sizeof(CONFIG_SYS_PROMPT) + 16)
	199	#define CONFIG_SYS_MAXARGS 16
	200	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	201	/* Memtest from start of memory to 31MB */
	202	#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
	203	#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + 0x01F00000)
	204	/* The default load address is the start of memory */
	205	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
	206	/* everything, incl board info, in Hz */
	207	#undef CONFIG_SYS_CLKS_IN_HZ
	208	/*
	209	* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
	210	* 32KHz clk, or from external sig. This rate is divided by a local divisor.
	211	*/
	212	#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
	213	#define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */
	214	#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PTV))
	215
	216	/*-----------------------------------------------------------------------
	217	* Stack sizes
	218	*
	219	* The stack sizes are set up in start.S using these settings
	220	*/
9c44ddcc	221	#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
376aee78	222	#ifdef CONFIG_USE_IRQ
9c44ddcc SP	223	#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
9c44ddcc SP	224	#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
376aee78 TR	225	#endif
	226
	227	/*-----------------------------------------------------------------------
	228	* Physical Memory Map
	229	*/
	230	#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
	231	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
9c44ddcc	232	#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
376aee78 TR	233	#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
	234
	235	/* SDRAM Bank Allocation method */
	236	#define SDRC_R_B_C 1
	237
	238	/*-----------------------------------------------------------------------
	239	* FLASH and environment organization
	240	*/
	241
	242	/* ** PISMO SUPPORT * */
	243
	244	/* Configure the PISMO */
	245	#define PISMO1_NAND_SIZE GPMC_SIZE_128M
	246	#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
	247
	248	#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */
	249	/* one chip */
	250	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
9c44ddcc	251	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
376aee78 TR	252
	253	#define CONFIG_SYS_FLASH_BASE boot_flash_base
	254
	255	/* Monitor at start of flash */
	256	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	257
	258	#define CONFIG_ENV_IS_IN_NAND 1
	259	#define SMNAND_ENV_OFFSET 0x0c0000 /* environment starts here */
	260
	261	#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
	262	#define CONFIG_ENV_OFFSET boot_flash_off
	263	#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
	264
	265	/*-----------------------------------------------------------------------
	266	* CFI FLASH driver setup
	267	*/
	268	/* timeout values are in ticks */
	269	#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
	270	#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
	271
	272	#ifndef __ASSEMBLY__
376aee78 TR	273	extern unsigned int boot_flash_base;
	274	extern volatile unsigned int boot_flash_env_addr;
	275	extern unsigned int boot_flash_off;
	276	extern unsigned int boot_flash_sec;
	277	extern unsigned int boot_flash_type;
	278	#endif
	279
	280	#endif /* __CONFIG_H */