[people/ms/u-boot.git] / include / configs / omap3_zoom2.h

/*
 * (C) Copyright 2006-2009
 * Texas Instruments.
 * Richard Woodruff <r-woodruff2@ti.com>
 * Syed Mohammed Khasim <x0khasim@ti.com>
 * Nishanth Menon <nm@ti.com>
 * Tom Rix <Tom.Rix@windriver.com>
 *
 * Configuration settings for the TI OMAP3430 Zoom II board.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_OMAP		1	/* in a TI OMAP core */
#define CONFIG_OMAP34XX		1	/* which is a 34XX */
#define CONFIG_OMAP3_ZOOM2	1	/* working with Zoom II */
#define CONFIG_OMAP_GPIO
#define CONFIG_OMAP_COMMON

#define CONFIG_SDRC	/* The chip has SDRC controller */

#include <asm/arch/cpu.h>	/* get chip and board defs */
#include <asm/arch/omap3.h>

/*
 * Display CPU and Board information
 */
#define CONFIG_DISPLAY_CPUINFO		1
#define CONFIG_DISPLAY_BOARDINFO	1

/* Clock Defines */
#define V_OSCK			26000000	/* Clock output from T2 */
#define V_SCLK			(V_OSCK >> 1)

#define CONFIG_MISC_INIT_R

#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_INITRD_TAG		1
#define CONFIG_REVISION_TAG		1

#define CONFIG_OF_LIBFDT		1

/*
 * Size of malloc() pool
 */
#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
						/* Sector */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
/*
 * Hardware drivers
 */

/*
 * NS16550 Configuration
 * Zoom2 uses the TL16CP754C on the debug board
 */
/*
 * 0 - 1 : first  USB with respect to the left edge of the debug board
 * 2 - 3 : second USB with respect to the left edge of the debug board
 */
#define ZOOM2_DEFAULT_SERIAL_DEVICE	0

#define V_NS16550_CLK			(1843200)	/* 1.8432 Mhz */

#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_REG_SIZE	(-2)
#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{115200}

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_GENERIC_MMC		1
#define CONFIG_MMC			1
#define CONFIG_OMAP_HSMMC		1
#define CONFIG_DOS_PARTITION		1

/* Status LED */
#define CONFIG_STATUS_LED		1 /* Status LED enabled	*/
#define CONFIG_BOARD_SPECIFIC_LED	1
#define STATUS_LED_BLUE			0
#define STATUS_LED_RED			1
/* Blue */
#define STATUS_LED_BIT			STATUS_LED_BLUE
#define STATUS_LED_STATE		STATUS_LED_ON
#define STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 2)
/* Red */
#define STATUS_LED_BIT1			STATUS_LED_RED
#define STATUS_LED_STATE1		STATUS_LED_OFF
#define STATUS_LED_PERIOD1		(CONFIG_SYS_HZ / 2)
/* Optional value */
#define STATUS_LED_BOOT			STATUS_LED_BIT

/* GPIO banks */
#ifdef CONFIG_STATUS_LED
#define CONFIG_OMAP3_GPIO_2 /* ZOOM2_LED_BLUE2 */
#define CONFIG_OMAP3_GPIO_6 /* ZOOM2_LED_RED */
#endif
#define CONFIG_OMAP3_GPIO_3 /* board revision */
#define CONFIG_OMAP3_GPIO_5 /* debug board detection, ZOOM2_LED_BLUE */

/* USB */
#define CONFIG_MUSB_UDC			1
#define CONFIG_USB_OMAP3		1
#define CONFIG_TWL4030_USB		1

/* USB device configuration */
#define CONFIG_USB_DEVICE		1
#define CONFIG_USB_TTY			1
/* Change these to suit your needs */
#define CONFIG_USBD_VENDORID		0x0451
#define CONFIG_USBD_PRODUCTID		0x5678
#define CONFIG_USBD_MANUFACTURER	"Texas Instruments"
#define CONFIG_USBD_PRODUCT_NAME	"Zoom2"

/* commands to include */
#include <config_cmd_default.h>

#define CONFIG_CMD_FAT			/* FAT support			*/
#define CONFIG_CMD_I2C			/* I2C serial bus support	*/
#define CONFIG_CMD_MMC			/* MMC support			*/
#define CONFIG_CMD_NAND			/* NAND support			*/
#define CONFIG_CMD_NAND_LOCK_UNLOCK	/* Enable lock/unlock support	*/

#undef CONFIG_CMD_FLASH			/* flinfo, erase, protect	*/
#undef CONFIG_CMD_FPGA			/* FPGA configuration Support	*/
#undef CONFIG_CMD_IMI			/* iminfo			*/
#undef CONFIG_CMD_IMLS			/* List all found images	*/
#undef CONFIG_CMD_NET			/* bootp, tftpboot, rarpboot	*/
#undef CONFIG_CMD_NFS			/* NFS support			*/

#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_I2C
#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
#define CONFIG_SYS_I2C_OMAP34XX

/*
 * TWL4030
 */
#define CONFIG_TWL4030_POWER		1
#define CONFIG_TWL4030_LED		1

/*
 * Board NAND Info.
 */
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
							/* to access nand */
#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
							/* to access nand at */
							/* CS0 */
#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
#define CONFIG_SYS_MAX_NAND_DEVICE	1

/* Environment information */
#define CONFIG_BOOTDELAY		10

#define CONFIG_EXTRA_ENV_SETTINGS \
	"usbtty=cdc_acm\0" \

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE	0x800
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - \
					 GENERATED_GBL_DATA_SIZE)
/*
 * Miscellaneous configurable options
 */

#define CONFIG_SYS_PROMPT		"OMAP3 Zoom2 # "
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_CBSIZE		512
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					 sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
/* Memtest from start of memory to 31MB */
#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + 0x01F00000)
/* The default load address is the start of memory */
#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)
/* everything, incl board info, in Hz */
#undef CONFIG_SYS_CLKS_IN_HZ
/*
 * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
 * 32KHz clk, or from external sig. This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
#define CONFIG_SYS_PTV			7	/* 2^(PTV+1) */
#define CONFIG_SYS_HZ			((V_SCLK) / (2 << CONFIG_SYS_PTV))

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */

/* **** PISMO SUPPORT *** */

/* Configure the PISMO */
#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M

#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */

#if defined(CONFIG_CMD_NAND)
#define CONFIG_SYS_FLASH_BASE		PISMO1_NAND_BASE
#endif

/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE

#define CONFIG_ENV_IS_IN_NAND		1
#define SMNAND_ENV_OFFSET		0x0c0000 /* environment starts here */

#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET

#define CONFIG_SYS_CACHELINE_SIZE	64

#endif /* __CONFIG_H */
Commit	Line	Data
376aee78 TR	1	/*
	2	* (C) Copyright 2006-2009
	3	* Texas Instruments.
	4	* Richard Woodruff <r-woodruff2@ti.com>
	5	* Syed Mohammed Khasim <x0khasim@ti.com>
	6	* Nishanth Menon <nm@ti.com>
	7	* Tom Rix <Tom.Rix@windriver.com>
	8	*
	9	* Configuration settings for the TI OMAP3430 Zoom II board.
	10	*
1a459660	11	* SPDX-License-Identifier: GPL-2.0+
376aee78 TR	12	*/
	13
	14	#ifndef __CONFIG_H
	15	#define __CONFIG_H
376aee78 TR	16
	17	/*
	18	* High Level Configuration Options
	19	*/
376aee78 TR	20	#define CONFIG_OMAP 1 /* in a TI OMAP core */
376aee78 TR	21	#define CONFIG_OMAP34XX 1 /* which is a 34XX */
376aee78	22	#define CONFIG_OMAP3_ZOOM2 1 /* working with Zoom II */
308252ad	23	#define CONFIG_OMAP_GPIO
806d2792	24	#define CONFIG_OMAP_COMMON
376aee78	25
cae377b5 VH	26	#define CONFIG_SDRC /* The chip has SDRC controller */
cae377b5 VH	27
376aee78 TR	28	#include <asm/arch/cpu.h> /* get chip and board defs */
	29	#include <asm/arch/omap3.h>
	30
3962c4f9 DB	31	/*
	32	* Display CPU and Board information
	33	*/
	34	#define CONFIG_DISPLAY_CPUINFO 1
	35	#define CONFIG_DISPLAY_BOARDINFO 1
	36
376aee78 TR	37	/* Clock Defines */
	38	#define V_OSCK 26000000 /* Clock output from T2 */
	39	#define V_SCLK (V_OSCK >> 1)
	40
376aee78 TR	41	#define CONFIG_MISC_INIT_R
	42
	43	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	44	#define CONFIG_SETUP_MEMORY_TAGS 1
	45	#define CONFIG_INITRD_TAG 1
	46	#define CONFIG_REVISION_TAG 1
	47
2fa8ca98 GL	48	#define CONFIG_OF_LIBFDT 1
2fa8ca98 GL	49
376aee78 TR	50	/*
	51	* Size of malloc() pool
	52	*/
9c44ddcc	53	#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
376aee78	54	/* Sector */
9c44ddcc	55	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
376aee78 TR	56	/*
	57	* Hardware drivers
	58	*/
	59
	60	/*
	61	* NS16550 Configuration
660888b7	62	* Zoom2 uses the TL16CP754C on the debug board
376aee78	63	*/
660888b7 TR	64	/*
	65	* 0 - 1 : first USB with respect to the left edge of the debug board
	66	* 2 - 3 : second USB with respect to the left edge of the debug board
	67	*/
425101e1	68	#define ZOOM2_DEFAULT_SERIAL_DEVICE 0
660888b7 TR	69
660888b7 TR	70	#define V_NS16550_CLK (1843200) /* 1.8432 Mhz */
376aee78 TR	71
376aee78 TR	72	#define CONFIG_SYS_NS16550
660888b7	73	#define CONFIG_SYS_NS16550_REG_SIZE (-2)
376aee78	74	#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
660888b7 TR	75	#define CONFIG_BAUDRATE 115200
660888b7 TR	76	#define CONFIG_SYS_BAUDRATE_TABLE {115200}
376aee78 TR	77
	78	/* allow to overwrite serial and ethaddr */
	79	#define CONFIG_ENV_OVERWRITE
660888b7	80
cfc4384c	81	#define CONFIG_GENERIC_MMC 1
376aee78	82	#define CONFIG_MMC 1
cfc4384c	83	#define CONFIG_OMAP_HSMMC 1
376aee78	84	#define CONFIG_DOS_PARTITION 1
30563a04	85
83ae698f TR	86	/* Status LED */
	87	#define CONFIG_STATUS_LED 1 /* Status LED enabled */
	88	#define CONFIG_BOARD_SPECIFIC_LED 1
	89	#define STATUS_LED_BLUE 0
	90	#define STATUS_LED_RED 1
	91	/* Blue */
	92	#define STATUS_LED_BIT STATUS_LED_BLUE
	93	#define STATUS_LED_STATE STATUS_LED_ON
	94	#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
	95	/* Red */
	96	#define STATUS_LED_BIT1 STATUS_LED_RED
	97	#define STATUS_LED_STATE1 STATUS_LED_OFF
	98	#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
	99	/* Optional value */
	100	#define STATUS_LED_BOOT STATUS_LED_BIT
	101
0c9520ef TR	102	/* GPIO banks */
	103	#ifdef CONFIG_STATUS_LED
	104	#define CONFIG_OMAP3_GPIO_2 /* ZOOM2_LED_BLUE2 */
	105	#define CONFIG_OMAP3_GPIO_6 /* ZOOM2_LED_RED */
	106	#endif
	107	#define CONFIG_OMAP3_GPIO_3 /* board revision */
	108	#define CONFIG_OMAP3_GPIO_5 /* debug board detection, ZOOM2_LED_BLUE */
	109
2ec1abea TR	110	/* USB */
	111	#define CONFIG_MUSB_UDC 1
	112	#define CONFIG_USB_OMAP3 1
	113	#define CONFIG_TWL4030_USB 1
	114
	115	/* USB device configuration */
	116	#define CONFIG_USB_DEVICE 1
	117	#define CONFIG_USB_TTY 1
	118	/* Change these to suit your needs */
	119	#define CONFIG_USBD_VENDORID 0x0451
	120	#define CONFIG_USBD_PRODUCTID 0x5678
	121	#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
	122	#define CONFIG_USBD_PRODUCT_NAME "Zoom2"
	123
376aee78 TR	124	/* commands to include */
	125	#include <config_cmd_default.h>
	126
	127	#define CONFIG_CMD_FAT /* FAT support */
	128	#define CONFIG_CMD_I2C /* I2C serial bus support */
	129	#define CONFIG_CMD_MMC /* MMC support */
	130	#define CONFIG_CMD_NAND /* NAND support */
	131	#define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */
	132
	133	#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
	134	#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
	135	#undef CONFIG_CMD_IMI /* iminfo */
	136	#undef CONFIG_CMD_IMLS /* List all found images */
	137	#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
	138	#undef CONFIG_CMD_NFS /* NFS support */
	139
	140	#define CONFIG_SYS_NO_FLASH
6789e84e HS	141	#define CONFIG_SYS_I2C
	142	#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
	143	#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
	144	#define CONFIG_SYS_I2C_OMAP34XX
376aee78	145
cd782635 TR	146	/*
	147	* TWL4030
	148	*/
	149	#define CONFIG_TWL4030_POWER 1
2c155130	150	#define CONFIG_TWL4030_LED 1
cd782635	151
376aee78 TR	152	/*
	153	* Board NAND Info.
	154	*/
	155	#define CONFIG_NAND_OMAP_GPMC
	156	#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
	157	/* to access nand */
	158	#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
	159	/* to access nand at */
	160	/* CS0 */
	161	#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
	162	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	163
	164	/* Environment information */
	165	#define CONFIG_BOOTDELAY 10
	166
2ec1abea TR	167	#define CONFIG_EXTRA_ENV_SETTINGS \
	168	"usbtty=cdc_acm\0" \
	169
998f4caf DB	170	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	171	#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
	172	#define CONFIG_SYS_INIT_RAM_SIZE 0x800
	173	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	174	CONFIG_SYS_INIT_RAM_SIZE - \
	175	GENERATED_GBL_DATA_SIZE)
376aee78 TR	176	/*
	177	* Miscellaneous configurable options
	178	*/
	179
	180	#define CONFIG_SYS_PROMPT "OMAP3 Zoom2 # "
	181	#define CONFIG_SYS_LONGHELP
f62b1257	182	#define CONFIG_SYS_CBSIZE 512
376aee78 TR	183	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	184	sizeof(CONFIG_SYS_PROMPT) + 16)
	185	#define CONFIG_SYS_MAXARGS 16
	186	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	187	/* Memtest from start of memory to 31MB */
	188	#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
	189	#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + 0x01F00000)
	190	/* The default load address is the start of memory */
	191	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
	192	/* everything, incl board info, in Hz */
	193	#undef CONFIG_SYS_CLKS_IN_HZ
	194	/*
	195	* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
	196	* 32KHz clk, or from external sig. This rate is divided by a local divisor.
	197	*/
	198	#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
	199	#define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */
	200	#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PTV))
	201
376aee78 TR	202	/*-----------------------------------------------------------------------
	203	* Physical Memory Map
	204	*/
	205	#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
	206	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
376aee78 TR	207	#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
376aee78 TR	208
376aee78 TR	209	/*-----------------------------------------------------------------------
	210	* FLASH and environment organization
	211	*/
	212
	213	/* ** PISMO SUPPORT * */
	214
	215	/* Configure the PISMO */
	216	#define PISMO1_NAND_SIZE GPMC_SIZE_128M
	217	#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
	218
9c44ddcc	219	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
376aee78	220
6cbec7b3 LC	221	#if defined(CONFIG_CMD_NAND)
	222	#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
	223	#endif
376aee78 TR	224
	225	/* Monitor at start of flash */
	226	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	227
	228	#define CONFIG_ENV_IS_IN_NAND 1
	229	#define SMNAND_ENV_OFFSET 0x0c0000 /* environment starts here */
	230
6cbec7b3 LC	231	#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
6cbec7b3 LC	232	#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
376aee78 TR	233	#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
376aee78 TR	234
8e40852f A	235	#define CONFIG_SYS_CACHELINE_SIZE 64
8e40852f A	236
376aee78	237	#endif /* __CONFIG_H */