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a56bd922 | 1 | /* |
1eaeb58e | 2 | * (C) Copyright 2003-2004 |
a56bd922 WD |
3 | * MPC Data Limited (http://www.mpc-data.co.uk) |
4 | * Dave Peverley <dpeverley at mpc-data.co.uk> | |
5 | * | |
6 | * Configuation settings for the TI OMAP Perseus 2 board. | |
7 | * | |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
1eaeb58e | 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
a56bd922 WD |
19 | * GNU General Public License for more details. |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | * MA 02111-1307 USA | |
25 | */ | |
26 | ||
27 | #ifndef __CONFIG_H | |
28 | #define __CONFIG_H | |
29 | ||
a56bd922 WD |
30 | /* allow to overwrite serial and ethaddr */ |
31 | #define CONFIG_ENV_OVERWRITE | |
32 | ||
a56bd922 WD |
33 | /* |
34 | * High Level Configuration Options | |
35 | * (easy to change) | |
36 | */ | |
37 | ||
1eaeb58e WD |
38 | #define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */ |
39 | #define CONFIG_OMAP 1 /* in a TI OMAP core */ | |
40 | #define CONFIG_OMAP730 1 /* which is in a 730 */ | |
41 | #define CONFIG_P2_OMAP730 1 /* a Perseus 2 Board */ | |
a56bd922 | 42 | |
1eaeb58e WD |
43 | /* |
44 | * Input clock of PLL | |
45 | * The OMAP730 Perseus 2 has 13MHz input clock | |
a56bd922 WD |
46 | */ |
47 | ||
1eaeb58e | 48 | #define CONFIG_SYS_CLK_FREQ 13000000 |
a56bd922 | 49 | |
1eaeb58e | 50 | #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ |
a56bd922 | 51 | |
1eaeb58e | 52 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
a56bd922 WD |
53 | #define CONFIG_SETUP_MEMORY_TAGS 1 |
54 | ||
a56bd922 WD |
55 | /* |
56 | * Size of malloc() pool | |
57 | */ | |
58 | ||
6d0f6bcf | 59 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) |
a56bd922 WD |
60 | |
61 | /* | |
62 | * Hardware drivers | |
63 | */ | |
64 | ||
ac6b362a | 65 | #define CONFIG_LAN91C96 |
1eaeb58e | 66 | #define CONFIG_LAN91C96_BASE 0x04000300 |
a56bd922 WD |
67 | #define CONFIG_LAN91C96_EXT_PHY |
68 | ||
a56bd922 WD |
69 | /* |
70 | * NS16550 Configuration | |
71 | */ | |
72 | ||
6d0f6bcf JCPV |
73 | #define CONFIG_SYS_NS16550 |
74 | #define CONFIG_SYS_NS16550_SERIAL | |
75 | #define CONFIG_SYS_NS16550_REG_SIZE (1) | |
76 | #define CONFIG_SYS_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */ | |
77 | #define CONFIG_SYS_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart | |
1eaeb58e | 78 | * on perseus */ |
a56bd922 WD |
79 | |
80 | /* | |
81 | * select serial console configuration | |
82 | */ | |
83 | ||
1eaeb58e | 84 | #define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP730 Perseus 2 */ |
a56bd922 | 85 | |
1eaeb58e WD |
86 | #define CONFIG_CONS_INDEX 1 |
87 | #define CONFIG_BAUDRATE 115200 | |
a56bd922 | 88 | |
1eaeb58e | 89 | /* |
a5cb2309 | 90 | * Command line configuration. |
a56bd922 | 91 | */ |
a5cb2309 JL |
92 | #include <config_cmd_default.h> |
93 | ||
94 | #define CONFIG_CMD_DHCP | |
95 | ||
96 | ||
d3b8c1a7 JL |
97 | /* |
98 | * BOOTP options | |
99 | */ | |
100 | #define CONFIG_BOOTP_SUBNETMASK | |
101 | #define CONFIG_BOOTP_GATEWAY | |
102 | #define CONFIG_BOOTP_HOSTNAME | |
103 | #define CONFIG_BOOTP_BOOTPATH | |
104 | ||
a56bd922 | 105 | |
a56bd922 WD |
106 | #include <configs/omap730.h> |
107 | #include <configs/h2_p2_dbg_board.h> | |
108 | ||
1eaeb58e WD |
109 | #define CONFIG_BOOTDELAY 3 |
110 | #define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw ip=bootp" | |
a56bd922 | 111 | |
1eaeb58e | 112 | #define CONFIG_LOADADDR 0x10000000 |
a56bd922 WD |
113 | |
114 | #define CONFIG_ETHADDR | |
1eaeb58e WD |
115 | #define CONFIG_NETMASK 255.255.255.0 |
116 | #define CONFIG_IPADDR 192.168.0.23 | |
117 | #define CONFIG_SERVERIP 192.150.0.100 | |
118 | #define CONFIG_BOOTFILE "uImage" /* File to load */ | |
a56bd922 | 119 | |
a5cb2309 | 120 | #if defined(CONFIG_CMD_KGDB) |
1eaeb58e WD |
121 | #define CONFIG_KGDB_BAUDRATE 115200 /* Speed to run kgdb serial port */ |
122 | #define CONFIG_KGDB_SER_INDEX 1 /* Which serial port to use */ | |
a56bd922 WD |
123 | #endif |
124 | ||
a56bd922 WD |
125 | /* |
126 | * Miscellaneous configurable options | |
127 | */ | |
128 | ||
6d0f6bcf JCPV |
129 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
130 | #define CONFIG_SYS_PROMPT "OMAP730 P2 # " /* Monitor Command Prompt */ | |
131 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
a56bd922 | 132 | /* Print Buffer Size */ |
6d0f6bcf JCPV |
133 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
134 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
135 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
a56bd922 | 136 | |
6d0f6bcf JCPV |
137 | #define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */ |
138 | #define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ | |
a56bd922 | 139 | |
6d0f6bcf | 140 | #define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */ |
a56bd922 | 141 | |
1eaeb58e WD |
142 | /* The OMAP730 has 3 general purpose MPU timers, they can be driven by |
143 | * the RefClk (12Mhz) or by DPLL1. This time is further subdivided by a | |
a56bd922 WD |
144 | * local divisor. |
145 | */ | |
81472d89 LM |
146 | #define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */ |
147 | #define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */ | |
148 | #define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV)) | |
a56bd922 WD |
149 | |
150 | /*----------------------------------------------------------------------- | |
151 | * Stack sizes | |
152 | * | |
153 | * The stack sizes are set up in start.S using the settings below | |
154 | */ | |
155 | ||
1eaeb58e | 156 | #define CONFIG_STACKSIZE (128*1024) /* regular stack */ |
a56bd922 | 157 | #ifdef CONFIG_USE_IRQ |
1eaeb58e WD |
158 | #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ |
159 | #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ | |
a56bd922 WD |
160 | #endif |
161 | ||
a56bd922 WD |
162 | /*----------------------------------------------------------------------- |
163 | * Physical Memory Map | |
164 | */ | |
165 | ||
1eaeb58e WD |
166 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
167 | #define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ | |
168 | #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ | |
a56bd922 WD |
169 | |
170 | #if defined(CONFIG_CS0_BOOT) | |
1eaeb58e | 171 | #define PHYS_FLASH_1 0x0C000000 |
a56bd922 | 172 | #elif defined(CONFIG_CS3_BOOT) |
1eaeb58e | 173 | #define PHYS_FLASH_1 0x00000000 |
a56bd922 WD |
174 | #else |
175 | #error Unknown Boot Chip-Select number | |
176 | #endif | |
177 | ||
154f5348 A |
178 | #define PHYS_SRAM 0x20000000 |
179 | ||
6d0f6bcf | 180 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
a56bd922 WD |
181 | |
182 | /*----------------------------------------------------------------------- | |
183 | * FLASH and environment organization | |
184 | */ | |
185 | ||
6d0f6bcf | 186 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
1eaeb58e | 187 | #define PHYS_FLASH_SIZE 0x02000000 /* 32MB */ |
6d0f6bcf | 188 | #define CONFIG_SYS_MAX_FLASH_SECT (259) /* max number of sectors on one chip */ |
a56bd922 | 189 | /* addr of environment */ |
6d0f6bcf | 190 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x020000) |
a56bd922 WD |
191 | |
192 | /* timeout values are in ticks */ | |
6d0f6bcf JCPV |
193 | #define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ |
194 | #define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */ | |
a56bd922 | 195 | |
5a1aceb0 | 196 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
197 | #define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ |
198 | #define CONFIG_ENV_OFFSET 0x20000 /* environment starts here */ | |
a56bd922 | 199 | |
154f5348 A |
200 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
201 | #define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM | |
202 | ||
1eaeb58e | 203 | #endif /* ! __CONFIG_H */ |