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a868e443 PH |
1 | /* |
2 | * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ | |
3 | * | |
4 | * Based on davinci_dvevm.h. Original Copyrights follow: | |
5 | * | |
6 | * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> | |
7 | * | |
5b8031cc | 8 | * SPDX-License-Identifier: GPL-2.0 |
a868e443 PH |
9 | */ |
10 | ||
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
14 | /* | |
15 | * Board | |
16 | */ | |
17 | #define CONFIG_DRIVER_TI_EMAC | |
18 | #undef CONFIG_USE_SPIFLASH | |
19 | #undef CONFIG_SYS_USE_NOR | |
20 | #define CONFIG_USE_NAND | |
21 | ||
22 | /* | |
23 | * SoC Configuration | |
24 | */ | |
25 | #define CONFIG_MACH_OMAPL138_LCDK | |
26 | #define CONFIG_ARM926EJS /* arm926ejs CPU core */ | |
27 | #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ | |
28 | #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) | |
29 | #define CONFIG_SYS_OSCIN_FREQ 24000000 | |
30 | #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE | |
31 | #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) | |
32 | #define CONFIG_SYS_HZ 1000 | |
33 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
34 | #define CONFIG_SYS_TEXT_BASE 0xc1080000 | |
35 | ||
36 | /* | |
37 | * Memory Info | |
38 | */ | |
39 | #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ | |
40 | #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ | |
41 | #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ | |
42 | #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ | |
43 | ||
44 | /* memtest start addr */ | |
45 | #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) | |
46 | ||
47 | /* memtest will be run on 16MB */ | |
48 | #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024) | |
49 | ||
50 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ | |
a868e443 PH |
51 | |
52 | #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ | |
53 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ | |
54 | DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ | |
55 | DAVINCI_SYSCFG_SUSPSRC_UART2 | \ | |
56 | DAVINCI_SYSCFG_SUSPSRC_EMAC | \ | |
57 | DAVINCI_SYSCFG_SUSPSRC_I2C) | |
58 | ||
59 | /* | |
60 | * PLL configuration | |
61 | */ | |
62 | #define CONFIG_SYS_DV_CLKMODE 0 | |
63 | #define CONFIG_SYS_DA850_PLL0_POSTDIV 1 | |
64 | #define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000 | |
65 | #define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001 | |
66 | #define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 | |
67 | #define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003 | |
68 | #define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002 | |
69 | #define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1 | |
70 | #define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005 | |
71 | ||
72 | #define CONFIG_SYS_DA850_PLL1_POSTDIV 1 | |
73 | #define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000 | |
74 | #define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001 | |
75 | #define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8003 | |
76 | ||
1601dd97 | 77 | #define CONFIG_SYS_DA850_PLL0_PLLM 37 |
a868e443 PH |
78 | #define CONFIG_SYS_DA850_PLL1_PLLM 21 |
79 | ||
a5ab44f6 FP |
80 | /* |
81 | * DDR2 memory configuration | |
82 | */ | |
83 | #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ | |
84 | DV_DDR_PHY_EXT_STRBEN | \ | |
85 | (0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT)) | |
86 | ||
87 | #define CONFIG_SYS_DA850_DDR2_SDBCR ( \ | |
88 | (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \ | |
89 | (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ | |
90 | (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ | |
91 | (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ | |
92 | (4 << DV_DDR_SDCR_CL_SHIFT) | \ | |
93 | (3 << DV_DDR_SDCR_IBANK_SHIFT) | \ | |
94 | (2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) | |
95 | ||
96 | /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ | |
97 | #define CONFIG_SYS_DA850_DDR2_SDBCR2 0 | |
98 | ||
99 | #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ | |
100 | (19 << DV_DDR_SDTMR1_RFC_SHIFT) | \ | |
101 | (1 << DV_DDR_SDTMR1_RP_SHIFT) | \ | |
102 | (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \ | |
103 | (2 << DV_DDR_SDTMR1_WR_SHIFT) | \ | |
104 | (6 << DV_DDR_SDTMR1_RAS_SHIFT) | \ | |
105 | (8 << DV_DDR_SDTMR1_RC_SHIFT) | \ | |
106 | (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ | |
107 | (1 << DV_DDR_SDTMR1_WTR_SHIFT)) | |
108 | ||
109 | #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ | |
110 | (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ | |
111 | (2 << DV_DDR_SDTMR2_XP_SHIFT) | \ | |
112 | (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ | |
264e420f | 113 | (20 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ |
a5ab44f6 FP |
114 | (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ |
115 | (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \ | |
116 | (2 << DV_DDR_SDTMR2_CKE_SHIFT)) | |
117 | ||
118 | #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000492 | |
119 | #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 | |
120 | ||
a868e443 PH |
121 | /* |
122 | * Serial Driver info | |
123 | */ | |
a868e443 PH |
124 | #define CONFIG_SYS_NS16550_SERIAL |
125 | #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ | |
126 | #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ | |
127 | #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) | |
128 | #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ | |
a868e443 PH |
129 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
130 | ||
131 | #define CONFIG_SPI | |
a868e443 PH |
132 | #define CONFIG_DAVINCI_SPI |
133 | #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE | |
134 | #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) | |
135 | #define CONFIG_SF_DEFAULT_SPEED 30000000 | |
136 | #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED | |
137 | ||
138 | #ifdef CONFIG_USE_SPIFLASH | |
a868e443 PH |
139 | #define CONFIG_SPL_SPI_LOAD |
140 | #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 | |
141 | #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x30000 | |
142 | #endif | |
143 | ||
144 | /* | |
145 | * I2C Configuration | |
146 | */ | |
147 | #define CONFIG_SYS_I2C | |
148 | #define CONFIG_SYS_I2C_DAVINCI | |
149 | #define CONFIG_SYS_DAVINCI_I2C_SPEED 25000 | |
150 | #define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ | |
151 | #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 | |
152 | ||
153 | /* | |
154 | * Flash & Environment | |
155 | */ | |
156 | #ifdef CONFIG_USE_NAND | |
a868e443 | 157 | #define CONFIG_NAND_DAVINCI |
a868e443 PH |
158 | #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ |
159 | #define CONFIG_ENV_SIZE (128 << 9) | |
160 | #define CONFIG_SYS_NAND_USE_FLASH_BBT | |
161 | #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST | |
162 | #define CONFIG_SYS_NAND_PAGE_2K | |
a868e443 PH |
163 | #define CONFIG_SYS_NAND_CS 3 |
164 | #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE | |
1dbab274 | 165 | #define CONFIG_SYS_NAND_MASK_CLE 0x10 |
ef044796 | 166 | #define CONFIG_SYS_NAND_MASK_ALE 0x8 |
a868e443 PH |
167 | #undef CONFIG_SYS_NAND_HW_ECC |
168 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ | |
c69a05d0 | 169 | #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST |
2b2cab24 | 170 | #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC |
c69a05d0 FP |
171 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE |
172 | #define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) | |
173 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) | |
c0c10449 | 174 | #define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K |
c69a05d0 FP |
175 | #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 |
176 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST | |
177 | #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \ | |
178 | CONFIG_SYS_NAND_U_BOOT_SIZE - \ | |
179 | CONFIG_SYS_MALLOC_LEN - \ | |
180 | GENERATED_GBL_DATA_SIZE) | |
181 | #define CONFIG_SYS_NAND_ECCPOS { \ | |
2b2cab24 FP |
182 | 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ |
183 | 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \ | |
184 | 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ | |
185 | 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 } | |
c69a05d0 FP |
186 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 |
187 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 | |
188 | #define CONFIG_SYS_NAND_ECCSIZE 512 | |
189 | #define CONFIG_SYS_NAND_ECCBYTES 10 | |
190 | #define CONFIG_SYS_NAND_OOBSIZE 64 | |
191 | #define CONFIG_SPL_NAND_BASE | |
192 | #define CONFIG_SPL_NAND_DRIVERS | |
193 | #define CONFIG_SPL_NAND_ECC | |
c69a05d0 | 194 | #define CONFIG_SPL_NAND_LOAD |
a868e443 PH |
195 | #endif |
196 | ||
197 | #ifdef CONFIG_SYS_USE_NOR | |
a868e443 PH |
198 | #define CONFIG_FLASH_CFI_DRIVER |
199 | #define CONFIG_SYS_FLASH_CFI | |
200 | #define CONFIG_SYS_FLASH_PROTECTION | |
201 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ | |
202 | #define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */ | |
203 | #define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3) | |
204 | #define CONFIG_ENV_SIZE (128 << 10) | |
205 | #define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE | |
206 | #define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */ | |
207 | #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\ | |
208 | + 3) | |
209 | #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ | |
210 | #endif | |
211 | ||
212 | #ifdef CONFIG_USE_SPIFLASH | |
a868e443 PH |
213 | #define CONFIG_ENV_SIZE (64 << 10) |
214 | #define CONFIG_ENV_OFFSET (256 << 10) | |
215 | #define CONFIG_ENV_SECT_SIZE (64 << 10) | |
a868e443 PH |
216 | #endif |
217 | ||
218 | /* | |
219 | * Network & Ethernet Configuration | |
220 | */ | |
221 | #ifdef CONFIG_DRIVER_TI_EMAC | |
a868e443 PH |
222 | #define CONFIG_MII |
223 | #undef CONFIG_DRIVER_TI_EMAC_USE_RMII | |
224 | #define CONFIG_BOOTP_DEFAULT | |
225 | #define CONFIG_BOOTP_DNS | |
226 | #define CONFIG_BOOTP_DNS2 | |
227 | #define CONFIG_BOOTP_SEND_HOSTNAME | |
228 | #define CONFIG_NET_RETRY_COUNT 10 | |
a868e443 PH |
229 | #endif |
230 | ||
231 | /* | |
232 | * U-Boot general configuration | |
233 | */ | |
a868e443 | 234 | #define CONFIG_MISC_INIT_R |
963ed6f3 | 235 | #define CONFIG_BOOTFILE "zImage" /* Boot file name */ |
a868e443 | 236 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
a868e443 PH |
237 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ |
238 | #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) | |
a868e443 | 239 | #define CONFIG_AUTO_COMPLETE |
a868e443 PH |
240 | #define CONFIG_CMDLINE_EDITING |
241 | #define CONFIG_SYS_LONGHELP | |
a868e443 | 242 | #define CONFIG_MX_CYCLIC |
a868e443 PH |
243 | |
244 | /* | |
245 | * Linux Information | |
246 | */ | |
247 | #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) | |
248 | #define CONFIG_CMDLINE_TAG | |
249 | #define CONFIG_REVISION_TAG | |
250 | #define CONFIG_SETUP_MEMORY_TAGS | |
f96ab6a4 | 251 | #define CONFIG_BOOTCOMMAND \ |
1120dda8 | 252 | "run envboot; " \ |
4c8865a2 | 253 | "run mmcboot; " |
6e806961 SN |
254 | |
255 | #define DEFAULT_LINUX_BOOT_ENV \ | |
256 | "loadaddr=0xc0700000\0" \ | |
5ca28f67 | 257 | "fdtaddr=0xc0600000\0" \ |
6e806961 SN |
258 | "scriptaddr=0xc0600000\0" |
259 | ||
1120dda8 SN |
260 | #include <environment/ti/mmc.h> |
261 | ||
6e806961 SN |
262 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
263 | DEFAULT_LINUX_BOOT_ENV \ | |
1120dda8 SN |
264 | DEFAULT_MMC_TI_ARGS \ |
265 | "bootpart=0:2\0" \ | |
266 | "bootdir=/boot\0" \ | |
267 | "bootfile=zImage\0" \ | |
5ca28f67 | 268 | "fdtfile=da850-lcdk.dtb\0" \ |
1120dda8 SN |
269 | "boot_fdt=yes\0" \ |
270 | "boot_fit=0\0" \ | |
271 | "console=ttyS2,115200n8\0" | |
a868e443 | 272 | |
a868e443 PH |
273 | #ifdef CONFIG_CMD_BDI |
274 | #define CONFIG_CLOCKS | |
275 | #endif | |
276 | ||
277 | #ifndef CONFIG_DRIVER_TI_EMAC | |
a868e443 PH |
278 | #endif |
279 | ||
280 | #ifdef CONFIG_USE_NAND | |
a868e443 PH |
281 | #define CONFIG_MTD_DEVICE |
282 | #define CONFIG_MTD_PARTITIONS | |
a868e443 PH |
283 | #endif |
284 | ||
a868e443 PH |
285 | #if !defined(CONFIG_USE_NAND) && \ |
286 | !defined(CONFIG_SYS_USE_NOR) && \ | |
287 | !defined(CONFIG_USE_SPIFLASH) | |
a868e443 | 288 | #define CONFIG_ENV_SIZE (16 << 10) |
a868e443 PH |
289 | #endif |
290 | ||
291 | /* SD/MMC */ | |
a868e443 PH |
292 | |
293 | #ifdef CONFIG_ENV_IS_IN_MMC | |
294 | #undef CONFIG_ENV_SIZE | |
295 | #undef CONFIG_ENV_OFFSET | |
296 | #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ | |
297 | #define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */ | |
a868e443 PH |
298 | #endif |
299 | ||
300 | #ifndef CONFIG_DIRECT_NOR_BOOT | |
301 | /* defines for SPL */ | |
302 | #define CONFIG_SPL_FRAMEWORK | |
a868e443 PH |
303 | #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ |
304 | CONFIG_SYS_MALLOC_LEN) | |
305 | #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN | |
a868e443 PH |
306 | #define CONFIG_SPL_STACK 0x8001ff00 |
307 | #define CONFIG_SPL_TEXT_BASE 0x80000000 | |
308 | #define CONFIG_SPL_MAX_FOOTPRINT 32768 | |
309 | #define CONFIG_SPL_PAD_TO 32768 | |
310 | #endif | |
311 | ||
312 | /* additions for new relocation code, must added to all boards */ | |
313 | #define CONFIG_SYS_SDRAM_BASE 0xc0000000 | |
314 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ | |
315 | GENERATED_GBL_DATA_SIZE) | |
89f5eaa1 SG |
316 | |
317 | #include <asm/arch/hardware.h> | |
318 | ||
a868e443 | 319 | #endif /* __CONFIG_H */ |