]>
Commit | Line | Data |
---|---|---|
a868e443 PH |
1 | /* |
2 | * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ | |
3 | * | |
4 | * Based on davinci_dvevm.h. Original Copyrights follow: | |
5 | * | |
6 | * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> | |
7 | * | |
5b8031cc | 8 | * SPDX-License-Identifier: GPL-2.0 |
a868e443 PH |
9 | */ |
10 | ||
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
14 | /* | |
15 | * Board | |
16 | */ | |
17 | #define CONFIG_DRIVER_TI_EMAC | |
18 | #undef CONFIG_USE_SPIFLASH | |
19 | #undef CONFIG_SYS_USE_NOR | |
20 | #define CONFIG_USE_NAND | |
21 | ||
22 | /* | |
23 | * SoC Configuration | |
24 | */ | |
25 | #define CONFIG_MACH_OMAPL138_LCDK | |
26 | #define CONFIG_ARM926EJS /* arm926ejs CPU core */ | |
27 | #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ | |
28 | #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) | |
29 | #define CONFIG_SYS_OSCIN_FREQ 24000000 | |
30 | #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE | |
31 | #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) | |
32 | #define CONFIG_SYS_HZ 1000 | |
33 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
34 | #define CONFIG_SYS_TEXT_BASE 0xc1080000 | |
35 | ||
36 | /* | |
37 | * Memory Info | |
38 | */ | |
39 | #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ | |
40 | #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ | |
41 | #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ | |
42 | #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ | |
43 | ||
44 | /* memtest start addr */ | |
45 | #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) | |
46 | ||
47 | /* memtest will be run on 16MB */ | |
48 | #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024) | |
49 | ||
50 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ | |
51 | #define CONFIG_STACKSIZE (256*1024) /* regular stack */ | |
52 | ||
53 | #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ | |
54 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ | |
55 | DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ | |
56 | DAVINCI_SYSCFG_SUSPSRC_UART2 | \ | |
57 | DAVINCI_SYSCFG_SUSPSRC_EMAC | \ | |
58 | DAVINCI_SYSCFG_SUSPSRC_I2C) | |
59 | ||
60 | /* | |
61 | * PLL configuration | |
62 | */ | |
63 | #define CONFIG_SYS_DV_CLKMODE 0 | |
64 | #define CONFIG_SYS_DA850_PLL0_POSTDIV 1 | |
65 | #define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000 | |
66 | #define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001 | |
67 | #define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 | |
68 | #define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003 | |
69 | #define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002 | |
70 | #define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1 | |
71 | #define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005 | |
72 | ||
73 | #define CONFIG_SYS_DA850_PLL1_POSTDIV 1 | |
74 | #define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000 | |
75 | #define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001 | |
76 | #define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8003 | |
77 | ||
78 | #define CONFIG_SYS_DA850_PLL0_PLLM 24 | |
79 | #define CONFIG_SYS_DA850_PLL1_PLLM 21 | |
80 | ||
81 | /* | |
82 | * Serial Driver info | |
83 | */ | |
a868e443 PH |
84 | #define CONFIG_SYS_NS16550_SERIAL |
85 | #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ | |
86 | #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ | |
87 | #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) | |
88 | #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ | |
89 | #define CONFIG_BAUDRATE 115200 /* Default baud rate */ | |
90 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
91 | ||
92 | #define CONFIG_SPI | |
a868e443 PH |
93 | #define CONFIG_DAVINCI_SPI |
94 | #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE | |
95 | #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) | |
96 | #define CONFIG_SF_DEFAULT_SPEED 30000000 | |
97 | #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED | |
98 | ||
99 | #ifdef CONFIG_USE_SPIFLASH | |
a868e443 PH |
100 | #define CONFIG_SPL_SPI_LOAD |
101 | #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 | |
102 | #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x30000 | |
103 | #endif | |
104 | ||
105 | /* | |
106 | * I2C Configuration | |
107 | */ | |
108 | #define CONFIG_SYS_I2C | |
109 | #define CONFIG_SYS_I2C_DAVINCI | |
110 | #define CONFIG_SYS_DAVINCI_I2C_SPEED 25000 | |
111 | #define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ | |
112 | #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 | |
113 | ||
114 | /* | |
115 | * Flash & Environment | |
116 | */ | |
117 | #ifdef CONFIG_USE_NAND | |
118 | #undef CONFIG_ENV_IS_IN_FLASH | |
119 | #define CONFIG_NAND_DAVINCI | |
120 | #define CONFIG_SYS_NO_FLASH | |
121 | #define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ | |
122 | #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ | |
123 | #define CONFIG_ENV_SIZE (128 << 9) | |
124 | #define CONFIG_SYS_NAND_USE_FLASH_BBT | |
125 | #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST | |
126 | #define CONFIG_SYS_NAND_PAGE_2K | |
127 | #define CONFIG_SYS_NAND_BUSWIDTH_16_BIT | |
128 | #define CONFIG_SYS_NAND_CS 3 | |
129 | #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE | |
130 | #define CONFIG_SYS_CLE_MASK 0x10 | |
131 | #define CONFIG_SYS_ALE_MASK 0x8 | |
132 | #undef CONFIG_SYS_NAND_HW_ECC | |
133 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ | |
134 | #define NAND_MAX_CHIPS 1 | |
135 | #endif | |
136 | ||
137 | #ifdef CONFIG_SYS_USE_NOR | |
138 | #define CONFIG_ENV_IS_IN_FLASH | |
139 | #undef CONFIG_SYS_NO_FLASH | |
140 | #define CONFIG_FLASH_CFI_DRIVER | |
141 | #define CONFIG_SYS_FLASH_CFI | |
142 | #define CONFIG_SYS_FLASH_PROTECTION | |
143 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ | |
144 | #define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */ | |
145 | #define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3) | |
146 | #define CONFIG_ENV_SIZE (128 << 10) | |
147 | #define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE | |
148 | #define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */ | |
149 | #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\ | |
150 | + 3) | |
151 | #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ | |
152 | #endif | |
153 | ||
154 | #ifdef CONFIG_USE_SPIFLASH | |
155 | #undef CONFIG_ENV_IS_IN_FLASH | |
156 | #undef CONFIG_ENV_IS_IN_NAND | |
157 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
158 | #define CONFIG_ENV_SIZE (64 << 10) | |
159 | #define CONFIG_ENV_OFFSET (256 << 10) | |
160 | #define CONFIG_ENV_SECT_SIZE (64 << 10) | |
161 | #define CONFIG_SYS_NO_FLASH | |
162 | #endif | |
163 | ||
164 | /* | |
165 | * Network & Ethernet Configuration | |
166 | */ | |
167 | #ifdef CONFIG_DRIVER_TI_EMAC | |
168 | #define CONFIG_EMAC_MDIO_PHY_NUM 7 | |
169 | #define CONFIG_MII | |
170 | #undef CONFIG_DRIVER_TI_EMAC_USE_RMII | |
171 | #define CONFIG_BOOTP_DEFAULT | |
172 | #define CONFIG_BOOTP_DNS | |
173 | #define CONFIG_BOOTP_DNS2 | |
174 | #define CONFIG_BOOTP_SEND_HOSTNAME | |
175 | #define CONFIG_NET_RETRY_COUNT 10 | |
a868e443 PH |
176 | #endif |
177 | ||
178 | /* | |
179 | * U-Boot general configuration | |
180 | */ | |
a868e443 PH |
181 | #define CONFIG_MISC_INIT_R |
182 | #define CONFIG_BOARD_EARLY_INIT_F | |
183 | #define CONFIG_BOOTFILE "uImage" /* Boot file name */ | |
a868e443 PH |
184 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
185 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
186 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
187 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ | |
188 | #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) | |
a868e443 | 189 | #define CONFIG_AUTO_COMPLETE |
a868e443 PH |
190 | #define CONFIG_CMDLINE_EDITING |
191 | #define CONFIG_SYS_LONGHELP | |
192 | #define CONFIG_CRC32_VERIFY | |
193 | #define CONFIG_MX_CYCLIC | |
a868e443 PH |
194 | |
195 | /* | |
196 | * Linux Information | |
197 | */ | |
198 | #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) | |
199 | #define CONFIG_CMDLINE_TAG | |
200 | #define CONFIG_REVISION_TAG | |
201 | #define CONFIG_SETUP_MEMORY_TAGS | |
202 | #define CONFIG_BOOTARGS "console=ttyS2,115200n8 root=/dev/mmcblk0p2 rw rootwait ip=off" | |
d03a0308 | 203 | #define CONFIG_BOOTCOMMAND "if mmc rescan; then if fatload mmc 0 0xc0600000 boot.scr; then source 0xc0600000; else fatload mmc 0 0xc0700000 uImage; bootm c0700000; fi; else sf probe 0; sf read 0xc0700000 0x80000 0x220000; bootm 0xc0700000; fi" |
a868e443 PH |
204 | |
205 | /* | |
206 | * U-Boot commands | |
207 | */ | |
a868e443 | 208 | #define CONFIG_CMD_ENV |
a868e443 | 209 | #define CONFIG_CMD_DIAG |
a868e443 | 210 | #define CONFIG_CMD_SAVES |
a868e443 PH |
211 | #ifdef CONFIG_CMD_BDI |
212 | #define CONFIG_CLOCKS | |
213 | #endif | |
214 | ||
215 | #ifndef CONFIG_DRIVER_TI_EMAC | |
a868e443 PH |
216 | #endif |
217 | ||
218 | #ifdef CONFIG_USE_NAND | |
a868e443 PH |
219 | #define CONFIG_CMD_NAND |
220 | ||
221 | #define CONFIG_CMD_MTDPARTS | |
222 | #define CONFIG_MTD_DEVICE | |
223 | #define CONFIG_MTD_PARTITIONS | |
224 | #define CONFIG_LZO | |
225 | #define CONFIG_RBTREE | |
226 | #define CONFIG_CMD_UBI | |
227 | #define CONFIG_CMD_UBIFS | |
228 | #endif | |
229 | ||
230 | #ifdef CONFIG_USE_SPIFLASH | |
a868e443 PH |
231 | #endif |
232 | ||
233 | #if !defined(CONFIG_USE_NAND) && \ | |
234 | !defined(CONFIG_SYS_USE_NOR) && \ | |
235 | !defined(CONFIG_USE_SPIFLASH) | |
236 | #define CONFIG_ENV_IS_NOWHERE | |
237 | #define CONFIG_SYS_NO_FLASH | |
238 | #define CONFIG_ENV_SIZE (16 << 10) | |
a868e443 PH |
239 | #undef CONFIG_CMD_ENV |
240 | #endif | |
241 | ||
242 | /* SD/MMC */ | |
243 | #define CONFIG_MMC | |
244 | #define CONFIG_GENERIC_MMC | |
245 | #define CONFIG_DAVINCI_MMC | |
246 | ||
247 | #ifdef CONFIG_MMC | |
248 | #define CONFIG_DOS_PARTITION | |
a868e443 PH |
249 | #undef CONFIG_ENV_IS_IN_MMC |
250 | #endif | |
251 | ||
252 | #ifdef CONFIG_ENV_IS_IN_MMC | |
253 | #undef CONFIG_ENV_SIZE | |
254 | #undef CONFIG_ENV_OFFSET | |
255 | #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ | |
256 | #define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */ | |
257 | #undef CONFIG_ENV_IS_IN_FLASH | |
258 | #undef CONFIG_ENV_IS_IN_NAND | |
259 | #undef CONFIG_ENV_IS_IN_SPI_FLASH | |
260 | #endif | |
261 | ||
262 | #ifndef CONFIG_DIRECT_NOR_BOOT | |
263 | /* defines for SPL */ | |
264 | #define CONFIG_SPL_FRAMEWORK | |
265 | #define CONFIG_SPL_BOARD_INIT | |
266 | #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ | |
267 | CONFIG_SYS_MALLOC_LEN) | |
268 | #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN | |
a868e443 PH |
269 | #define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-da850evm.lds" |
270 | #define CONFIG_SPL_STACK 0x8001ff00 | |
271 | #define CONFIG_SPL_TEXT_BASE 0x80000000 | |
272 | #define CONFIG_SPL_MAX_FOOTPRINT 32768 | |
273 | #define CONFIG_SPL_PAD_TO 32768 | |
274 | #endif | |
275 | ||
276 | /* additions for new relocation code, must added to all boards */ | |
277 | #define CONFIG_SYS_SDRAM_BASE 0xc0000000 | |
278 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ | |
279 | GENERATED_GBL_DATA_SIZE) | |
280 | #endif /* __CONFIG_H */ |