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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
a868e443 PH |
2 | /* |
3 | * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ | |
4 | * | |
5 | * Based on davinci_dvevm.h. Original Copyrights follow: | |
6 | * | |
7 | * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> | |
a868e443 PH |
8 | */ |
9 | ||
10 | #ifndef __CONFIG_H | |
11 | #define __CONFIG_H | |
12 | ||
13 | /* | |
14 | * Board | |
15 | */ | |
a868e443 PH |
16 | |
17 | /* | |
18 | * SoC Configuration | |
19 | */ | |
a868e443 PH |
20 | #define CONFIG_SYS_OSCIN_FREQ 24000000 |
21 | #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE | |
22 | #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) | |
a868e443 PH |
23 | |
24 | /* | |
25 | * Memory Info | |
26 | */ | |
a868e443 PH |
27 | #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ |
28 | #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ | |
29 | #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ | |
30 | ||
15b8c750 AF |
31 | #define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE |
32 | #define CONFIG_SPL_BSS_MAX_SIZE 0x1080000 | |
33 | ||
a868e443 | 34 | /* memtest start addr */ |
a868e443 PH |
35 | |
36 | /* memtest will be run on 16MB */ | |
a868e443 | 37 | |
a868e443 PH |
38 | #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ |
39 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ | |
40 | DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ | |
41 | DAVINCI_SYSCFG_SUSPSRC_UART2 | \ | |
42 | DAVINCI_SYSCFG_SUSPSRC_EMAC | \ | |
43 | DAVINCI_SYSCFG_SUSPSRC_I2C) | |
44 | ||
45 | /* | |
46 | * PLL configuration | |
47 | */ | |
a868e443 | 48 | |
dc73483a DL |
49 | /* Requires CONFIG_SYS_DA850_PLL0_POSTDIV=0, set in Kconfig */ |
50 | #define CONFIG_SYS_DA850_PLL0_PLLM 18 | |
a868e443 PH |
51 | #define CONFIG_SYS_DA850_PLL1_PLLM 21 |
52 | ||
a5ab44f6 FP |
53 | /* |
54 | * DDR2 memory configuration | |
55 | */ | |
56 | #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ | |
57 | DV_DDR_PHY_EXT_STRBEN | \ | |
58 | (0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT)) | |
59 | ||
60 | #define CONFIG_SYS_DA850_DDR2_SDBCR ( \ | |
61 | (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \ | |
62 | (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ | |
63 | (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ | |
64 | (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ | |
65 | (4 << DV_DDR_SDCR_CL_SHIFT) | \ | |
66 | (3 << DV_DDR_SDCR_IBANK_SHIFT) | \ | |
67 | (2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) | |
68 | ||
69 | /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ | |
70 | #define CONFIG_SYS_DA850_DDR2_SDBCR2 0 | |
71 | ||
72 | #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ | |
73 | (19 << DV_DDR_SDTMR1_RFC_SHIFT) | \ | |
74 | (1 << DV_DDR_SDTMR1_RP_SHIFT) | \ | |
75 | (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \ | |
76 | (2 << DV_DDR_SDTMR1_WR_SHIFT) | \ | |
77 | (6 << DV_DDR_SDTMR1_RAS_SHIFT) | \ | |
78 | (8 << DV_DDR_SDTMR1_RC_SHIFT) | \ | |
79 | (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ | |
80 | (1 << DV_DDR_SDTMR1_WTR_SHIFT)) | |
81 | ||
82 | #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ | |
83 | (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ | |
84 | (2 << DV_DDR_SDTMR2_XP_SHIFT) | \ | |
85 | (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ | |
264e420f | 86 | (20 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ |
a5ab44f6 FP |
87 | (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ |
88 | (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \ | |
89 | (2 << DV_DDR_SDTMR2_CKE_SHIFT)) | |
90 | ||
91 | #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000492 | |
92 | #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 | |
93 | ||
a868e443 PH |
94 | /* |
95 | * Serial Driver info | |
96 | */ | |
d6d8c4d4 | 97 | #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) |
a868e443 | 98 | |
a868e443 PH |
99 | #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE |
100 | #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) | |
a868e443 | 101 | |
a868e443 PH |
102 | /* |
103 | * I2C Configuration | |
104 | */ | |
a868e443 PH |
105 | #define CONFIG_SYS_DAVINCI_I2C_SPEED 25000 |
106 | #define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ | |
107 | #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 | |
108 | ||
109 | /* | |
110 | * Flash & Environment | |
111 | */ | |
88718be3 | 112 | #ifdef CONFIG_MTD_RAW_NAND |
a868e443 PH |
113 | #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST |
114 | #define CONFIG_SYS_NAND_PAGE_2K | |
a868e443 PH |
115 | #define CONFIG_SYS_NAND_CS 3 |
116 | #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE | |
1dbab274 | 117 | #define CONFIG_SYS_NAND_MASK_CLE 0x10 |
ef044796 | 118 | #define CONFIG_SYS_NAND_MASK_ALE 0x8 |
a868e443 PH |
119 | #undef CONFIG_SYS_NAND_HW_ECC |
120 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ | |
c69a05d0 | 121 | #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST |
2b2cab24 | 122 | #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC |
c0c10449 | 123 | #define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K |
c69a05d0 FP |
124 | #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 |
125 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST | |
126 | #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \ | |
127 | CONFIG_SYS_NAND_U_BOOT_SIZE - \ | |
128 | CONFIG_SYS_MALLOC_LEN - \ | |
129 | GENERATED_GBL_DATA_SIZE) | |
130 | #define CONFIG_SYS_NAND_ECCPOS { \ | |
2b2cab24 FP |
131 | 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ |
132 | 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \ | |
133 | 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ | |
134 | 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 } | |
c69a05d0 FP |
135 | #define CONFIG_SYS_NAND_ECCSIZE 512 |
136 | #define CONFIG_SYS_NAND_ECCBYTES 10 | |
a868e443 PH |
137 | #endif |
138 | ||
a868e443 PH |
139 | /* |
140 | * U-Boot general configuration | |
141 | */ | |
a868e443 | 142 | |
8f6babf8 AF |
143 | /* |
144 | * USB Configs | |
145 | */ | |
146 | #define CONFIG_USB_OHCI_NEW | |
147 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 | |
148 | ||
a868e443 PH |
149 | /* |
150 | * Linux Information | |
151 | */ | |
152 | #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) | |
6e806961 SN |
153 | |
154 | #define DEFAULT_LINUX_BOOT_ENV \ | |
155 | "loadaddr=0xc0700000\0" \ | |
5ca28f67 | 156 | "fdtaddr=0xc0600000\0" \ |
6e806961 SN |
157 | "scriptaddr=0xc0600000\0" |
158 | ||
1120dda8 SN |
159 | #include <environment/ti/mmc.h> |
160 | ||
6e806961 SN |
161 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
162 | DEFAULT_LINUX_BOOT_ENV \ | |
1120dda8 SN |
163 | DEFAULT_MMC_TI_ARGS \ |
164 | "bootpart=0:2\0" \ | |
165 | "bootdir=/boot\0" \ | |
166 | "bootfile=zImage\0" \ | |
5ca28f67 | 167 | "fdtfile=da850-lcdk.dtb\0" \ |
1120dda8 SN |
168 | "boot_fdt=yes\0" \ |
169 | "boot_fit=0\0" \ | |
170 | "console=ttyS2,115200n8\0" | |
a868e443 | 171 | |
a868e443 | 172 | /* SD/MMC */ |
a868e443 | 173 | |
a868e443 | 174 | /* defines for SPL */ |
a868e443 PH |
175 | #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ |
176 | CONFIG_SYS_MALLOC_LEN) | |
177 | #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN | |
a868e443 | 178 | #define CONFIG_SPL_STACK 0x8001ff00 |
a868e443 | 179 | #define CONFIG_SPL_MAX_FOOTPRINT 32768 |
a868e443 PH |
180 | |
181 | /* additions for new relocation code, must added to all boards */ | |
182 | #define CONFIG_SYS_SDRAM_BASE 0xc0000000 | |
183 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ | |
184 | GENERATED_GBL_DATA_SIZE) | |
89f5eaa1 SG |
185 | |
186 | #include <asm/arch/hardware.h> | |
187 | ||
a868e443 | 188 | #endif /* __CONFIG_H */ |