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b9a1ef21 CK |
1 | /* |
2 | * Copyright (C) 2011 Samsung Electronics | |
3 | * | |
393cb361 | 4 | * Configuration settings for the SAMSUNG ORIGEN (EXYNOS4210) board. |
b9a1ef21 | 5 | * |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
b9a1ef21 CK |
7 | */ |
8 | ||
bf7716d6 PW |
9 | #ifndef __CONFIG_ORIGEN_H |
10 | #define __CONFIG_ORIGEN_H | |
11 | ||
4c7bb1d2 | 12 | #include <configs/exynos4-common.h> |
bf7716d6 | 13 | |
b9a1ef21 | 14 | /* High Level Configuration Options */ |
393cb361 | 15 | #define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */ |
b9a1ef21 CK |
16 | #define CONFIG_ORIGEN 1 /* working with ORIGEN*/ |
17 | ||
b9a1ef21 CK |
18 | #define CONFIG_SYS_DCACHE_OFF 1 |
19 | ||
bf7716d6 PW |
20 | /* ORIGEN has 4 bank of DRAM */ |
21 | #define CONFIG_NR_DRAM_BANKS 4 | |
b9a1ef21 | 22 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 |
bf7716d6 PW |
23 | #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE |
24 | #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ | |
b9a1ef21 | 25 | |
bf7716d6 PW |
26 | /* memtest works on */ |
27 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE | |
28 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000) | |
29 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) | |
b9a1ef21 | 30 | |
bf7716d6 | 31 | #define CONFIG_SYS_TEXT_BASE 0x43E00000 |
b9a1ef21 | 32 | |
b9a1ef21 CK |
33 | #define CONFIG_MACH_TYPE MACH_TYPE_ORIGEN |
34 | ||
b9a1ef21 | 35 | /* select serial console configuration */ |
bf7716d6 | 36 | #define CONFIG_SERIAL2 |
b9a1ef21 | 37 | |
bf7716d6 | 38 | /* Console configuration */ |
bf7716d6 | 39 | #define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" |
643be9c0 | 40 | |
bf7716d6 | 41 | #define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ |
b9a1ef21 | 42 | |
bf7716d6 | 43 | #define CONFIG_SYS_MONITOR_BASE 0x00000000 |
b9a1ef21 | 44 | |
bf7716d6 PW |
45 | /* Power Down Modes */ |
46 | #define S5P_CHECK_SLEEP 0x00000BAD | |
47 | #define S5P_CHECK_DIDLE 0xBAD00000 | |
48 | #define S5P_CHECK_LPA 0xABAD0000 | |
b9a1ef21 | 49 | |
7741c8b8 | 50 | #define CONFIG_SUPPORT_RAW_INITRD |
b9a1ef21 | 51 | |
98a48c5d | 52 | /* MMC SPL */ |
98a48c5d | 53 | #define COPY_BL2_FNPTR_ADDR 0x02020030 |
8a00061e IS |
54 | #define CONFIG_SPL_TEXT_BASE 0x02021410 |
55 | ||
7741c8b8 GG |
56 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
57 | "loadaddr=0x40007000\0" \ | |
58 | "rdaddr=0x48000000\0" \ | |
59 | "kerneladdr=0x40007000\0" \ | |
60 | "ramdiskaddr=0x48000000\0" \ | |
61 | "console=ttySAC2,115200n8\0" \ | |
62 | "mmcdev=0\0" \ | |
63 | "bootenv=uEnv.txt\0" \ | |
64 | "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ | |
65 | "importbootenv=echo Importing environment from mmc ...; " \ | |
66 | "env import -t $loadaddr $filesize\0" \ | |
67 | "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \ | |
68 | "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ | |
69 | "source ${loadaddr}\0" | |
70 | #define CONFIG_BOOTCOMMAND \ | |
71 | "if mmc rescan; then " \ | |
72 | "echo SD/MMC found on device ${mmcdev};" \ | |
73 | "if run loadbootenv; then " \ | |
74 | "echo Loaded environment from ${bootenv};" \ | |
75 | "run importbootenv;" \ | |
76 | "fi;" \ | |
77 | "if test -n $uenvcmd; then " \ | |
78 | "echo Running uenvcmd ...;" \ | |
79 | "run uenvcmd;" \ | |
80 | "fi;" \ | |
81 | "if run loadbootscript; then " \ | |
82 | "run bootscript; " \ | |
83 | "fi; " \ | |
84 | "fi;" \ | |
85 | "load mmc ${mmcdev} ${loadaddr} uImage; bootm ${loadaddr} " | |
b9a1ef21 | 86 | |
b9a1ef21 CK |
87 | #define CONFIG_CLK_1000_400_200 |
88 | ||
89 | /* MIU (Memory Interleaving Unit) */ | |
90 | #define CONFIG_MIU_2BIT_21_7_INTERLEAVED | |
91 | ||
b9a1ef21 CK |
92 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
93 | #define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ | |
94 | #define RESERVE_BLOCK_SIZE (512) | |
95 | #define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ | |
96 | #define CONFIG_ENV_OFFSET (RESERVE_BLOCK_SIZE + BL1_SIZE) | |
b9a1ef21 | 97 | |
643be9c0 RS |
98 | #define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) |
99 | ||
100 | #define CONFIG_SYS_INIT_SP_ADDR 0x02040000 | |
98a48c5d | 101 | |
a187559e | 102 | /* U-Boot copy size from boot Media to DRAM.*/ |
98a48c5d CK |
103 | #define COPY_BL2_SIZE 0x80000 |
104 | #define BL2_START_OFFSET ((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512) | |
105 | #define BL2_SIZE_BLOC_COUNT (COPY_BL2_SIZE/512) | |
099e884a | 106 | |
b9a1ef21 | 107 | #endif /* __CONFIG_H */ |