[people/ms/u-boot.git] / include / configs / ot1200.h

/*
 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
 * Copyright (C) 2014 Bachmann electronic GmbH
 *
 * SPDX-License-Identifier:     GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include "mx6_common.h"

/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)

#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_MISC_INIT_R

/* UART Configs */
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE           UART1_BASE

/* SF Configs */
#define CONFIG_CMD_SF
#define CONFIG_SPI
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SPI_FLASH_MACRONIX
#define CONFIG_SPI_FLASH_SST
#define CONFIG_MXC_SPI
#define CONFIG_SF_DEFAULT_BUS  2
#define CONFIG_SF_DEFAULT_CS   0
#define CONFIG_SF_DEFAULT_SPEED 25000000
#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)

/* IO expander */
#define CONFIG_PCA953X
#define CONFIG_SYS_I2C_PCA953X_ADDR	0x20
#define CONFIG_SYS_I2C_PCA953X_WIDTH	{ {0x20, 16} }
#define CONFIG_CMD_PCA953X
#define CONFIG_CMD_PCA953X_INFO

/* I2C Configs */
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
#define CONFIG_SYS_I2C_SPEED            100000

/* OCOTP Configs */
#define CONFIG_CMD_IMXOTP
#define CONFIG_IMX_OTP
#define IMX_OTP_BASE                    OCOTP_BASE_ADDR
#define IMX_OTP_ADDR_MAX                0x7F
#define IMX_OTP_DATA_ERROR_VAL          0xBADABADA
#define IMX_OTPWRITE_ENABLED

/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR      0
#define CONFIG_SYS_FSL_USDHC_NUM       2

/* USB Configs */
#define CONFIG_CMD_USB
#define CONFIG_USB_STORAGE
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_MX6
#define CONFIG_MXC_USB_PORTSC   (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2

#ifdef CONFIG_MX6Q
#define CONFIG_CMD_SATA
#endif

/*
 * SATA Configs
 */
#ifdef CONFIG_CMD_SATA
#define CONFIG_DWC_AHSATA
#define CONFIG_SYS_SATA_MAX_DEVICE	1
#define CONFIG_DWC_AHSATA_PORT_ID	0
#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
#define CONFIG_LBA48
#define CONFIG_LIBATA
#endif


/* SPL */
#ifdef CONFIG_SPL
#include "imx6_spl.h"
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SYS_SPI_U_BOOT_OFFS     (64 * 1024)
#define CONFIG_SPL_SPI_LOAD
#endif

#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
#define CONFIG_FEC_MXC
#define CONFIG_MII
#define IMX_FEC_BASE                    ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE             MII100
#define CONFIG_ETHPRIME                 "FEC"
#define CONFIG_FEC_MXC_PHYADDR          0x5
#define CONFIG_PHYLIB
#define CONFIG_PHY_SMSC

#ifndef CONFIG_SPL
#define CONFIG_CMD_EEPROM
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_BUS             1
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN        1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS     3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
#define CONFIG_SYS_I2C_MULTI_EEPROMS
#endif

/* Miscellaneous commands */
#define CONFIG_CMD_BMODE

#define CONFIG_PREBOOT                 ""

/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)

/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS           1
#define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR

#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE

#define CONFIG_SYS_INIT_SP_OFFSET \
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

/* Environment organization */
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE                 (64 * 1024)	/* 64 kb */
#define CONFIG_ENV_OFFSET               (1024 * 1024)
/* M25P16 has an erase size of 64 KiB */
#define CONFIG_ENV_SECT_SIZE            (64 * 1024)
#define CONFIG_ENV_SPI_BUS              CONFIG_SF_DEFAULT_BUS
#define CONFIG_ENV_SPI_CS               CONFIG_SF_DEFAULT_CS
#define CONFIG_ENV_SPI_MODE             CONFIG_SF_DEFAULT_MODE
#define CONFIG_ENV_SPI_MAX_HZ           CONFIG_SF_DEFAULT_SPEED

#define CONFIG_BOOTP_SERVERIP
#define CONFIG_BOOTP_BOOTFILE

#endif         /* __CONFIG_H */
Commit	Line	Data
39d09733 CG	1	/*
	2	* Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
	3	* Copyright (C) 2014 Bachmann electronic GmbH
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#ifndef __CONFIG_H
	9	#define __CONFIG_H
	10
	11	#include "mx6_common.h"
39d09733	12
39d09733 CG	13	/* Size of malloc() pool */
	14	#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
	15
	16	#define CONFIG_BOARD_EARLY_INIT_F
	17	#define CONFIG_MISC_INIT_R
39d09733	18
39d09733 CG	19	/* UART Configs */
	20	#define CONFIG_MXC_UART
	21	#define CONFIG_MXC_UART_BASE UART1_BASE
	22
	23	/* SF Configs */
	24	#define CONFIG_CMD_SF
	25	#define CONFIG_SPI
39d09733 CG	26	#define CONFIG_SPI_FLASH_STMICRO
	27	#define CONFIG_SPI_FLASH_WINBOND
	28	#define CONFIG_SPI_FLASH_MACRONIX
	29	#define CONFIG_SPI_FLASH_SST
	30	#define CONFIG_MXC_SPI
	31	#define CONFIG_SF_DEFAULT_BUS 2
2e3a1f4d	32	#define CONFIG_SF_DEFAULT_CS 0
39d09733 CG	33	#define CONFIG_SF_DEFAULT_SPEED 25000000
	34	#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
	35
	36	/* IO expander */
	37	#define CONFIG_PCA953X
	38	#define CONFIG_SYS_I2C_PCA953X_ADDR 0x20
	39	#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} }
	40	#define CONFIG_CMD_PCA953X
	41	#define CONFIG_CMD_PCA953X_INFO
	42
	43	/* I2C Configs */
	44	#define CONFIG_CMD_I2C
	45	#define CONFIG_SYS_I2C
	46	#define CONFIG_SYS_I2C_MXC
f8cb101e	47	#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
39d09733 CG	48	#define CONFIG_SYS_I2C_SPEED 100000
	49
	50	/* OCOTP Configs */
	51	#define CONFIG_CMD_IMXOTP
	52	#define CONFIG_IMX_OTP
	53	#define IMX_OTP_BASE OCOTP_BASE_ADDR
	54	#define IMX_OTP_ADDR_MAX 0x7F
	55	#define IMX_OTP_DATA_ERROR_VAL 0xBADABADA
	56	#define IMX_OTPWRITE_ENABLED
	57
	58	/* MMC Configs */
39d09733 CG	59	#define CONFIG_SYS_FSL_ESDHC_ADDR 0
	60	#define CONFIG_SYS_FSL_USDHC_NUM 2
	61
39c7d5a2 CG	62	/* USB Configs */
39c7d5a2 CG	63	#define CONFIG_CMD_USB
7f22307c	64	#define CONFIG_USB_STORAGE
39c7d5a2 CG	65	#define CONFIG_USB_EHCI
	66	#define CONFIG_USB_EHCI_MX6
	67	#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI \| PORT_PTS_PTW)
	68	#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
	69
39d09733 CG	70	#ifdef CONFIG_MX6Q
	71	#define CONFIG_CMD_SATA
	72	#endif
	73
	74	/*
	75	* SATA Configs
	76	*/
	77	#ifdef CONFIG_CMD_SATA
	78	#define CONFIG_DWC_AHSATA
	79	#define CONFIG_SYS_SATA_MAX_DEVICE 1
	80	#define CONFIG_DWC_AHSATA_PORT_ID 0
	81	#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
	82	#define CONFIG_LBA48
	83	#define CONFIG_LIBATA
	84	#endif
	85
	86
68a3664a CG	87	/* SPL */
	88	#ifdef CONFIG_SPL
	89	#include "imx6_spl.h"
	90	#define CONFIG_SPL_SPI_SUPPORT
	91	#define CONFIG_SPL_LIBCOMMON_SUPPORT
	92	#define CONFIG_SPL_SPI_FLASH_SUPPORT
	93	#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
	94	#define CONFIG_SPL_SPI_LOAD
	95	#endif
	96
39d09733 CG	97	#define CONFIG_CMD_PING
	98	#define CONFIG_CMD_DHCP
	99	#define CONFIG_CMD_MII
39d09733 CG	100	#define CONFIG_FEC_MXC
	101	#define CONFIG_MII
	102	#define IMX_FEC_BASE ENET_BASE_ADDR
	103	#define CONFIG_FEC_XCV_TYPE MII100
	104	#define CONFIG_ETHPRIME "FEC"
	105	#define CONFIG_FEC_MXC_PHYADDR 0x5
	106	#define CONFIG_PHYLIB
	107	#define CONFIG_PHY_SMSC
	108
fb2589b3 CG	109	#ifndef CONFIG_SPL
	110	#define CONFIG_CMD_EEPROM
	111	#define CONFIG_ENV_EEPROM_IS_ON_I2C
	112	#define CONFIG_SYS_I2C_EEPROM_BUS 1
	113	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	114	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	115	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
	116	#define CONFIG_SYS_I2C_MULTI_EEPROMS
	117	#endif
	118
39d09733 CG	119	/* Miscellaneous commands */
39d09733 CG	120	#define CONFIG_CMD_BMODE
39d09733	121
39d09733 CG	122	#define CONFIG_PREBOOT ""
39d09733 CG	123
39d09733 CG	124	/* Print Buffer Size */
39d09733 CG	125	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
39d09733 CG	126
	127	/* Physical Memory Map */
	128	#define CONFIG_NR_DRAM_BANKS 1
	129	#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
39d09733 CG	130
	131	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
	132	#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
	133	#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
	134
	135	#define CONFIG_SYS_INIT_SP_OFFSET \
	136	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	137	#define CONFIG_SYS_INIT_SP_ADDR \
	138	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
	139
056845c2	140	/* Environment organization */
39d09733 CG	141	#define CONFIG_ENV_IS_IN_SPI_FLASH
	142	#define CONFIG_ENV_SIZE (64 * 1024) /* 64 kb */
	143	#define CONFIG_ENV_OFFSET (1024 * 1024)
	144	/* M25P16 has an erase size of 64 KiB */
	145	#define CONFIG_ENV_SECT_SIZE (64 * 1024)
	146	#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
	147	#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
	148	#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
	149	#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
	150
39d09733 CG	151	#define CONFIG_BOOTP_SERVERIP
	152	#define CONFIG_BOOTP_BOOTFILE
	153
	154	#endif /* __CONFIG_H */