[thirdparty/u-boot.git] / include / configs / p1_twr.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2013 Freescale Semiconductor, Inc.
 */

/*
 * QorIQ P1 Tower boards configuration file
 */
#ifndef __CONFIG_H
#define __CONFIG_H

#include <linux/stringify.h>

#if defined(CONFIG_TWR_P1025)
#define CONFIG_BOARDNAME "TWR-P1025"
#define CONFIG_SYS_LBC_LBCR	0x00080000	/* Conversion of LBC addr */
#define CONFIG_SYS_LBC_LCRR	0x80000002	/* LB clock ratio reg */
#endif

#ifdef CONFIG_SDCARD
#define CONFIG_RAMBOOT_SDCARD
#define CONFIG_SYS_RAMBOOT
#define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
#endif

#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
#endif

#ifndef CONFIG_SYS_MONITOR_BASE
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
#endif

#define CONFIG_PCIE1	/* PCIE controller 1 (slot 1) */
#define CONFIG_PCIE2	/* PCIE controller 2 (slot 2) */
#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
#define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */

#define CONFIG_ENV_OVERWRITE

#define CONFIG_SYS_SATA_MAX_DEVICE	2
#define CONFIG_LBA48

#ifndef __ASSEMBLY__
extern unsigned long get_board_sys_clk(unsigned long dummy);
#endif
#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /*sysclk for TWR-P1025 */

#define CONFIG_DDR_CLK_FREQ	66666666

#define CONFIG_HWCONFIG
/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE
#define CONFIG_BTB

#define CONFIG_SYS_CCSRBAR		0xffe00000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR

/* DDR Setup */

#define CONFIG_SYS_SDRAM_SIZE_LAW	LAW_SIZE_512M
#define CONFIG_CHIP_SELECTS_PER_CTRL	1

#define CONFIG_SYS_SDRAM_SIZE		(1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

#define CONFIG_DIMM_SLOTS_PER_CTLR	1

/* Default settings for DDR3 */
#define CONFIG_SYS_DDR_CS0_BNDS		0x0000001f
#define CONFIG_SYS_DDR_CS0_CONFIG	0x80014202
#define CONFIG_SYS_DDR_CS0_CONFIG_2	0x00000000
#define CONFIG_SYS_DDR_CS1_BNDS		0x00000000
#define CONFIG_SYS_DDR_CS1_CONFIG	0x00000000
#define CONFIG_SYS_DDR_CS1_CONFIG_2	0x00000000

#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
#define CONFIG_SYS_DDR_INIT_ADDR	0x00000000
#define CONFIG_SYS_DDR_INIT_EXT_ADDR	0x00000000
#define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000

#define CONFIG_SYS_DDR_ZQ_CONTROL	0x89080600
#define CONFIG_SYS_DDR_WRLVL_CONTROL	0x8655a608
#define CONFIG_SYS_DDR_SR_CNTR		0x00000000
#define CONFIG_SYS_DDR_RCW_1		0x00000000
#define CONFIG_SYS_DDR_RCW_2		0x00000000
#define CONFIG_SYS_DDR_CONTROL		0xc70c0000	/* Type = DDR3	*/
#define CONFIG_SYS_DDR_CONTROL_2	0x04401050
#define CONFIG_SYS_DDR_TIMING_4		0x00220001
#define CONFIG_SYS_DDR_TIMING_5		0x03402400

#define CONFIG_SYS_DDR_TIMING_3		0x00020000
#define CONFIG_SYS_DDR_TIMING_0		0x00220004
#define CONFIG_SYS_DDR_TIMING_1		0x5c5b6544
#define CONFIG_SYS_DDR_TIMING_2		0x0fa880de
#define CONFIG_SYS_DDR_CLK_CTRL		0x03000000
#define CONFIG_SYS_DDR_MODE_1		0x80461320
#define CONFIG_SYS_DDR_MODE_2		0x00008000
#define CONFIG_SYS_DDR_INTERVAL		0x09480000

/*
 * Memory map
 *
 * 0x0000_0000 0x1fff_ffff	DDR		Up to 512MB cacheable
 * 0x8000_0000 0xdfff_ffff	PCI Express Mem	1.5G non-cacheable(PCIe * 3)
 * 0xffc0_0000 0xffc3_ffff	PCI IO range	256k non-cacheable
 *
 * Localbus
 * 0xe000_0000 0xe002_0000	SSD1289		128K non-cacheable
 * 0xec00_0000 0xefff_ffff	FLASH		Up to 64M non-cacheable
 *
 * 0xff90_0000 0xff97_ffff	L2 SRAM		Up to 512K cacheable
 * 0xffd0_0000 0xffd0_3fff	init ram	16K Cacheable
 * 0xffe0_0000 0xffef_ffff	CCSR		1M non-cacheable
 */

/*
 * Local Bus Definitions
 */
#define CONFIG_SYS_MAX_FLASH_SECT	512	/* 64M */
#define CONFIG_SYS_FLASH_BASE		0xec000000

#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE

#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \
	| BR_PS_16 | BR_V)

#define CONFIG_FLASH_OR_PRELIM	0xfc0000b1

#define CONFIG_SYS_SSD_BASE	0xe0000000
#define CONFIG_SYS_SSD_BASE_PHYS	CONFIG_SYS_SSD_BASE
#define CONFIG_SSD_BR_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_SSD_BASE_PHYS) | \
					BR_PS_16 | BR_V)
#define CONFIG_SSD_OR_PRELIM	(OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
				 OR_GPCM_ACS_DIV2 | OR_GPCM_SCY | \
				 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)

#define CONFIG_SYS_BR2_PRELIM CONFIG_SSD_BR_PRELIM
#define CONFIG_SYS_OR2_PRELIM CONFIG_SSD_OR_PRELIM

#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */

#undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_FLASH_EMPTY_INFO

#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000
/* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS	CONFIG_SYS_INIT_RAM_ADDR
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
/* Size of used area in RAM */
#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
					GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
#define CONFIG_SYS_MALLOC_LEN	(1024 * 1024)/* Reserved for malloc */

#define CONFIG_SYS_BR0_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
#define CONFIG_SYS_OR0_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */

/* Serial Port
 * open - index 2
 * shorted - index 1
 */
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE	\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL			/* Use FSL common I2C driver */
#define CONFIG_SYS_FSL_I2C_SPEED	400000	/* I2C spd and slave address */
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x52

/*
 * I2C2 EEPROM
 */
#define CONFIG_SYS_FSL_I2C2_SPEED	400000	/* I2C spd and slave address */
#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100

#define CONFIG_SYS_I2C_PCA9555_ADDR	0x23

/* enable read and write access to EEPROM */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5

#if defined(CONFIG_PCI)
/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */

/* controller 2, direct to uli, tgtid 2, Base address 9000 */
#define CONFIG_SYS_PCIE2_NAME		"TWR-ELEV PCIe SLOT"
#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
#define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */

/* controller 1, tgtid 1, Base address a000 */
#define CONFIG_SYS_PCIE1_NAME		"mini PCIe SLOT"
#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc00000
#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc00000
#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */

#define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
#endif /* CONFIG_PCI */

#if defined(CONFIG_TSEC_ENET)

#define CONFIG_TSEC1
#define CONFIG_TSEC1_NAME	"eTSEC1"
#undef CONFIG_TSEC2
#undef CONFIG_TSEC2_NAME
#define CONFIG_TSEC3
#define CONFIG_TSEC3_NAME	"eTSEC3"

#define TSEC1_PHY_ADDR	2
#define TSEC2_PHY_ADDR	0
#define TSEC3_PHY_ADDR	1

#define TSEC1_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC3_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)

#define TSEC1_PHYIDX	0
#define TSEC2_PHYIDX	0
#define TSEC3_PHYIDX	0

#define CONFIG_ETHPRIME	"eTSEC1"

#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#undef CONFIG_HAS_ETH2
#endif /* CONFIG_TSEC_ENET */

#ifdef CONFIG_QE
/* QE microcode/firmware address */
#define CONFIG_SYS_QE_FW_ADDR	0xefec0000
#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
#endif /* CONFIG_QE */

#ifdef CONFIG_TWR_P1025
/*
 * QE UEC ethernet configuration
 */
#define CONFIG_MIIM_ADDRESS	(CONFIG_SYS_CCSRBAR + 0x82120)

#undef CONFIG_UEC_ETH
#define CONFIG_PHY_MODE_NEED_CHANGE

#define CONFIG_UEC_ETH1	/* ETH1 */
#define CONFIG_HAS_ETH0

#ifdef CONFIG_UEC_ETH1
#define CONFIG_SYS_UEC1_UCC_NUM	0	/* UCC1 */
#define CONFIG_SYS_UEC1_RX_CLK	QE_CLK12 /* CLK12 for MII */
#define CONFIG_SYS_UEC1_TX_CLK	QE_CLK9 /* CLK9 for MII */
#define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR	0x18	/* 0x18 for MII */
#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
#define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
#endif /* CONFIG_UEC_ETH1 */

#define CONFIG_UEC_ETH5	/* ETH5 */
#define CONFIG_HAS_ETH1

#ifdef CONFIG_UEC_ETH5
#define CONFIG_SYS_UEC5_UCC_NUM	4	/* UCC5 */
#define CONFIG_SYS_UEC5_RX_CLK	QE_CLK_NONE
#define CONFIG_SYS_UEC5_TX_CLK	QE_CLK13 /* CLK 13 for RMII */
#define CONFIG_SYS_UEC5_ETH_TYPE	FAST_ETH
#define CONFIG_SYS_UEC5_PHY_ADDR	0x19	/* 0x19 for RMII */
#define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
#define CONFIG_SYS_UEC5_INTERFACE_SPEED	100
#endif /* CONFIG_UEC_ETH5 */
#endif /* CONFIG_TWR-P1025 */

/*
 * Dynamic MTD Partition support with mtdparts
 */

/*
 * Environment
 */
#ifdef CONFIG_SYS_RAMBOOT
#ifdef CONFIG_RAMBOOT_SDCARD
#define CONFIG_SYS_MMC_ENV_DEV	0
#endif
#endif

#define CONFIG_LOADS_ECHO		/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */

/*
 * USB
 */
#define CONFIG_HAS_FSL_DR_USB

#if defined(CONFIG_HAS_FSL_DR_USB)
#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_EHCI_FSL
#endif
#endif

#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
#endif

#undef CONFIG_WATCHDOG	/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 64 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory for Linux*/
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

/*
 * Environment Configuration
 */
#define CONFIG_HOSTNAME		"unknown"
#define CONFIG_ROOTPATH		"/opt/nfsroot"
#define CONFIG_BOOTFILE		"uImage"
#define CONFIG_UBOOTPATH	u-boot.bin /* U-Boot image on TFTP server */

/* default location for tftp and bootm */
#define CONFIG_LOADADDR	1000000

#define	CONFIG_EXTRA_ENV_SETTINGS	\
"netdev=eth0\0"	\
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"	\
"loadaddr=1000000\0"	\
"bootfile=uImage\0"	\
"dtbfile=twr-p1025twr.dtb\0"	\
"ramdiskfile=rootfs.ext2.gz.uboot\0"	\
"qefirmwarefile=fsl_qe_ucode_1021_10_A.bin\0"	\
"tftpflash=tftpboot $loadaddr $uboot; "	\
	"protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
	"erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
	"protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
"kernelflash=tftpboot $loadaddr $bootfile; "	\
	"protect off 0xefa80000 +$filesize; "	\
	"erase 0xefa80000 +$filesize; "	\
	"cp.b $loadaddr 0xefa80000 $filesize; "	\
	"protect on 0xefa80000 +$filesize; "	\
	"cmp.b $loadaddr 0xefa80000 $filesize\0"	\
"dtbflash=tftpboot $loadaddr $dtbfile; "	\
	"protect off 0xefe80000 +$filesize; "	\
	"erase 0xefe80000 +$filesize; "	\
	"cp.b $loadaddr 0xefe80000 $filesize; "	\
	"protect on 0xefe80000 +$filesize; "	\
	"cmp.b $loadaddr 0xefe80000 $filesize\0"	\
"ramdiskflash=tftpboot $loadaddr $ramdiskfile; "	\
	"protect off 0xeeb80000 +$filesize; "	\
	"erase 0xeeb80000 +$filesize; "	\
	"cp.b $loadaddr 0xeeb80000 $filesize; "	\
	"protect on 0xeeb80000 +$filesize; "	\
	"cmp.b $loadaddr 0xeeb80000 $filesize\0"	\
"qefirmwareflash=tftpboot $loadaddr $qefirmwarefile; "	\
	"protect off 0xefec0000 +$filesize; "	\
	"erase 0xefec0000 +$filesize; "	\
	"cp.b $loadaddr 0xefec0000 $filesize; "	\
	"protect on 0xefec0000 +$filesize; "	\
	"cmp.b $loadaddr 0xefec0000 $filesize\0"	\
"consoledev=ttyS0\0"	\
"ramdiskaddr=2000000\0"	\
"ramdiskfile=rootfs.ext2.gz.uboot\0"	\
"fdtaddr=1e00000\0"	\
"bdev=sda1\0"	\
"norbootaddr=ef080000\0"	\
"norfdtaddr=ef040000\0"	\
"ramdisk_size=120000\0" \
"usbboot=setenv bootargs root=/dev/sda1 rw rootdelay=5 " \
"console=$consoledev,$baudrate $othbootargs ; bootm 0xefa80000 - 0xefe80000"

#define CONFIG_NFSBOOTCOMMAND	\
"setenv bootargs root=/dev/nfs rw "	\
"nfsroot=$serverip:$rootpath "	\
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile&&"	\
"tftp $fdtaddr $fdtfile&&"	\
"bootm $loadaddr - $fdtaddr"

#define CONFIG_HDBOOT	\
"setenv bootargs root=/dev/$bdev rw rootdelay=30 "	\
"console=$consoledev,$baudrate $othbootargs;" \
"usb start;"	\
"ext2load usb 0:1 $loadaddr /boot/$bootfile;"	\
"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"	\
"bootm $loadaddr - $fdtaddr"

#define CONFIG_USB_FAT_BOOT	\
"setenv bootargs root=/dev/ram rw "	\
"console=$consoledev,$baudrate $othbootargs " \
"ramdisk_size=$ramdisk_size;"	\
"usb start;"	\
"fatload usb 0:2 $loadaddr $bootfile;"	\
"fatload usb 0:2 $fdtaddr $fdtfile;"	\
"fatload usb 0:2 $ramdiskaddr $ramdiskfile;"	\
"bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_USB_EXT2_BOOT	\
"setenv bootargs root=/dev/ram rw "	\
"console=$consoledev,$baudrate $othbootargs " \
"ramdisk_size=$ramdisk_size;"	\
"usb start;"	\
"ext2load usb 0:4 $loadaddr $bootfile;"	\
"ext2load usb 0:4 $fdtaddr $fdtfile;" \
"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_NORBOOT	\
"setenv bootargs root=/dev/mtdblock3 rw "	\
"console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;"	\
"bootm $norbootaddr - $norfdtaddr"

#define CONFIG_RAMBOOTCOMMAND_TFTP	\
"setenv bootargs root=/dev/ram rw "	\
"console=$consoledev,$baudrate $othbootargs " \
"ramdisk_size=$ramdisk_size;"	\
"tftp $ramdiskaddr $ramdiskfile;"	\
"tftp $loadaddr $bootfile;"	\
"tftp $fdtaddr $fdtfile;"	\
"bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND	\
"setenv bootargs root=/dev/ram rw "	\
"console=$consoledev,$baudrate $othbootargs " \
"ramdisk_size=$ramdisk_size;"	\
"bootm 0xefa80000 0xeeb80000 0xefe80000"

#define CONFIG_BOOTCOMMAND	CONFIG_RAMBOOTCOMMAND

#endif /* __CONFIG_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
49f5befa XX	2	/*
49f5befa XX	3	* Copyright 2013 Freescale Semiconductor, Inc.
49f5befa XX	4	*/
	5
	6	/*
	7	* QorIQ P1 Tower boards configuration file
	8	*/
	9	#ifndef __CONFIG_H
	10	#define __CONFIG_H
	11
1af3c7f4 SG	12	#include <linux/stringify.h>
1af3c7f4 SG	13
49f5befa XX	14	#if defined(CONFIG_TWR_P1025)
49f5befa XX	15	#define CONFIG_BOARDNAME "TWR-P1025"
49f5befa XX	16	#define CONFIG_SYS_LBC_LBCR 0x00080000 /* Conversion of LBC addr */
	17	#define CONFIG_SYS_LBC_LCRR 0x80000002 /* LB clock ratio reg */
	18	#endif
	19
	20	#ifdef CONFIG_SDCARD
	21	#define CONFIG_RAMBOOT_SDCARD
	22	#define CONFIG_SYS_RAMBOOT
e222b1f3	23	#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
49f5befa XX	24	#endif
49f5befa XX	25
49f5befa XX	26	#ifndef CONFIG_RESET_VECTOR_ADDRESS
	27	#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
	28	#endif
	29
	30	#ifndef CONFIG_SYS_MONITOR_BASE
	31	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
	32	#endif
	33
b38eaec5 RD	34	#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
b38eaec5 RD	35	#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
49f5befa XX	36	#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
49f5befa XX	37	#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
49f5befa XX	38	#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
49f5befa XX	39
49f5befa XX	40	#define CONFIG_ENV_OVERWRITE
49f5befa XX	41
49f5befa	42	#define CONFIG_SYS_SATA_MAX_DEVICE 2
49f5befa XX	43	#define CONFIG_LBA48
	44
	45	#ifndef __ASSEMBLY__
	46	extern unsigned long get_board_sys_clk(unsigned long dummy);
	47	#endif
	48	#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /sysclk for TWR-P1025 /
	49
	50	#define CONFIG_DDR_CLK_FREQ 66666666
	51
	52	#define CONFIG_HWCONFIG
	53	/*
	54	* These can be toggled for performance analysis, otherwise use default.
	55	*/
	56	#define CONFIG_L2_CACHE
	57	#define CONFIG_BTB
	58
49f5befa XX	59	#define CONFIG_SYS_CCSRBAR 0xffe00000
	60	#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
	61
	62	/* DDR Setup */
49f5befa XX	63
	64	#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
	65	#define CONFIG_CHIP_SELECTS_PER_CTRL 1
	66
	67	#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
	68	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
	69	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	70
49f5befa XX	71	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	72
	73	/* Default settings for DDR3 */
	74	#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
	75	#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
	76	#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
	77	#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
	78	#define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
	79	#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
	80
	81	#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
	82	#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
	83	#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
	84	#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
	85
	86	#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
	87	#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655a608
	88	#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
	89	#define CONFIG_SYS_DDR_RCW_1 0x00000000
	90	#define CONFIG_SYS_DDR_RCW_2 0x00000000
	91	#define CONFIG_SYS_DDR_CONTROL 0xc70c0000 /* Type = DDR3 */
	92	#define CONFIG_SYS_DDR_CONTROL_2 0x04401050
	93	#define CONFIG_SYS_DDR_TIMING_4 0x00220001
	94	#define CONFIG_SYS_DDR_TIMING_5 0x03402400
	95
	96	#define CONFIG_SYS_DDR_TIMING_3 0x00020000
	97	#define CONFIG_SYS_DDR_TIMING_0 0x00220004
	98	#define CONFIG_SYS_DDR_TIMING_1 0x5c5b6544
	99	#define CONFIG_SYS_DDR_TIMING_2 0x0fa880de
	100	#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
	101	#define CONFIG_SYS_DDR_MODE_1 0x80461320
	102	#define CONFIG_SYS_DDR_MODE_2 0x00008000
	103	#define CONFIG_SYS_DDR_INTERVAL 0x09480000
	104
	105	/*
	106	* Memory map
	107	*
	108	* 0x0000_0000 0x1fff_ffff DDR Up to 512MB cacheable
	109	* 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
	110	* 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
	111	*
	112	* Localbus
	113	* 0xe000_0000 0xe002_0000 SSD1289 128K non-cacheable
	114	* 0xec00_0000 0xefff_ffff FLASH Up to 64M non-cacheable
	115	*
	116	* 0xff90_0000 0xff97_ffff L2 SRAM Up to 512K cacheable
	117	* 0xffd0_0000 0xffd0_3fff init ram 16K Cacheable
	118	* 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
	119	*/
	120
	121	/*
	122	* Local Bus Definitions
	123	*/
	124	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
	125	#define CONFIG_SYS_FLASH_BASE 0xec000000
	126
	127	#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
	128
	129	#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \
	130	\| BR_PS_16 \| BR_V)
	131
	132	#define CONFIG_FLASH_OR_PRELIM 0xfc0000b1
	133
	134	#define CONFIG_SYS_SSD_BASE 0xe0000000
135	#define CONFIG_SYS_SSD_BASE_PHYS CONFIG_SYS_SSD_BASE
136	#define CONFIG_SSD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_SSD_BASE_PHYS) \| \
137	BR_PS_16 \| BR_V)
138	#define CONFIG_SSD_OR_PRELIM (OR_AM_64KB \| OR_GPCM_CSNT \| OR_GPCM_XACS \| \
139	OR_GPCM_ACS_DIV2 \| OR_GPCM_SCY \| \
140	OR_GPCM_TRLX \| OR_GPCM_EHTR \| OR_GPCM_EAD)
141
142	#define CONFIG_SYS_BR2_PRELIM CONFIG_SSD_BR_PRELIM
143	#define CONFIG_SYS_OR2_PRELIM CONFIG_SSD_OR_PRELIM
144
145	#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
146	#define CONFIG_SYS_FLASH_QUIET_TEST
147	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
148
149	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
150
151	#undef CONFIG_SYS_FLASH_CHECKSUM
152	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
153	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
154
49f5befa	155	#define CONFIG_SYS_FLASH_EMPTY_INFO
49f5befa	156
49f5befa XX	157	#define CONFIG_SYS_INIT_RAM_LOCK
	158	#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
	159	/* Initial L1 address */
	160	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
	161	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
	162	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
	163	/* Size of used area in RAM */
	164	#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
	165
	166	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
	167	GENERATED_GBL_DATA_SIZE)
	168	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	169
9307cbab	170	#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
49f5befa XX	171	#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
	172
	173	#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
	174	#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
	175
	176	/* Serial Port
	177	* open - index 2
	178	* shorted - index 1
	179	*/
49f5befa	180	#undef CONFIG_SERIAL_SOFTWARE_FIFO
49f5befa XX	181	#define CONFIG_SYS_NS16550_SERIAL
	182	#define CONFIG_SYS_NS16550_REG_SIZE 1
	183	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
	184
	185	#define CONFIG_SYS_BAUDRATE_TABLE \
	186	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
	187
	188	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
	189	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
	190
49f5befa XX	191	/* I2C */
	192	#define CONFIG_SYS_I2C
	193	#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
	194	#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C spd and slave address */
	195	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	196	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	197	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
	198
	199	/*
	200	* I2C2 EEPROM
	201	*/
	202	#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C spd and slave address */
	203	#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
	204	#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
	205
	206	#define CONFIG_SYS_I2C_PCA9555_ADDR 0x23
	207
	208	/* enable read and write access to EEPROM */
49f5befa XX	209	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	210	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	211	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
	212
49f5befa XX	213	#if defined(CONFIG_PCI)
	214	/*
	215	* General PCI
	216	* Memory space is mapped 1-1, but I/O space must start from 0.
	217	*/
	218
	219	/* controller 2, direct to uli, tgtid 2, Base address 9000 */
	220	#define CONFIG_SYS_PCIE2_NAME "TWR-ELEV PCIe SLOT"
	221	#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
	222	#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
	223	#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
	224	#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
	225	#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
	226	#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
	227	#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
	228	#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
	229
	230	/* controller 1, tgtid 1, Base address a000 */
	231	#define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
	232	#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
	233	#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
	234	#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
	235	#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
	236	#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
	237	#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
	238	#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
	239	#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
	240
49f5befa	241	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
49f5befa XX	242	#endif /* CONFIG_PCI */
	243
	244	#if defined(CONFIG_TSEC_ENET)
	245
49f5befa XX	246	#define CONFIG_TSEC1
	247	#define CONFIG_TSEC1_NAME "eTSEC1"
	248	#undef CONFIG_TSEC2
	249	#undef CONFIG_TSEC2_NAME
	250	#define CONFIG_TSEC3
	251	#define CONFIG_TSEC3_NAME "eTSEC3"
	252
	253	#define TSEC1_PHY_ADDR 2
	254	#define TSEC2_PHY_ADDR 0
	255	#define TSEC3_PHY_ADDR 1
	256
	257	#define TSEC1_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	258	#define TSEC2_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	259	#define TSEC3_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	260
	261	#define TSEC1_PHYIDX 0
	262	#define TSEC2_PHYIDX 0
	263	#define TSEC3_PHYIDX 0
	264
	265	#define CONFIG_ETHPRIME "eTSEC1"
	266
49f5befa XX	267	#define CONFIG_HAS_ETH0
	268	#define CONFIG_HAS_ETH1
	269	#undef CONFIG_HAS_ETH2
	270	#endif /* CONFIG_TSEC_ENET */
	271
	272	#ifdef CONFIG_QE
	273	/* QE microcode/firmware address */
dcf1d774	274	#define CONFIG_SYS_QE_FW_ADDR 0xefec0000
49f5befa XX	275	#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
	276	#endif /* CONFIG_QE */
	277
	278	#ifdef CONFIG_TWR_P1025
	279	/*
	280	* QE UEC ethernet configuration
	281	*/
	282	#define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
	283
	284	#undef CONFIG_UEC_ETH
	285	#define CONFIG_PHY_MODE_NEED_CHANGE
	286
	287	#define CONFIG_UEC_ETH1 /* ETH1 */
	288	#define CONFIG_HAS_ETH0
	289
	290	#ifdef CONFIG_UEC_ETH1
	291	#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
	292	#define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */
	293	#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */
	294	#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
	295	#define CONFIG_SYS_UEC1_PHY_ADDR 0x18 /* 0x18 for MII */
	296	#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
	297	#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
	298	#endif /* CONFIG_UEC_ETH1 */
	299
	300	#define CONFIG_UEC_ETH5 /* ETH5 */
	301	#define CONFIG_HAS_ETH1
	302
	303	#ifdef CONFIG_UEC_ETH5
	304	#define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */
	305	#define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
	306	#define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */
	307	#define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
	308	#define CONFIG_SYS_UEC5_PHY_ADDR 0x19 /* 0x19 for RMII */
	309	#define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
	310	#define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
	311	#endif /* CONFIG_UEC_ETH5 */
	312	#endif /* CONFIG_TWR-P1025 */
	313
94b383e7 YL	314	/*
	315	* Dynamic MTD Partition support with mtdparts
	316	*/
94b383e7	317
49f5befa XX	318	/*
	319	* Environment
	320	*/
	321	#ifdef CONFIG_SYS_RAMBOOT
	322	#ifdef CONFIG_RAMBOOT_SDCARD
49f5befa	323	#define CONFIG_SYS_MMC_ENV_DEV 0
49f5befa	324	#endif
49f5befa XX	325	#endif
	326
	327	#define CONFIG_LOADS_ECHO /* echo on for serial download */
	328	#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
	329
49f5befa XX	330	/*
	331	* USB
	332	*/
	333	#define CONFIG_HAS_FSL_DR_USB
	334
	335	#if defined(CONFIG_HAS_FSL_DR_USB)
8850c5d5	336	#ifdef CONFIG_USB_EHCI_HCD
49f5befa XX	337	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
49f5befa XX	338	#define CONFIG_USB_EHCI_FSL
49f5befa XX	339	#endif
	340	#endif
	341
49f5befa	342	#ifdef CONFIG_MMC
49f5befa	343	#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
49f5befa XX	344	#endif
49f5befa XX	345
49f5befa XX	346	#undef CONFIG_WATCHDOG /* watchdog disabled */
	347
	348	/*
	349	* Miscellaneous configurable options
	350	*/
49f5befa	351	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
49f5befa XX	352
	353	/*
	354	* For booting Linux, the board info and command line data
	355	* have to be in the first 64 MB of memory, since this is
	356	* the maximum mapped by the Linux kernel during initialization.
	357	*/
	358	#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
	359	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
	360
	361	/*
	362	* Environment Configuration
	363	*/
5bc0543d	364	#define CONFIG_HOSTNAME "unknown"
49f5befa XX	365	#define CONFIG_ROOTPATH "/opt/nfsroot"
	366	#define CONFIG_BOOTFILE "uImage"
	367	#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
	368
	369	/* default location for tftp and bootm */
	370	#define CONFIG_LOADADDR 1000000
	371
49f5befa XX	372	#define CONFIG_EXTRA_ENV_SETTINGS \
	373	"netdev=eth0\0" \
	374	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
	375	"loadaddr=1000000\0" \
	376	"bootfile=uImage\0" \
	377	"dtbfile=twr-p1025twr.dtb\0" \
	378	"ramdiskfile=rootfs.ext2.gz.uboot\0" \
	379	"qefirmwarefile=fsl_qe_ucode_1021_10_A.bin\0" \
	380	"tftpflash=tftpboot $loadaddr $uboot; " \
	381	"protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
	382	"erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
	383	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
	384	"protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
	385	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
	386	"kernelflash=tftpboot $loadaddr $bootfile; " \
	387	"protect off 0xefa80000 +$filesize; " \
	388	"erase 0xefa80000 +$filesize; " \
	389	"cp.b $loadaddr 0xefa80000 $filesize; " \
	390	"protect on 0xefa80000 +$filesize; " \
	391	"cmp.b $loadaddr 0xefa80000 $filesize\0" \
	392	"dtbflash=tftpboot $loadaddr $dtbfile; " \
	393	"protect off 0xefe80000 +$filesize; " \
	394	"erase 0xefe80000 +$filesize; " \
	395	"cp.b $loadaddr 0xefe80000 $filesize; " \
	396	"protect on 0xefe80000 +$filesize; " \
	397	"cmp.b $loadaddr 0xefe80000 $filesize\0" \
	398	"ramdiskflash=tftpboot $loadaddr $ramdiskfile; " \
	399	"protect off 0xeeb80000 +$filesize; " \
	400	"erase 0xeeb80000 +$filesize; " \
	401	"cp.b $loadaddr 0xeeb80000 $filesize; " \
	402	"protect on 0xeeb80000 +$filesize; " \
	403	"cmp.b $loadaddr 0xeeb80000 $filesize\0" \
	404	"qefirmwareflash=tftpboot $loadaddr $qefirmwarefile; " \
	405	"protect off 0xefec0000 +$filesize; " \
	406	"erase 0xefec0000 +$filesize; " \
	407	"cp.b $loadaddr 0xefec0000 $filesize; " \
	408	"protect on 0xefec0000 +$filesize; " \
	409	"cmp.b $loadaddr 0xefec0000 $filesize\0" \
	410	"consoledev=ttyS0\0" \
	411	"ramdiskaddr=2000000\0" \
	412	"ramdiskfile=rootfs.ext2.gz.uboot\0" \
b24a4f62	413	"fdtaddr=1e00000\0" \
49f5befa XX	414	"bdev=sda1\0" \
	415	"norbootaddr=ef080000\0" \
	416	"norfdtaddr=ef040000\0" \
	417	"ramdisk_size=120000\0" \
	418	"usbboot=setenv bootargs root=/dev/sda1 rw rootdelay=5 " \
	419	"console=$consoledev,$baudrate $othbootargs ; bootm 0xefa80000 - 0xefe80000"
	420
	421	#define CONFIG_NFSBOOTCOMMAND \
	422	"setenv bootargs root=/dev/nfs rw " \
	423	"nfsroot=$serverip:$rootpath " \
	424	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
	425	"console=$consoledev,$baudrate $othbootargs;" \
	426	"tftp $loadaddr $bootfile&&" \
	427	"tftp $fdtaddr $fdtfile&&" \
	428	"bootm $loadaddr - $fdtaddr"
	429
	430	#define CONFIG_HDBOOT \
	431	"setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
	432	"console=$consoledev,$baudrate $othbootargs;" \
	433	"usb start;" \
	434	"ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
	435	"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
	436	"bootm $loadaddr - $fdtaddr"
	437
	438	#define CONFIG_USB_FAT_BOOT \
	439	"setenv bootargs root=/dev/ram rw " \
	440	"console=$consoledev,$baudrate $othbootargs " \
	441	"ramdisk_size=$ramdisk_size;" \
	442	"usb start;" \
	443	"fatload usb 0:2 $loadaddr $bootfile;" \
	444	"fatload usb 0:2 $fdtaddr $fdtfile;" \
	445	"fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
	446	"bootm $loadaddr $ramdiskaddr $fdtaddr"
	447
	448	#define CONFIG_USB_EXT2_BOOT \
	449	"setenv bootargs root=/dev/ram rw " \
	450	"console=$consoledev,$baudrate $othbootargs " \
	451	"ramdisk_size=$ramdisk_size;" \
	452	"usb start;" \
	453	"ext2load usb 0:4 $loadaddr $bootfile;" \
	454	"ext2load usb 0:4 $fdtaddr $fdtfile;" \
	455	"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
	456	"bootm $loadaddr $ramdiskaddr $fdtaddr"
	457
	458	#define CONFIG_NORBOOT \
	459	"setenv bootargs root=/dev/mtdblock3 rw " \
	460	"console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
	461	"bootm $norbootaddr - $norfdtaddr"
	462
	463	#define CONFIG_RAMBOOTCOMMAND_TFTP \
	464	"setenv bootargs root=/dev/ram rw " \
	465	"console=$consoledev,$baudrate $othbootargs " \
	466	"ramdisk_size=$ramdisk_size;" \
	467	"tftp $ramdiskaddr $ramdiskfile;" \
	468	"tftp $loadaddr $bootfile;" \
	469	"tftp $fdtaddr $fdtfile;" \
	470	"bootm $loadaddr $ramdiskaddr $fdtaddr"
	471
	472	#define CONFIG_RAMBOOTCOMMAND \
	473	"setenv bootargs root=/dev/ram rw " \
	474	"console=$consoledev,$baudrate $othbootargs " \
	475	"ramdisk_size=$ramdisk_size;" \
	476	"bootm 0xefa80000 0xeeb80000 0xefe80000"
	477
478	#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
479
480	#endif /* __CONFIG_H */