[people/ms/u-boot.git] / include / configs / p1_twr.h

/*
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * QorIQ P1 Tower boards configuration file
 */
#ifndef __CONFIG_H
#define __CONFIG_H

#if defined(CONFIG_TWR_P1025)
#define CONFIG_BOARDNAME "TWR-P1025"
#define CONFIG_PHY_ATHEROS
#define CONFIG_QE
#define CONFIG_SYS_LBC_LBCR	0x00080000	/* Conversion of LBC addr */
#define CONFIG_SYS_LBC_LCRR	0x80000002	/* LB clock ratio reg */
#endif

#ifdef CONFIG_SDCARD
#define CONFIG_RAMBOOT_SDCARD
#define CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_SYS_TEXT_BASE		0x11000000
#define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
#endif

#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE		0xeff40000
#endif

#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
#endif

#ifndef CONFIG_SYS_MONITOR_BASE
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
#endif

#define CONFIG_MP

#define CONFIG_PCIE1	/* PCIE controller 1 (slot 1) */
#define CONFIG_PCIE2	/* PCIE controller 2 (slot 2) */
#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET	/* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */

#define CONFIG_TSEC_ENET	/* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_CMD_SATA
#define CONFIG_SATA_SIL3114
#define CONFIG_SYS_SATA_MAX_DEVICE	2
#define CONFIG_LIBATA
#define CONFIG_LBA48

#ifndef __ASSEMBLY__
extern unsigned long get_board_sys_clk(unsigned long dummy);
#endif
#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /*sysclk for TWR-P1025 */

#define CONFIG_DDR_CLK_FREQ	66666666

#define CONFIG_HWCONFIG
/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE
#define CONFIG_BTB

#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x1fffffff
#define CONFIG_PANIC_HANG	/* do not reset board on panic */

#define CONFIG_SYS_CCSRBAR		0xffe00000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR

/* DDR Setup */

#define CONFIG_SYS_SDRAM_SIZE_LAW	LAW_SIZE_512M
#define CONFIG_CHIP_SELECTS_PER_CTRL	1

#define CONFIG_SYS_SDRAM_SIZE		(1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

#define CONFIG_DIMM_SLOTS_PER_CTLR	1

/* Default settings for DDR3 */
#define CONFIG_SYS_DDR_CS0_BNDS		0x0000001f
#define CONFIG_SYS_DDR_CS0_CONFIG	0x80014202
#define CONFIG_SYS_DDR_CS0_CONFIG_2	0x00000000
#define CONFIG_SYS_DDR_CS1_BNDS		0x00000000
#define CONFIG_SYS_DDR_CS1_CONFIG	0x00000000
#define CONFIG_SYS_DDR_CS1_CONFIG_2	0x00000000

#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
#define CONFIG_SYS_DDR_INIT_ADDR	0x00000000
#define CONFIG_SYS_DDR_INIT_EXT_ADDR	0x00000000
#define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000

#define CONFIG_SYS_DDR_ZQ_CONTROL	0x89080600
#define CONFIG_SYS_DDR_WRLVL_CONTROL	0x8655a608
#define CONFIG_SYS_DDR_SR_CNTR		0x00000000
#define CONFIG_SYS_DDR_RCW_1		0x00000000
#define CONFIG_SYS_DDR_RCW_2		0x00000000
#define CONFIG_SYS_DDR_CONTROL		0xc70c0000	/* Type = DDR3	*/
#define CONFIG_SYS_DDR_CONTROL_2	0x04401050
#define CONFIG_SYS_DDR_TIMING_4		0x00220001
#define CONFIG_SYS_DDR_TIMING_5		0x03402400

#define CONFIG_SYS_DDR_TIMING_3		0x00020000
#define CONFIG_SYS_DDR_TIMING_0		0x00220004
#define CONFIG_SYS_DDR_TIMING_1		0x5c5b6544
#define CONFIG_SYS_DDR_TIMING_2		0x0fa880de
#define CONFIG_SYS_DDR_CLK_CTRL		0x03000000
#define CONFIG_SYS_DDR_MODE_1		0x80461320
#define CONFIG_SYS_DDR_MODE_2		0x00008000
#define CONFIG_SYS_DDR_INTERVAL		0x09480000

/*
 * Memory map
 *
 * 0x0000_0000 0x1fff_ffff	DDR		Up to 512MB cacheable
 * 0x8000_0000 0xdfff_ffff	PCI Express Mem	1.5G non-cacheable(PCIe * 3)
 * 0xffc0_0000 0xffc3_ffff	PCI IO range	256k non-cacheable
 *
 * Localbus
 * 0xe000_0000 0xe002_0000	SSD1289		128K non-cacheable
 * 0xec00_0000 0xefff_ffff	FLASH		Up to 64M non-cacheable
 *
 * 0xff90_0000 0xff97_ffff	L2 SRAM		Up to 512K cacheable
 * 0xffd0_0000 0xffd0_3fff	init ram	16K Cacheable
 * 0xffe0_0000 0xffef_ffff	CCSR		1M non-cacheable
 */

/*
 * Local Bus Definitions
 */
#define CONFIG_SYS_MAX_FLASH_SECT	512	/* 64M */
#define CONFIG_SYS_FLASH_BASE		0xec000000

#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE

#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \
	| BR_PS_16 | BR_V)

#define CONFIG_FLASH_OR_PRELIM	0xfc0000b1

#define CONFIG_SYS_SSD_BASE	0xe0000000
#define CONFIG_SYS_SSD_BASE_PHYS	CONFIG_SYS_SSD_BASE
#define CONFIG_SSD_BR_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_SSD_BASE_PHYS) | \
					BR_PS_16 | BR_V)
#define CONFIG_SSD_OR_PRELIM	(OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
				 OR_GPCM_ACS_DIV2 | OR_GPCM_SCY | \
				 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)

#define CONFIG_SYS_BR2_PRELIM CONFIG_SSD_BR_PRELIM
#define CONFIG_SYS_OR2_PRELIM CONFIG_SSD_OR_PRELIM

#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */

#undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE

#define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */

#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000
/* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS	CONFIG_SYS_INIT_RAM_ADDR
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
/* Size of used area in RAM */
#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
					GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
#define CONFIG_SYS_MALLOC_LEN	(1024 * 1024)/* Reserved for malloc */

#define CONFIG_SYS_BR0_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
#define CONFIG_SYS_OR0_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */

/* Serial Port
 * open - index 2
 * shorted - index 1
 */
#define CONFIG_CONS_INDEX		1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE	\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL			/* Use FSL common I2C driver */
#define CONFIG_SYS_FSL_I2C_SPEED	400000	/* I2C spd and slave address */
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x52

/*
 * I2C2 EEPROM
 */
#define CONFIG_SYS_FSL_I2C2_SPEED	400000	/* I2C spd and slave address */
#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100

#define CONFIG_SYS_I2C_PCA9555_ADDR	0x23

/* enable read and write access to EEPROM */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5

/*
 * eSPI - Enhanced SPI
 */
#define CONFIG_HARD_SPI

#if defined(CONFIG_PCI)
/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */

/* controller 2, direct to uli, tgtid 2, Base address 9000 */
#define CONFIG_SYS_PCIE2_NAME		"TWR-ELEV PCIe SLOT"
#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
#define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */

/* controller 1, tgtid 1, Base address a000 */
#define CONFIG_SYS_PCIE1_NAME		"mini PCIe SLOT"
#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc00000
#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc00000
#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */

#define CONFIG_CMD_PCI

#define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
#endif /* CONFIG_PCI */

#if defined(CONFIG_TSEC_ENET)

#define CONFIG_MII		/* MII PHY management */
#define CONFIG_TSEC1
#define CONFIG_TSEC1_NAME	"eTSEC1"
#undef CONFIG_TSEC2
#undef CONFIG_TSEC2_NAME
#define CONFIG_TSEC3
#define CONFIG_TSEC3_NAME	"eTSEC3"

#define TSEC1_PHY_ADDR	2
#define TSEC2_PHY_ADDR	0
#define TSEC3_PHY_ADDR	1

#define TSEC1_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC3_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)

#define TSEC1_PHYIDX	0
#define TSEC2_PHYIDX	0
#define TSEC3_PHYIDX	0

#define CONFIG_ETHPRIME	"eTSEC1"

#define CONFIG_PHY_GIGE	1	/* Include GbE speed/duplex detection */

#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#undef CONFIG_HAS_ETH2
#endif /* CONFIG_TSEC_ENET */

#ifdef CONFIG_QE
/* QE microcode/firmware address */
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#define CONFIG_SYS_QE_FW_ADDR	0xefec0000
#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
#endif /* CONFIG_QE */

#ifdef CONFIG_TWR_P1025
/*
 * QE UEC ethernet configuration
 */
#define CONFIG_MIIM_ADDRESS	(CONFIG_SYS_CCSRBAR + 0x82120)

#undef CONFIG_UEC_ETH
#define CONFIG_PHY_MODE_NEED_CHANGE

#define CONFIG_UEC_ETH1	/* ETH1 */
#define CONFIG_HAS_ETH0

#ifdef CONFIG_UEC_ETH1
#define CONFIG_SYS_UEC1_UCC_NUM	0	/* UCC1 */
#define CONFIG_SYS_UEC1_RX_CLK	QE_CLK12 /* CLK12 for MII */
#define CONFIG_SYS_UEC1_TX_CLK	QE_CLK9 /* CLK9 for MII */
#define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR	0x18	/* 0x18 for MII */
#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
#define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
#endif /* CONFIG_UEC_ETH1 */

#define CONFIG_UEC_ETH5	/* ETH5 */
#define CONFIG_HAS_ETH1

#ifdef CONFIG_UEC_ETH5
#define CONFIG_SYS_UEC5_UCC_NUM	4	/* UCC5 */
#define CONFIG_SYS_UEC5_RX_CLK	QE_CLK_NONE
#define CONFIG_SYS_UEC5_TX_CLK	QE_CLK13 /* CLK 13 for RMII */
#define CONFIG_SYS_UEC5_ETH_TYPE	FAST_ETH
#define CONFIG_SYS_UEC5_PHY_ADDR	0x19	/* 0x19 for RMII */
#define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
#define CONFIG_SYS_UEC5_INTERFACE_SPEED	100
#endif /* CONFIG_UEC_ETH5 */
#endif /* CONFIG_TWR-P1025 */

/*
 * Dynamic MTD Partition support with mtdparts
 */
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_CMD_MTDPARTS
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT "nor0=ec000000.nor"
#define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:256k(vsc7385-firmware)," \
			"256k(dtb),5632k(kernel),57856k(fs)," \
			"256k(qe-ucode-firmware),1280k(u-boot)"

/*
 * Environment
 */
#ifdef CONFIG_SYS_RAMBOOT
#ifdef CONFIG_RAMBOOT_SDCARD
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_SYS_MMC_ENV_DEV	0
#else
#define CONFIG_ENV_IS_NOWHERE	/* Store ENV in memory only */
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE		0x2000
#endif
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
#endif

#define CONFIG_LOADS_ECHO		/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */

/*
 * Command line configuration.
 */
#define CONFIG_CMD_REGINFO

/*
 * USB
 */
#define CONFIG_HAS_FSL_DR_USB

#if defined(CONFIG_HAS_FSL_DR_USB)
#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_EHCI_FSL
#endif
#endif

#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
#endif

#undef CONFIG_WATCHDOG	/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory */
#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 64 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory for Linux*/
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

/*
 * Environment Configuration
 */
#define CONFIG_HOSTNAME		unknown
#define CONFIG_ROOTPATH		"/opt/nfsroot"
#define CONFIG_BOOTFILE		"uImage"
#define CONFIG_UBOOTPATH	u-boot.bin /* U-Boot image on TFTP server */

/* default location for tftp and bootm */
#define CONFIG_LOADADDR	1000000

#define CONFIG_BOOTARGS	/* the boot command will set bootargs */

#define	CONFIG_EXTRA_ENV_SETTINGS	\
"netdev=eth0\0"	\
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"	\
"loadaddr=1000000\0"	\
"bootfile=uImage\0"	\
"dtbfile=twr-p1025twr.dtb\0"	\
"ramdiskfile=rootfs.ext2.gz.uboot\0"	\
"qefirmwarefile=fsl_qe_ucode_1021_10_A.bin\0"	\
"tftpflash=tftpboot $loadaddr $uboot; "	\
	"protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
	"erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
	"protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
"kernelflash=tftpboot $loadaddr $bootfile; "	\
	"protect off 0xefa80000 +$filesize; "	\
	"erase 0xefa80000 +$filesize; "	\
	"cp.b $loadaddr 0xefa80000 $filesize; "	\
	"protect on 0xefa80000 +$filesize; "	\
	"cmp.b $loadaddr 0xefa80000 $filesize\0"	\
"dtbflash=tftpboot $loadaddr $dtbfile; "	\
	"protect off 0xefe80000 +$filesize; "	\
	"erase 0xefe80000 +$filesize; "	\
	"cp.b $loadaddr 0xefe80000 $filesize; "	\
	"protect on 0xefe80000 +$filesize; "	\
	"cmp.b $loadaddr 0xefe80000 $filesize\0"	\
"ramdiskflash=tftpboot $loadaddr $ramdiskfile; "	\
	"protect off 0xeeb80000 +$filesize; "	\
	"erase 0xeeb80000 +$filesize; "	\
	"cp.b $loadaddr 0xeeb80000 $filesize; "	\
	"protect on 0xeeb80000 +$filesize; "	\
	"cmp.b $loadaddr 0xeeb80000 $filesize\0"	\
"qefirmwareflash=tftpboot $loadaddr $qefirmwarefile; "	\
	"protect off 0xefec0000 +$filesize; "	\
	"erase 0xefec0000 +$filesize; "	\
	"cp.b $loadaddr 0xefec0000 $filesize; "	\
	"protect on 0xefec0000 +$filesize; "	\
	"cmp.b $loadaddr 0xefec0000 $filesize\0"	\
"consoledev=ttyS0\0"	\
"ramdiskaddr=2000000\0"	\
"ramdiskfile=rootfs.ext2.gz.uboot\0"	\
"fdtaddr=1e00000\0"	\
"bdev=sda1\0"	\
"norbootaddr=ef080000\0"	\
"norfdtaddr=ef040000\0"	\
"ramdisk_size=120000\0" \
"usbboot=setenv bootargs root=/dev/sda1 rw rootdelay=5 " \
"console=$consoledev,$baudrate $othbootargs ; bootm 0xefa80000 - 0xefe80000"

#define CONFIG_NFSBOOTCOMMAND	\
"setenv bootargs root=/dev/nfs rw "	\
"nfsroot=$serverip:$rootpath "	\
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile&&"	\
"tftp $fdtaddr $fdtfile&&"	\
"bootm $loadaddr - $fdtaddr"

#define CONFIG_HDBOOT	\
"setenv bootargs root=/dev/$bdev rw rootdelay=30 "	\
"console=$consoledev,$baudrate $othbootargs;" \
"usb start;"	\
"ext2load usb 0:1 $loadaddr /boot/$bootfile;"	\
"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"	\
"bootm $loadaddr - $fdtaddr"

#define CONFIG_USB_FAT_BOOT	\
"setenv bootargs root=/dev/ram rw "	\
"console=$consoledev,$baudrate $othbootargs " \
"ramdisk_size=$ramdisk_size;"	\
"usb start;"	\
"fatload usb 0:2 $loadaddr $bootfile;"	\
"fatload usb 0:2 $fdtaddr $fdtfile;"	\
"fatload usb 0:2 $ramdiskaddr $ramdiskfile;"	\
"bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_USB_EXT2_BOOT	\
"setenv bootargs root=/dev/ram rw "	\
"console=$consoledev,$baudrate $othbootargs " \
"ramdisk_size=$ramdisk_size;"	\
"usb start;"	\
"ext2load usb 0:4 $loadaddr $bootfile;"	\
"ext2load usb 0:4 $fdtaddr $fdtfile;" \
"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_NORBOOT	\
"setenv bootargs root=/dev/mtdblock3 rw "	\
"console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;"	\
"bootm $norbootaddr - $norfdtaddr"

#define CONFIG_RAMBOOTCOMMAND_TFTP	\
"setenv bootargs root=/dev/ram rw "	\
"console=$consoledev,$baudrate $othbootargs " \
"ramdisk_size=$ramdisk_size;"	\
"tftp $ramdiskaddr $ramdiskfile;"	\
"tftp $loadaddr $bootfile;"	\
"tftp $fdtaddr $fdtfile;"	\
"bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND	\
"setenv bootargs root=/dev/ram rw "	\
"console=$consoledev,$baudrate $othbootargs " \
"ramdisk_size=$ramdisk_size;"	\
"bootm 0xefa80000 0xeeb80000 0xefe80000"

#define CONFIG_BOOTCOMMAND	CONFIG_RAMBOOTCOMMAND

#endif /* __CONFIG_H */
Commit	Line	Data
49f5befa XX	1	/*
	2	* Copyright 2013 Freescale Semiconductor, Inc.
	3	*
3aab0cd8	4	* SPDX-License-Identifier: GPL-2.0+
49f5befa XX	5	*/
	6
	7	/*
	8	* QorIQ P1 Tower boards configuration file
	9	*/
	10	#ifndef __CONFIG_H
	11	#define __CONFIG_H
	12
	13	#if defined(CONFIG_TWR_P1025)
	14	#define CONFIG_BOARDNAME "TWR-P1025"
49f5befa XX	15	#define CONFIG_PHY_ATHEROS
	16	#define CONFIG_QE
	17	#define CONFIG_SYS_LBC_LBCR 0x00080000 /* Conversion of LBC addr */
	18	#define CONFIG_SYS_LBC_LCRR 0x80000002 /* LB clock ratio reg */
	19	#endif
	20
	21	#ifdef CONFIG_SDCARD
	22	#define CONFIG_RAMBOOT_SDCARD
	23	#define CONFIG_SYS_RAMBOOT
	24	#define CONFIG_SYS_EXTRA_ENV_RELOC
	25	#define CONFIG_SYS_TEXT_BASE 0x11000000
e222b1f3	26	#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
49f5befa XX	27	#endif
	28
	29	#ifndef CONFIG_SYS_TEXT_BASE
e222b1f3	30	#define CONFIG_SYS_TEXT_BASE 0xeff40000
49f5befa XX	31	#endif
	32
	33	#ifndef CONFIG_RESET_VECTOR_ADDRESS
	34	#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
	35	#endif
	36
	37	#ifndef CONFIG_SYS_MONITOR_BASE
	38	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
	39	#endif
	40
49f5befa XX	41	#define CONFIG_MP
49f5befa XX	42
b38eaec5 RD	43	#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
b38eaec5 RD	44	#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
49f5befa XX	45	#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
	46	#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
	47	#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
	48	#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
	49
49f5befa XX	50	#define CONFIG_TSEC_ENET /* tsec ethernet support */
	51	#define CONFIG_ENV_OVERWRITE
	52
	53	#define CONFIG_CMD_SATA
	54	#define CONFIG_SATA_SIL3114
	55	#define CONFIG_SYS_SATA_MAX_DEVICE 2
	56	#define CONFIG_LIBATA
	57	#define CONFIG_LBA48
	58
	59	#ifndef __ASSEMBLY__
	60	extern unsigned long get_board_sys_clk(unsigned long dummy);
	61	#endif
	62	#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /sysclk for TWR-P1025 /
	63
	64	#define CONFIG_DDR_CLK_FREQ 66666666
	65
	66	#define CONFIG_HWCONFIG
	67	/*
	68	* These can be toggled for performance analysis, otherwise use default.
	69	*/
	70	#define CONFIG_L2_CACHE
	71	#define CONFIG_BTB
	72
49f5befa XX	73	#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
	74	#define CONFIG_SYS_MEMTEST_END 0x1fffffff
	75	#define CONFIG_PANIC_HANG /* do not reset board on panic */
	76
	77	#define CONFIG_SYS_CCSRBAR 0xffe00000
	78	#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
	79
	80	/* DDR Setup */
49f5befa XX	81
	82	#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
	83	#define CONFIG_CHIP_SELECTS_PER_CTRL 1
	84
	85	#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
	86	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
	87	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	88
49f5befa XX	89	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	90
	91	/* Default settings for DDR3 */
	92	#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
	93	#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
	94	#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
	95	#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
	96	#define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
	97	#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
	98
	99	#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
	100	#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
	101	#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
	102	#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
	103
	104	#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
	105	#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655a608
	106	#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
	107	#define CONFIG_SYS_DDR_RCW_1 0x00000000
	108	#define CONFIG_SYS_DDR_RCW_2 0x00000000
	109	#define CONFIG_SYS_DDR_CONTROL 0xc70c0000 /* Type = DDR3 */
	110	#define CONFIG_SYS_DDR_CONTROL_2 0x04401050
	111	#define CONFIG_SYS_DDR_TIMING_4 0x00220001
	112	#define CONFIG_SYS_DDR_TIMING_5 0x03402400
	113
	114	#define CONFIG_SYS_DDR_TIMING_3 0x00020000
	115	#define CONFIG_SYS_DDR_TIMING_0 0x00220004
	116	#define CONFIG_SYS_DDR_TIMING_1 0x5c5b6544
	117	#define CONFIG_SYS_DDR_TIMING_2 0x0fa880de
	118	#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
	119	#define CONFIG_SYS_DDR_MODE_1 0x80461320
	120	#define CONFIG_SYS_DDR_MODE_2 0x00008000
	121	#define CONFIG_SYS_DDR_INTERVAL 0x09480000
	122
	123	/*
	124	* Memory map
	125	*
	126	* 0x0000_0000 0x1fff_ffff DDR Up to 512MB cacheable
	127	* 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
	128	* 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
	129	*
	130	* Localbus
	131	* 0xe000_0000 0xe002_0000 SSD1289 128K non-cacheable
	132	* 0xec00_0000 0xefff_ffff FLASH Up to 64M non-cacheable
	133	*
	134	* 0xff90_0000 0xff97_ffff L2 SRAM Up to 512K cacheable
	135	* 0xffd0_0000 0xffd0_3fff init ram 16K Cacheable
	136	* 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
	137	*/
	138
	139	/*
	140	* Local Bus Definitions
	141	*/
	142	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
	143	#define CONFIG_SYS_FLASH_BASE 0xec000000
	144
	145	#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
	146
	147	#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \
	148	\| BR_PS_16 \| BR_V)
	149
	150	#define CONFIG_FLASH_OR_PRELIM 0xfc0000b1
	151
	152	#define CONFIG_SYS_SSD_BASE 0xe0000000
153	#define CONFIG_SYS_SSD_BASE_PHYS CONFIG_SYS_SSD_BASE
154	#define CONFIG_SSD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_SSD_BASE_PHYS) \| \
155	BR_PS_16 \| BR_V)
156	#define CONFIG_SSD_OR_PRELIM (OR_AM_64KB \| OR_GPCM_CSNT \| OR_GPCM_XACS \| \
157	OR_GPCM_ACS_DIV2 \| OR_GPCM_SCY \| \
158	OR_GPCM_TRLX \| OR_GPCM_EHTR \| OR_GPCM_EAD)
159
160	#define CONFIG_SYS_BR2_PRELIM CONFIG_SSD_BR_PRELIM
161	#define CONFIG_SYS_OR2_PRELIM CONFIG_SSD_OR_PRELIM
162
163	#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
164	#define CONFIG_SYS_FLASH_QUIET_TEST
165	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
166
167	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
168
169	#undef CONFIG_SYS_FLASH_CHECKSUM
170	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
171	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
172
173	#define CONFIG_FLASH_CFI_DRIVER
174	#define CONFIG_SYS_FLASH_CFI
175	#define CONFIG_SYS_FLASH_EMPTY_INFO
176	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
177
178	#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
179
180	#define CONFIG_SYS_INIT_RAM_LOCK
181	#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
182	/* Initial L1 address */
183	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
184	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
185	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
186	/* Size of used area in RAM */
187	#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
188
189	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
190	GENERATED_GBL_DATA_SIZE)
191	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
192
9307cbab	193	#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
49f5befa XX	194	#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
	195
	196	#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
	197	#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
	198
	199	/* Serial Port
	200	* open - index 2
	201	* shorted - index 1
	202	*/
	203	#define CONFIG_CONS_INDEX 1
	204	#undef CONFIG_SERIAL_SOFTWARE_FIFO
49f5befa XX	205	#define CONFIG_SYS_NS16550_SERIAL
	206	#define CONFIG_SYS_NS16550_REG_SIZE 1
	207	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
	208
	209	#define CONFIG_SYS_BAUDRATE_TABLE \
	210	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
	211
	212	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
	213	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
	214
49f5befa XX	215	/* I2C */
	216	#define CONFIG_SYS_I2C
	217	#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
	218	#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C spd and slave address */
	219	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	220	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	221	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
	222
	223	/*
	224	* I2C2 EEPROM
	225	*/
	226	#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C spd and slave address */
	227	#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
	228	#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
	229
	230	#define CONFIG_SYS_I2C_PCA9555_ADDR 0x23
	231
	232	/* enable read and write access to EEPROM */
49f5befa XX	233	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	234	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	235	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
	236
	237	/*
	238	* eSPI - Enhanced SPI
	239	*/
	240	#define CONFIG_HARD_SPI
49f5befa XX	241
	242	#if defined(CONFIG_PCI)
	243	/*
	244	* General PCI
	245	* Memory space is mapped 1-1, but I/O space must start from 0.
	246	*/
	247
	248	/* controller 2, direct to uli, tgtid 2, Base address 9000 */
	249	#define CONFIG_SYS_PCIE2_NAME "TWR-ELEV PCIe SLOT"
	250	#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
	251	#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
	252	#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
	253	#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
	254	#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
	255	#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
	256	#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
	257	#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
	258
	259	/* controller 1, tgtid 1, Base address a000 */
	260	#define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
	261	#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
	262	#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
	263	#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
	264	#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
	265	#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
	266	#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
	267	#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
	268	#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
	269
49f5befa	270	#define CONFIG_CMD_PCI
49f5befa XX	271
49f5befa XX	272	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
49f5befa XX	273	#endif /* CONFIG_PCI */
	274
	275	#if defined(CONFIG_TSEC_ENET)
	276
49f5befa XX	277	#define CONFIG_MII /* MII PHY management */
	278	#define CONFIG_TSEC1
	279	#define CONFIG_TSEC1_NAME "eTSEC1"
	280	#undef CONFIG_TSEC2
	281	#undef CONFIG_TSEC2_NAME
	282	#define CONFIG_TSEC3
	283	#define CONFIG_TSEC3_NAME "eTSEC3"
	284
	285	#define TSEC1_PHY_ADDR 2
	286	#define TSEC2_PHY_ADDR 0
	287	#define TSEC3_PHY_ADDR 1
	288
	289	#define TSEC1_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	290	#define TSEC2_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	291	#define TSEC3_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	292
	293	#define TSEC1_PHYIDX 0
	294	#define TSEC2_PHYIDX 0
	295	#define TSEC3_PHYIDX 0
	296
	297	#define CONFIG_ETHPRIME "eTSEC1"
	298
	299	#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
	300
	301	#define CONFIG_HAS_ETH0
	302	#define CONFIG_HAS_ETH1
	303	#undef CONFIG_HAS_ETH2
	304	#endif /* CONFIG_TSEC_ENET */
	305
	306	#ifdef CONFIG_QE
	307	/* QE microcode/firmware address */
	308	#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
dcf1d774	309	#define CONFIG_SYS_QE_FW_ADDR 0xefec0000
49f5befa XX	310	#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
	311	#endif /* CONFIG_QE */
	312
	313	#ifdef CONFIG_TWR_P1025
	314	/*
	315	* QE UEC ethernet configuration
	316	*/
	317	#define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
	318
	319	#undef CONFIG_UEC_ETH
	320	#define CONFIG_PHY_MODE_NEED_CHANGE
	321
	322	#define CONFIG_UEC_ETH1 /* ETH1 */
	323	#define CONFIG_HAS_ETH0
	324
	325	#ifdef CONFIG_UEC_ETH1
	326	#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
	327	#define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */
	328	#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */
	329	#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
	330	#define CONFIG_SYS_UEC1_PHY_ADDR 0x18 /* 0x18 for MII */
	331	#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
	332	#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
	333	#endif /* CONFIG_UEC_ETH1 */
	334
	335	#define CONFIG_UEC_ETH5 /* ETH5 */
	336	#define CONFIG_HAS_ETH1
	337
	338	#ifdef CONFIG_UEC_ETH5
	339	#define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */
	340	#define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
	341	#define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */
	342	#define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
	343	#define CONFIG_SYS_UEC5_PHY_ADDR 0x19 /* 0x19 for RMII */
	344	#define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
	345	#define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
	346	#endif /* CONFIG_UEC_ETH5 */
	347	#endif /* CONFIG_TWR-P1025 */
	348
94b383e7 YL	349	/*
	350	* Dynamic MTD Partition support with mtdparts
	351	*/
	352	#define CONFIG_MTD_DEVICE
	353	#define CONFIG_MTD_PARTITIONS
	354	#define CONFIG_CMD_MTDPARTS
	355	#define CONFIG_FLASH_CFI_MTD
	356	#define MTDIDS_DEFAULT "nor0=ec000000.nor"
	357	#define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:256k(vsc7385-firmware)," \
	358	"256k(dtb),5632k(kernel),57856k(fs)," \
	359	"256k(qe-ucode-firmware),1280k(u-boot)"
	360
49f5befa XX	361	/*
	362	* Environment
	363	*/
	364	#ifdef CONFIG_SYS_RAMBOOT
	365	#ifdef CONFIG_RAMBOOT_SDCARD
	366	#define CONFIG_ENV_IS_IN_MMC
	367	#define CONFIG_ENV_SIZE 0x2000
	368	#define CONFIG_SYS_MMC_ENV_DEV 0
	369	#else
	370	#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
	371	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
	372	#define CONFIG_ENV_SIZE 0x2000
	373	#endif
	374	#else
	375	#define CONFIG_ENV_IS_IN_FLASH
49f5befa	376	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
49f5befa XX	377	#define CONFIG_ENV_SIZE 0x2000
	378	#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
	379	#endif
	380
	381	#define CONFIG_LOADS_ECHO /* echo on for serial download */
	382	#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
	383
	384	/*
	385	* Command line configuration.
	386	*/
49f5befa XX	387	#define CONFIG_CMD_REGINFO
	388
	389	/*
	390	* USB
	391	*/
	392	#define CONFIG_HAS_FSL_DR_USB
	393
	394	#if defined(CONFIG_HAS_FSL_DR_USB)
8850c5d5	395	#ifdef CONFIG_USB_EHCI_HCD
49f5befa XX	396	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
49f5befa XX	397	#define CONFIG_USB_EHCI_FSL
49f5befa XX	398	#endif
	399	#endif
	400
49f5befa XX	401	#ifdef CONFIG_MMC
	402	#define CONFIG_FSL_ESDHC
	403	#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
49f5befa XX	404	#endif
49f5befa XX	405
49f5befa XX	406	#undef CONFIG_WATCHDOG /* watchdog disabled */
	407
	408	/*
	409	* Miscellaneous configurable options
	410	*/
	411	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	412	#define CONFIG_CMDLINE_EDITING /* Command-line editing */
	413	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
49f5befa XX	414	#if defined(CONFIG_CMD_KGDB)
	415	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
	416	#else
	417	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	418	#endif
	419	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	420	/* Print Buffer Size */
	421	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	422	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
49f5befa XX	423
	424	/*
	425	* For booting Linux, the board info and command line data
	426	* have to be in the first 64 MB of memory, since this is
	427	* the maximum mapped by the Linux kernel during initialization.
	428	*/
	429	#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
	430	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
	431
	432	/*
	433	* Environment Configuration
	434	*/
	435	#define CONFIG_HOSTNAME unknown
	436	#define CONFIG_ROOTPATH "/opt/nfsroot"
	437	#define CONFIG_BOOTFILE "uImage"
	438	#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
	439
	440	/* default location for tftp and bootm */
	441	#define CONFIG_LOADADDR 1000000
	442
49f5befa XX	443	#define CONFIG_BOOTARGS /* the boot command will set bootargs */
49f5befa XX	444
49f5befa XX	445	#define CONFIG_EXTRA_ENV_SETTINGS \
	446	"netdev=eth0\0" \
	447	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
	448	"loadaddr=1000000\0" \
	449	"bootfile=uImage\0" \
	450	"dtbfile=twr-p1025twr.dtb\0" \
	451	"ramdiskfile=rootfs.ext2.gz.uboot\0" \
	452	"qefirmwarefile=fsl_qe_ucode_1021_10_A.bin\0" \
	453	"tftpflash=tftpboot $loadaddr $uboot; " \
	454	"protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
	455	"erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
	456	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
	457	"protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
	458	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
	459	"kernelflash=tftpboot $loadaddr $bootfile; " \
	460	"protect off 0xefa80000 +$filesize; " \
	461	"erase 0xefa80000 +$filesize; " \
	462	"cp.b $loadaddr 0xefa80000 $filesize; " \
	463	"protect on 0xefa80000 +$filesize; " \
	464	"cmp.b $loadaddr 0xefa80000 $filesize\0" \
	465	"dtbflash=tftpboot $loadaddr $dtbfile; " \
	466	"protect off 0xefe80000 +$filesize; " \
	467	"erase 0xefe80000 +$filesize; " \
	468	"cp.b $loadaddr 0xefe80000 $filesize; " \
	469	"protect on 0xefe80000 +$filesize; " \
	470	"cmp.b $loadaddr 0xefe80000 $filesize\0" \
	471	"ramdiskflash=tftpboot $loadaddr $ramdiskfile; " \
	472	"protect off 0xeeb80000 +$filesize; " \
	473	"erase 0xeeb80000 +$filesize; " \
	474	"cp.b $loadaddr 0xeeb80000 $filesize; " \
	475	"protect on 0xeeb80000 +$filesize; " \
	476	"cmp.b $loadaddr 0xeeb80000 $filesize\0" \
	477	"qefirmwareflash=tftpboot $loadaddr $qefirmwarefile; " \
	478	"protect off 0xefec0000 +$filesize; " \
	479	"erase 0xefec0000 +$filesize; " \
	480	"cp.b $loadaddr 0xefec0000 $filesize; " \
	481	"protect on 0xefec0000 +$filesize; " \
	482	"cmp.b $loadaddr 0xefec0000 $filesize\0" \
	483	"consoledev=ttyS0\0" \
	484	"ramdiskaddr=2000000\0" \
	485	"ramdiskfile=rootfs.ext2.gz.uboot\0" \
b24a4f62	486	"fdtaddr=1e00000\0" \
49f5befa XX	487	"bdev=sda1\0" \
	488	"norbootaddr=ef080000\0" \
	489	"norfdtaddr=ef040000\0" \
	490	"ramdisk_size=120000\0" \
	491	"usbboot=setenv bootargs root=/dev/sda1 rw rootdelay=5 " \
	492	"console=$consoledev,$baudrate $othbootargs ; bootm 0xefa80000 - 0xefe80000"
	493
	494	#define CONFIG_NFSBOOTCOMMAND \
	495	"setenv bootargs root=/dev/nfs rw " \
	496	"nfsroot=$serverip:$rootpath " \
	497	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
	498	"console=$consoledev,$baudrate $othbootargs;" \
	499	"tftp $loadaddr $bootfile&&" \
	500	"tftp $fdtaddr $fdtfile&&" \
	501	"bootm $loadaddr - $fdtaddr"
	502
	503	#define CONFIG_HDBOOT \
	504	"setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
	505	"console=$consoledev,$baudrate $othbootargs;" \
	506	"usb start;" \
	507	"ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
	508	"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
	509	"bootm $loadaddr - $fdtaddr"
	510
	511	#define CONFIG_USB_FAT_BOOT \
	512	"setenv bootargs root=/dev/ram rw " \
	513	"console=$consoledev,$baudrate $othbootargs " \
	514	"ramdisk_size=$ramdisk_size;" \
	515	"usb start;" \
	516	"fatload usb 0:2 $loadaddr $bootfile;" \
	517	"fatload usb 0:2 $fdtaddr $fdtfile;" \
	518	"fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
	519	"bootm $loadaddr $ramdiskaddr $fdtaddr"
	520
	521	#define CONFIG_USB_EXT2_BOOT \
	522	"setenv bootargs root=/dev/ram rw " \
	523	"console=$consoledev,$baudrate $othbootargs " \
	524	"ramdisk_size=$ramdisk_size;" \
	525	"usb start;" \
	526	"ext2load usb 0:4 $loadaddr $bootfile;" \
	527	"ext2load usb 0:4 $fdtaddr $fdtfile;" \
	528	"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
	529	"bootm $loadaddr $ramdiskaddr $fdtaddr"
	530
	531	#define CONFIG_NORBOOT \
	532	"setenv bootargs root=/dev/mtdblock3 rw " \
	533	"console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
	534	"bootm $norbootaddr - $norfdtaddr"
	535
	536	#define CONFIG_RAMBOOTCOMMAND_TFTP \
	537	"setenv bootargs root=/dev/ram rw " \
	538	"console=$consoledev,$baudrate $othbootargs " \
	539	"ramdisk_size=$ramdisk_size;" \
	540	"tftp $ramdiskaddr $ramdiskfile;" \
	541	"tftp $loadaddr $bootfile;" \
	542	"tftp $fdtaddr $fdtfile;" \
	543	"bootm $loadaddr $ramdiskaddr $fdtaddr"
	544
	545	#define CONFIG_RAMBOOTCOMMAND \
	546	"setenv bootargs root=/dev/ram rw " \
	547	"console=$consoledev,$baudrate $othbootargs " \
	548	"ramdisk_size=$ramdisk_size;" \
	549	"bootm 0xefa80000 0xeeb80000 0xefe80000"
	550
551	#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
552
553	#endif /* __CONFIG_H */