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5568e613 | 1 | /* |
62534beb | 2 | * (C) Copyright 2005-2006 |
5568e613 SR |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
4 | * | |
5 | * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> | |
6 | * | |
7 | * See file CREDITS for list of people who contributed to this | |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
25 | ||
26 | /************************************************************************ | |
27 | * board/config_p3p440.h - configuration for Prodrive P3P440 | |
28 | ***********************************************************************/ | |
29 | ||
30 | #ifndef __CONFIG_H | |
31 | #define __CONFIG_H | |
32 | ||
33 | /*----------------------------------------------------------------------- | |
34 | * High Level Configuration Options | |
35 | *----------------------------------------------------------------------*/ | |
36 | #define CONFIG_P3P440 1 /* Board is P3P440 */ | |
37 | #define CONFIG_440GP 1 /* Specifc GP support */ | |
efa35cf1 | 38 | #define CONFIG_440 1 /* ... PPC440 family */ |
5568e613 SR |
39 | #define CONFIG_4xx 1 /* ... PPC4xx family */ |
40 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ | |
41 | #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ | |
2ae18241 WD |
42 | |
43 | #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 | |
44 | ||
5568e613 SR |
45 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ |
46 | ||
47 | /*----------------------------------------------------------------------- | |
48 | * Base addresses -- Note these are effective addresses where the | |
49 | * actual resources get mapped (not physical addresses) | |
50 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
51 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ |
52 | #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH */ | |
53 | #define CONFIG_SYS_MONITOR_BASE 0xfffc0000 /* start of monitor */ | |
54 | #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ | |
6d0f6bcf JCPV |
55 | #define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */ |
56 | #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ | |
5568e613 | 57 | |
6d0f6bcf | 58 | #define CONFIG_SYS_USB_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000000) |
5568e613 SR |
59 | |
60 | /*----------------------------------------------------------------------- | |
61 | * Initial RAM & stack pointer (placed in internal SRAM) | |
62 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 63 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */ |
553f0982 | 64 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ |
5568e613 | 65 | |
25ddd1fb | 66 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 67 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
5568e613 | 68 | |
6d0f6bcf JCPV |
69 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ |
70 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ | |
5568e613 SR |
71 | |
72 | /*----------------------------------------------------------------------- | |
73 | * DDR SDRAM | |
74 | *----------------------------------------------------------------------*/ | |
75 | #define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0*/ | |
62534beb | 76 | #define CONFIG_SDRAM_ECC /* enable ECC support */ |
6d0f6bcf | 77 | #define CONFIG_SYS_SDRAM_TABLE { \ |
62534beb SR |
78 | {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \ |
79 | {(64 << 20), 12, 0x00082001}} /* 64MB mode 2, 12x9(4) */ | |
5568e613 SR |
80 | |
81 | /*----------------------------------------------------------------------- | |
82 | * Serial Port | |
83 | *----------------------------------------------------------------------*/ | |
550650dd SR |
84 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
85 | #define CONFIG_SYS_NS16550 | |
86 | #define CONFIG_SYS_NS16550_SERIAL | |
87 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
88 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
89 | ||
6d0f6bcf | 90 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK |
5568e613 SR |
91 | #define CONFIG_BAUDRATE 115200 |
92 | ||
6d0f6bcf | 93 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
5568e613 SR |
94 | { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ |
95 | 57600, 115200, 230400, 460800, 921600 } | |
96 | ||
97 | /*----------------------------------------------------------------------- | |
98 | * I2C | |
99 | *----------------------------------------------------------------------*/ | |
100 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
d0b0dcaa | 101 | #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ |
6d0f6bcf JCPV |
102 | #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ |
103 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
104 | #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ | |
5568e613 SR |
105 | |
106 | /*----------------------------------------------------------------------- | |
107 | * I2C RTC | |
108 | *----------------------------------------------------------------------*/ | |
109 | #define CONFIG_RTC_MAX6900 1 /* MAX6900 RTC */ | |
110 | ||
111 | /*----------------------------------------------------------------------- | |
112 | * I2C EEPROM (PCF8594C) for environment | |
113 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
114 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 /* EEPROM PCF8594C */ |
115 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ | |
5568e613 | 116 | /* mask of address bits that overflow into the "EEPROM chip address" */ |
6d0f6bcf JCPV |
117 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
118 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* The Philips PCF8594C has */ | |
5568e613 SR |
119 | /* 8 byte page write mode using */ |
120 | /* last 3 bits of the address */ | |
6d0f6bcf | 121 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 40 /* and takes up to 40 msec */ |
5568e613 SR |
122 | |
123 | /*----------------------------------------------------------------------- | |
124 | * Default configuration (environment varibles...) | |
125 | *----------------------------------------------------------------------*/ | |
126 | #define CONFIG_PREBOOT "echo;" \ | |
32bf3d14 | 127 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
5568e613 SR |
128 | "echo" |
129 | ||
130 | #undef CONFIG_BOOTARGS | |
131 | ||
132 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
133 | "netdev=eth0\0" \ | |
134 | "hostname=p3p440\0" \ | |
135 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
136 | "nfsroot=${serverip}:${rootpath}\0" \ | |
137 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
138 | "addip=setenv bootargs ${bootargs} " \ | |
139 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
140 | ":${hostname}:${netdev}:off panic=1\0" \ | |
141 | "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ | |
142 | "flash_nfs=run nfsargs addip addtty;" \ | |
143 | "bootm ${kernel_addr}\0" \ | |
144 | "flash_self=run ramargs addip addtty;" \ | |
145 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
146 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ | |
147 | "bootm\0" \ | |
148 | "rootpath=/opt/eldk/ppc_4xx\0" \ | |
149 | "bootfile=/tftpboot/p3p440/uImage\0" \ | |
150 | "kernel_addr=ff800000\0" \ | |
151 | "ramdisk_addr=ff810000\0" \ | |
152 | "load=tftp 100000 /tftpboot/p3p440/u-boot.bin\0" \ | |
153 | "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ | |
154 | "cp.b 100000 fffc0000 40000;" \ | |
155 | "setenv filesize;saveenv\0" \ | |
d8ab58b2 | 156 | "upd=run load update\0" \ |
2662b40c | 157 | "unlock=yes\0" \ |
5568e613 SR |
158 | "" |
159 | #define CONFIG_BOOTCOMMAND "run net_nfs" | |
160 | ||
161 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
162 | ||
163 | #define CONFIG_BAUDRATE 115200 | |
164 | ||
165 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 166 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
5568e613 | 167 | |
96e21f86 | 168 | #define CONFIG_PPC4xx_EMAC |
5568e613 SR |
169 | #define CONFIG_MII 1 /* MII PHY management */ |
170 | #define CONFIG_PHY_ADDR 0x1c /* PHY address */ | |
171 | #define CONFIG_HAS_ETH1 | |
172 | #define CONFIG_PHY1_ADDR 0x1d /* EMAC1 PHY address */ | |
6d0f6bcf | 173 | #define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ |
5568e613 SR |
174 | |
175 | #define CONFIG_NETCONSOLE /* include NetConsole support */ | |
176 | ||
26a34560 | 177 | |
079a136c JL |
178 | /* |
179 | * BOOTP options | |
180 | */ | |
181 | #define CONFIG_BOOTP_BOOTFILESIZE | |
182 | #define CONFIG_BOOTP_BOOTPATH | |
183 | #define CONFIG_BOOTP_GATEWAY | |
184 | #define CONFIG_BOOTP_HOSTNAME | |
185 | ||
186 | ||
26a34560 JL |
187 | /* |
188 | * Command line configuration. | |
189 | */ | |
190 | #include <config_cmd_default.h> | |
191 | ||
192 | #define CONFIG_CMD_ASKENV | |
193 | #define CONFIG_CMD_DATE | |
194 | #define CONFIG_CMD_DHCP | |
195 | #define CONFIG_CMD_DIAG | |
196 | #define CONFIG_CMD_ELF | |
197 | #define CONFIG_CMD_I2C | |
198 | #define CONFIG_CMD_IRQ | |
199 | #define CONFIG_CMD_MII | |
200 | #define CONFIG_CMD_NET | |
201 | #define CONFIG_CMD_NFS | |
202 | #define CONFIG_CMD_PCI | |
203 | #define CONFIG_CMD_PING | |
204 | #define CONFIG_CMD_REGINFO | |
205 | #define CONFIG_CMD_EEPROM | |
206 | #define CONFIG_CMD_SNTP | |
207 | ||
5568e613 SR |
208 | |
209 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
210 | ||
211 | /*----------------------------------------------------------------------- | |
212 | * Miscellaneous configurable options | |
213 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
214 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
215 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
26a34560 | 216 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 217 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
5568e613 | 218 | #else |
6d0f6bcf | 219 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
5568e613 | 220 | #endif |
6d0f6bcf JCPV |
221 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
222 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
223 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
5568e613 | 224 | |
6d0f6bcf JCPV |
225 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
226 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
5568e613 | 227 | |
6d0f6bcf JCPV |
228 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
229 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
5568e613 | 230 | |
6d0f6bcf | 231 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
5568e613 SR |
232 | |
233 | #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ | |
234 | #define CONFIG_LOOPW 1 /* enable loopw command */ | |
235 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ | |
236 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ | |
237 | ||
238 | /*----------------------------------------------------------------------- | |
239 | * PCI stuff | |
240 | *----------------------------------------------------------------------*/ | |
241 | /* General PCI */ | |
242 | #define CONFIG_PCI /* include pci support */ | |
842033e6 | 243 | #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ |
5568e613 SR |
244 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
245 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
6d0f6bcf | 246 | #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */ |
5568e613 SR |
247 | |
248 | /* Board-specific PCI */ | |
6d0f6bcf | 249 | #define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */ |
5568e613 SR |
250 | |
251 | #define CONFIG_DISABLE_PISE_TEST /* disable PISE test (PCIX only)*/ | |
252 | ||
6d0f6bcf JCPV |
253 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ |
254 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ | |
5568e613 SR |
255 | |
256 | /*----------------------------------------------------------------------- | |
257 | * External Bus Controller (EBC) Setup | |
258 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
259 | #define CONFIG_SYS_FLASH0 0xFF800000 |
260 | #define CONFIG_SYS_FLASH1 0xFF000000 | |
261 | #define CONFIG_SYS_FLASH2 0xFE800000 | |
262 | #define CONFIG_SYS_FLASH3 0xFE000000 | |
263 | #define CONFIG_SYS_USB 0xF0000000 | |
5568e613 SR |
264 | |
265 | /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ | |
6d0f6bcf JCPV |
266 | #define CONFIG_SYS_EBC_PB0AP 0x03050200 |
267 | #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH0 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */ | |
5568e613 SR |
268 | |
269 | /* Memory Bank 1 (Flash Bank 1, NOR-FLASH) initialization */ | |
6d0f6bcf JCPV |
270 | #define CONFIG_SYS_EBC_PB1AP 0x03050200 |
271 | #define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_FLASH1 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */ | |
5568e613 SR |
272 | |
273 | /* Memory Bank 2 (Flash Bank 2, NOR-FLASH) initialization */ | |
6d0f6bcf JCPV |
274 | #define CONFIG_SYS_EBC_PB2AP 0x03050200 |
275 | #define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FLASH2 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */ | |
5568e613 SR |
276 | |
277 | /* Memory Bank 3 (Flash Bank 3, NOR-FLASH) initialization */ | |
6d0f6bcf JCPV |
278 | #define CONFIG_SYS_EBC_PB3AP 0x03050200 |
279 | #define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FLASH3 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */ | |
5568e613 SR |
280 | |
281 | /* Memory Bank 7 (USB controller) initialization */ | |
6d0f6bcf JCPV |
282 | #define CONFIG_SYS_EBC_PB7AP 0x02015000 |
283 | #define CONFIG_SYS_EBC_PB7CR (CONFIG_SYS_USB | 0xFE000) /* BAS=0xF00,BS=128MB,BU=R/W,BW=16bit*/ | |
5568e613 SR |
284 | |
285 | /*----------------------------------------------------------------------- | |
286 | * FLASH related | |
287 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 288 | #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ |
00b1883a | 289 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
5568e613 | 290 | |
6d0f6bcf | 291 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH3, CONFIG_SYS_FLASH2, CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 } |
5568e613 | 292 | |
6d0f6bcf JCPV |
293 | #define CONFIG_SYS_MAX_FLASH_BANKS 4 /* max number of memory banks */ |
294 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ | |
5568e613 | 295 | |
6d0f6bcf JCPV |
296 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
297 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
5568e613 | 298 | |
6d0f6bcf JCPV |
299 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
300 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */ | |
62534beb | 301 | |
6d0f6bcf JCPV |
302 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
303 | #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ | |
5568e613 | 304 | |
5a1aceb0 | 305 | #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
5568e613 | 306 | |
0e8d1586 | 307 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ |
6d0f6bcf | 308 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) |
0e8d1586 | 309 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ |
5568e613 SR |
310 | |
311 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
312 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) |
313 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
5568e613 SR |
314 | |
315 | /* | |
316 | * For booting Linux, the board info and command line data | |
317 | * have to be in the first 8 MB of memory, since this is | |
318 | * the maximum mapped by the Linux kernel during initialization. | |
319 | */ | |
6d0f6bcf | 320 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
5568e613 | 321 | |
26a34560 | 322 | #if defined(CONFIG_CMD_KGDB) |
5568e613 SR |
323 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
324 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
325 | #endif | |
326 | #endif /* __CONFIG_H */ |