[people/ms/u-boot.git] / include / configs / p3p440.h

/*
 * (C) Copyright 2005-2006
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/************************************************************************
 * board/config_p3p440.h - configuration for Prodrive P3P440
 ***********************************************************************/

#ifndef __CONFIG_H
#define __CONFIG_H

/*-----------------------------------------------------------------------
 * High Level Configuration Options
 *----------------------------------------------------------------------*/
#define CONFIG_P3P440		1	    /* Board is P3P440		*/
#define CONFIG_440GP		1	    /* Specifc GP support	*/
#define CONFIG_440		1	    /* ... PPC440 family	*/
#define CONFIG_4xx		1	    /* ... PPC4xx family	*/
#define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_early_init_f	*/
#define CONFIG_MISC_INIT_R	1	    /* Call misc_init_r		*/

#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000

#define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/

/*-----------------------------------------------------------------------
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_SDRAM_BASE	    0x00000000	    /* _must_ be 0		*/
#define CONFIG_SYS_FLASH_BASE	    0xff800000	    /* start of FLASH		*/
#define CONFIG_SYS_MONITOR_BASE    0xfffc0000	    /* start of monitor		*/
#define CONFIG_SYS_PCI_MEMBASE	    0x80000000	    /* mapped pci memory	*/
#define CONFIG_SYS_ISRAM_BASE	    0xc0000000	    /* internal SRAM		*/
#define CONFIG_SYS_PCI_BASE	    0xd0000000	    /* internal PCI regs	*/

#define CONFIG_SYS_USB_BASE	    (CONFIG_SYS_PERIPHERAL_BASE + 0x00000000)

/*-----------------------------------------------------------------------
 * Initial RAM & stack pointer (placed in internal SRAM)
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_ISRAM_BASE  /* Initial RAM address	*/
#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	    /* Size of used area in RAM	*/

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon*/
#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc*/

/*-----------------------------------------------------------------------
 * DDR SDRAM
 *----------------------------------------------------------------------*/
#define CONFIG_SDRAM_BANK0	1	/* init onboard DDR SDRAM bank 0*/
#define CONFIG_SDRAM_ECC		/* enable ECC support		*/
#define CONFIG_SYS_SDRAM_TABLE	{ \
		{(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \
		{(64 << 20),  12, 0x00082001}} /* 64MB mode 2, 12x9(4)	*/

/*-----------------------------------------------------------------------
 * Serial Port
 *----------------------------------------------------------------------*/
#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_serial_clock()

#undef CONFIG_SYS_EXT_SERIAL_CLOCK
#define CONFIG_BAUDRATE		115200

#define CONFIG_SYS_BAUDRATE_TABLE						\
	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,		\
			57600, 115200, 230400, 460800, 921600 }

/*-----------------------------------------------------------------------
 * I2C
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_PPC4XX
#define CONFIG_SYS_I2C_PPC4XX_CH0
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		100000
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
#define CONFIG_SYS_I2C_NOPROBES	{ {0, 0x69} }	/* Don't probe these addrs */

/*-----------------------------------------------------------------------
 * I2C RTC
 *----------------------------------------------------------------------*/
#define CONFIG_RTC_MAX6900	1		/* MAX6900 RTC		*/

/*-----------------------------------------------------------------------
 * I2C EEPROM (PCF8594C) for environment
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x54	/* EEPROM PCF8594C		*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
/* mask of address bits that overflow into the "EEPROM chip address"	*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3	/* The Philips PCF8594C has	*/
					/* 8 byte page write mode using */
					/* last 3 bits of the address	*/
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	40   /* and takes up to 40 msec */

/*-----------------------------------------------------------------------
 * Default configuration (environment varibles...)
 *----------------------------------------------------------------------*/
#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"hostname=p3p440\0"						\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
	"flash_nfs=run nfsargs addip addtty;"				\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip addtty;"				\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
		"bootm\0"						\
	"rootpath=/opt/eldk/ppc_4xx\0"					\
	"bootfile=/tftpboot/p3p440/uImage\0"				\
	"kernel_addr=ff800000\0"					\
	"ramdisk_addr=ff810000\0"					\
	"load=tftp 100000 /tftpboot/p3p440/u-boot.bin\0"		\
	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
		"cp.b 100000 fffc0000 40000;"			        \
		"setenv filesize;saveenv\0"				\
	"upd=run load update\0"						\
	"unlock=yes\0"							\
	""
#define CONFIG_BOOTCOMMAND	"run net_nfs"

#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/

#define CONFIG_BAUDRATE		115200

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		0x1c	/* PHY address			*/
#define CONFIG_HAS_ETH1
#define CONFIG_PHY1_ADDR	0x1d	/* EMAC1 PHY address		*/
#define CONFIG_SYS_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */

#define CONFIG_NETCONSOLE		/* include NetConsole support	*/


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_ELF
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_SNTP


#undef CONFIG_WATCHDOG			/* watchdog disabled		*/

/*-----------------------------------------------------------------------
 * Miscellaneous configurable options
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */

#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */

#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
#define CONFIG_LOOPW            1       /* enable loopw command         */
#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */

/*-----------------------------------------------------------------------
 * PCI stuff
 *----------------------------------------------------------------------*/
/* General PCI */
#define CONFIG_PCI			            /* include pci support	        */
#define	CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
#define CONFIG_PCI_PNP			        /* do pci plug-and-play         */
#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
#define CONFIG_SYS_PCI_TARGBASE    0x80000000  /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */

/* Board-specific PCI */
#define CONFIG_SYS_PCI_TARGET_INIT	            /* let board init pci target    */

#define CONFIG_DISABLE_PISE_TEST	/* disable PISE test (PCIX only)*/

#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe  /* Whatever */

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_FLASH0		0xFF800000
#define CONFIG_SYS_FLASH1		0xFF000000
#define CONFIG_SYS_FLASH2		0xFE800000
#define CONFIG_SYS_FLASH3		0xFE000000
#define CONFIG_SYS_USB			0xF0000000

/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
#define CONFIG_SYS_EBC_PB0AP		0x03050200
#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH0 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */

/* Memory Bank 1 (Flash Bank 1, NOR-FLASH) initialization			*/
#define CONFIG_SYS_EBC_PB1AP		0x03050200
#define CONFIG_SYS_EBC_PB1CR		(CONFIG_SYS_FLASH1 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */

/* Memory Bank 2 (Flash Bank 2, NOR-FLASH) initialization			*/
#define CONFIG_SYS_EBC_PB2AP		0x03050200
#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_FLASH2 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */

/* Memory Bank 3 (Flash Bank 3, NOR-FLASH) initialization			*/
#define CONFIG_SYS_EBC_PB3AP		0x03050200
#define CONFIG_SYS_EBC_PB3CR		(CONFIG_SYS_FLASH3 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */

/* Memory Bank 7 (USB controller) initialization				*/
#define CONFIG_SYS_EBC_PB7AP		0x02015000
#define CONFIG_SYS_EBC_PB7CR		(CONFIG_SYS_USB | 0xFE000) /* BAS=0xF00,BS=128MB,BU=R/W,BW=16bit*/

/*-----------------------------------------------------------------------
 * FLASH related
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_FLASH_CFI				/* The flash is CFI compatible	*/
#define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/

#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH3, CONFIG_SYS_FLASH2, CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }

#define CONFIG_SYS_MAX_FLASH_BANKS	4	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware flash protection	*/

#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/

#define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/

#define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector		*/
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif
#endif	/* __CONFIG_H */
Commit	Line	Data
5568e613	1	/*
62534beb	2	* (C) Copyright 2005-2006
5568e613 SR	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	4	*
	5	* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
	6	*
3765b3e7	7	* SPDX-License-Identifier: GPL-2.0+
5568e613 SR	8	*/
	9
	10	/************************************************************************
	11	* board/config_p3p440.h - configuration for Prodrive P3P440
	12	***********************************************************************/
	13
	14	#ifndef __CONFIG_H
	15	#define __CONFIG_H
	16
	17	/*-----------------------------------------------------------------------
	18	* High Level Configuration Options
	19	----------------------------------------------------------------------/
	20	#define CONFIG_P3P440 1 /* Board is P3P440 */
	21	#define CONFIG_440GP 1 /* Specifc GP support */
efa35cf1	22	#define CONFIG_440 1 /* ... PPC440 family */
5568e613 SR	23	#define CONFIG_4xx 1 /* ... PPC4xx family */
	24	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
	25	#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
2ae18241 WD	26
	27	#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
	28
5568e613 SR	29	#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
	30
	31	/*-----------------------------------------------------------------------
	32	* Base addresses -- Note these are effective addresses where the
	33	* actual resources get mapped (not physical addresses)
	34	----------------------------------------------------------------------/
6d0f6bcf JCPV	35	#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
	36	#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH */
	37	#define CONFIG_SYS_MONITOR_BASE 0xfffc0000 /* start of monitor */
	38	#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
6d0f6bcf JCPV	39	#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
6d0f6bcf JCPV	40	#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
5568e613	41
6d0f6bcf	42	#define CONFIG_SYS_USB_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000000)
5568e613 SR	43
	44	/*-----------------------------------------------------------------------
	45	* Initial RAM & stack pointer (placed in internal SRAM)
	46	----------------------------------------------------------------------/
6d0f6bcf	47	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
553f0982	48	#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
5568e613	49
25ddd1fb	50	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	51	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
5568e613	52
6d0f6bcf JCPV	53	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
6d0f6bcf JCPV	54	#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
5568e613 SR	55
	56	/*-----------------------------------------------------------------------
	57	* DDR SDRAM
	58	----------------------------------------------------------------------/
	59	#define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0*/
62534beb	60	#define CONFIG_SDRAM_ECC /* enable ECC support */
6d0f6bcf	61	#define CONFIG_SYS_SDRAM_TABLE { \
62534beb SR	62	{(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \
62534beb SR	63	{(64 << 20), 12, 0x00082001}} /* 64MB mode 2, 12x9(4) */
5568e613 SR	64
	65	/*-----------------------------------------------------------------------
	66	* Serial Port
	67	----------------------------------------------------------------------/
550650dd SR	68	#define CONFIG_CONS_INDEX 1 /* Use UART0 */
	69	#define CONFIG_SYS_NS16550
	70	#define CONFIG_SYS_NS16550_SERIAL
	71	#define CONFIG_SYS_NS16550_REG_SIZE 1
	72	#define CONFIG_SYS_NS16550_CLK get_serial_clock()
	73
6d0f6bcf	74	#undef CONFIG_SYS_EXT_SERIAL_CLOCK
5568e613 SR	75	#define CONFIG_BAUDRATE 115200
5568e613 SR	76
6d0f6bcf	77	#define CONFIG_SYS_BAUDRATE_TABLE \
5568e613 SR	78	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
	79	57600, 115200, 230400, 460800, 921600 }
	80
	81	/*-----------------------------------------------------------------------
	82	* I2C
	83	----------------------------------------------------------------------/
880540de DE	84	#define CONFIG_SYS_I2C
	85	#define CONFIG_SYS_I2C_PPC4XX
	86	#define CONFIG_SYS_I2C_PPC4XX_CH0
	87	#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
	88	#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
	89	#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */
5568e613 SR	90
	91	/*-----------------------------------------------------------------------
	92	* I2C RTC
	93	----------------------------------------------------------------------/
	94	#define CONFIG_RTC_MAX6900 1 /* MAX6900 RTC */
	95
	96	/*-----------------------------------------------------------------------
	97	* I2C EEPROM (PCF8594C) for environment
	98	----------------------------------------------------------------------/
6d0f6bcf JCPV	99	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 /* EEPROM PCF8594C */
6d0f6bcf JCPV	100	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
5568e613	101	/* mask of address bits that overflow into the "EEPROM chip address" */
6d0f6bcf JCPV	102	#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
6d0f6bcf JCPV	103	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* The Philips PCF8594C has */
5568e613 SR	104	/* 8 byte page write mode using */
5568e613 SR	105	/* last 3 bits of the address */
6d0f6bcf	106	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 40 /* and takes up to 40 msec */
5568e613 SR	107
	108	/*-----------------------------------------------------------------------
	109	* Default configuration (environment varibles...)
	110	----------------------------------------------------------------------/
	111	#define CONFIG_PREBOOT "echo;" \
32bf3d14	112	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
5568e613 SR	113	"echo"
	114
	115	#undef CONFIG_BOOTARGS
	116
	117	#define CONFIG_EXTRA_ENV_SETTINGS \
	118	"netdev=eth0\0" \
	119	"hostname=p3p440\0" \
	120	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	121	"nfsroot=${serverip}:${rootpath}\0" \
	122	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	123	"addip=setenv bootargs ${bootargs} " \
	124	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	125	":${hostname}:${netdev}:off panic=1\0" \
	126	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
	127	"flash_nfs=run nfsargs addip addtty;" \
	128	"bootm ${kernel_addr}\0" \
	129	"flash_self=run ramargs addip addtty;" \
	130	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
	131	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
93e14596	132	"bootm\0" \
5568e613 SR	133	"rootpath=/opt/eldk/ppc_4xx\0" \
	134	"bootfile=/tftpboot/p3p440/uImage\0" \
	135	"kernel_addr=ff800000\0" \
	136	"ramdisk_addr=ff810000\0" \
	137	"load=tftp 100000 /tftpboot/p3p440/u-boot.bin\0" \
	138	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
	139	"cp.b 100000 fffc0000 40000;" \
	140	"setenv filesize;saveenv\0" \
d8ab58b2	141	"upd=run load update\0" \
2662b40c	142	"unlock=yes\0" \
5568e613 SR	143	""
	144	#define CONFIG_BOOTCOMMAND "run net_nfs"
	145
	146	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	147
	148	#define CONFIG_BAUDRATE 115200
	149
	150	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	151	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
5568e613	152
96e21f86	153	#define CONFIG_PPC4xx_EMAC
5568e613 SR	154	#define CONFIG_MII 1 /* MII PHY management */
	155	#define CONFIG_PHY_ADDR 0x1c /* PHY address */
	156	#define CONFIG_HAS_ETH1
	157	#define CONFIG_PHY1_ADDR 0x1d /* EMAC1 PHY address */
6d0f6bcf	158	#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
5568e613 SR	159
	160	#define CONFIG_NETCONSOLE /* include NetConsole support */
	161
26a34560	162
079a136c JL	163	/*
	164	* BOOTP options
	165	*/
	166	#define CONFIG_BOOTP_BOOTFILESIZE
	167	#define CONFIG_BOOTP_BOOTPATH
	168	#define CONFIG_BOOTP_GATEWAY
	169	#define CONFIG_BOOTP_HOSTNAME
	170
	171
26a34560 JL	172	/*
	173	* Command line configuration.
	174	*/
	175	#include <config_cmd_default.h>
	176
	177	#define CONFIG_CMD_ASKENV
	178	#define CONFIG_CMD_DATE
	179	#define CONFIG_CMD_DHCP
	180	#define CONFIG_CMD_DIAG
	181	#define CONFIG_CMD_ELF
	182	#define CONFIG_CMD_I2C
	183	#define CONFIG_CMD_IRQ
	184	#define CONFIG_CMD_MII
	185	#define CONFIG_CMD_NET
	186	#define CONFIG_CMD_NFS
	187	#define CONFIG_CMD_PCI
	188	#define CONFIG_CMD_PING
	189	#define CONFIG_CMD_REGINFO
	190	#define CONFIG_CMD_EEPROM
	191	#define CONFIG_CMD_SNTP
	192
5568e613 SR	193
	194	#undef CONFIG_WATCHDOG /* watchdog disabled */
	195
	196	/*-----------------------------------------------------------------------
	197	* Miscellaneous configurable options
	198	----------------------------------------------------------------------/
6d0f6bcf JCPV	199	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	200	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
26a34560	201	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	202	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
5568e613	203	#else
6d0f6bcf	204	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
5568e613	205	#endif
6d0f6bcf JCPV	206	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	207	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	208	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
5568e613	209
6d0f6bcf JCPV	210	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	211	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
5568e613	212
6d0f6bcf JCPV	213	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
6d0f6bcf JCPV	214	#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
5568e613	215
6d0f6bcf	216	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
5568e613 SR	217
	218	#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
	219	#define CONFIG_LOOPW 1 /* enable loopw command */
	220	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
	221	#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
	222
	223	/*-----------------------------------------------------------------------
	224	* PCI stuff
	225	----------------------------------------------------------------------/
	226	/* General PCI */
	227	#define CONFIG_PCI /* include pci support */
842033e6	228	#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
5568e613 SR	229	#define CONFIG_PCI_PNP /* do pci plug-and-play */
5568e613 SR	230	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
6d0f6bcf	231	#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
5568e613 SR	232
5568e613 SR	233	/* Board-specific PCI */
6d0f6bcf	234	#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
5568e613 SR	235
	236	#define CONFIG_DISABLE_PISE_TEST /* disable PISE test (PCIX only)*/
	237
6d0f6bcf JCPV	238	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
6d0f6bcf JCPV	239	#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
5568e613 SR	240
	241	/*-----------------------------------------------------------------------
	242	* External Bus Controller (EBC) Setup
	243	----------------------------------------------------------------------/
6d0f6bcf JCPV	244	#define CONFIG_SYS_FLASH0 0xFF800000
	245	#define CONFIG_SYS_FLASH1 0xFF000000
	246	#define CONFIG_SYS_FLASH2 0xFE800000
	247	#define CONFIG_SYS_FLASH3 0xFE000000
	248	#define CONFIG_SYS_USB 0xF0000000
5568e613 SR	249
5568e613 SR	250	/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
6d0f6bcf JCPV	251	#define CONFIG_SYS_EBC_PB0AP 0x03050200
6d0f6bcf JCPV	252	#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH0 \| 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
5568e613 SR	253
5568e613 SR	254	/* Memory Bank 1 (Flash Bank 1, NOR-FLASH) initialization */
6d0f6bcf JCPV	255	#define CONFIG_SYS_EBC_PB1AP 0x03050200
6d0f6bcf JCPV	256	#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_FLASH1 \| 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
5568e613 SR	257
5568e613 SR	258	/* Memory Bank 2 (Flash Bank 2, NOR-FLASH) initialization */
6d0f6bcf JCPV	259	#define CONFIG_SYS_EBC_PB2AP 0x03050200
6d0f6bcf JCPV	260	#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FLASH2 \| 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
5568e613 SR	261
5568e613 SR	262	/* Memory Bank 3 (Flash Bank 3, NOR-FLASH) initialization */
6d0f6bcf JCPV	263	#define CONFIG_SYS_EBC_PB3AP 0x03050200
6d0f6bcf JCPV	264	#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FLASH3 \| 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
5568e613 SR	265
5568e613 SR	266	/* Memory Bank 7 (USB controller) initialization */
6d0f6bcf JCPV	267	#define CONFIG_SYS_EBC_PB7AP 0x02015000
6d0f6bcf JCPV	268	#define CONFIG_SYS_EBC_PB7CR (CONFIG_SYS_USB \| 0xFE000) /* BAS=0xF00,BS=128MB,BU=R/W,BW=16bit*/
5568e613 SR	269
	270	/*-----------------------------------------------------------------------
	271	* FLASH related
	272	----------------------------------------------------------------------/
6d0f6bcf	273	#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
00b1883a	274	#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
5568e613	275
6d0f6bcf	276	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH3, CONFIG_SYS_FLASH2, CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
5568e613	277
6d0f6bcf JCPV	278	#define CONFIG_SYS_MAX_FLASH_BANKS 4 /* max number of memory banks */
6d0f6bcf JCPV	279	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
5568e613	280
6d0f6bcf JCPV	281	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	282	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
5568e613	283
6d0f6bcf JCPV	284	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
6d0f6bcf JCPV	285	#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
62534beb	286
6d0f6bcf JCPV	287	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
6d0f6bcf JCPV	288	#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
5568e613	289
5a1aceb0	290	#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
5568e613	291
0e8d1586	292	#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
6d0f6bcf	293	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
0e8d1586	294	#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
5568e613 SR	295
5568e613 SR	296	/* Address and size of Redundant Environment Sector */
0e8d1586 JCPV	297	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
0e8d1586 JCPV	298	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
5568e613 SR	299
	300	/*
	301	* For booting Linux, the board info and command line data
	302	* have to be in the first 8 MB of memory, since this is
	303	* the maximum mapped by the Linux kernel during initialization.
	304	*/
6d0f6bcf	305	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
5568e613	306
26a34560	307	#if defined(CONFIG_CMD_KGDB)
5568e613 SR	308	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	309	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	310	#endif
	311	#endif /* __CONFIG_H */