[people/ms/u-boot.git] / include / configs / palmld.h

/*
 * Palm LifeDrive configuration file
 *
 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef	__CONFIG_H
#define	__CONFIG_H

/*
 * High Level Board Configuration Options
 */
#define	CONFIG_CPU_PXA27X		1	/* Marvell PXA270 CPU */
#define	CONFIG_PALMLD		1	/* Palm LifeDrive board */

/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_DCACHE_OFF

/*
 * Environment settings
 */
#define	CONFIG_ENV_OVERWRITE
#define	CONFIG_SYS_MALLOC_LEN		(128*1024)
#define	CONFIG_SYS_TEXT_BASE	0x0

#define	CONFIG_BOOTCOMMAND						\
	"if mmcinfo && fatload mmc 0 0xa0000000 uboot.script ; then "	\
		"source 0xa0000000; "					\
	"else "								\
		"bootm 0x0x60000; "					\
	"fi; "
#define	CONFIG_BOOTARGS			"console=tty0 console=ttyS0,9600"
#define	CONFIG_TIMESTAMP
#define	CONFIG_BOOTDELAY		2	/* Autoboot delay */
#define	CONFIG_CMDLINE_TAG
#define	CONFIG_SETUP_MEMORY_TAGS

#define	CONFIG_LZMA			/* LZMA compression support */

/*
 * Serial Console Configuration
 */
#define	CONFIG_PXA_SERIAL
#define	CONFIG_FFUART			1
#define CONFIG_CONS_INDEX		3
#define	CONFIG_BAUDRATE			9600

/*
 * Bootloader Components Configuration
 */
#include <config_cmd_default.h>

#undef	CONFIG_CMD_NET
#undef	CONFIG_CMD_NFS
#define	CONFIG_CMD_ENV
#undef	CONFIG_CMD_IMLS
#define	CONFIG_CMD_MMC
#define	CONFIG_CMD_IDE
#define	CONFIG_LCD
#define	CONFIG_PXA_LCD

/*
 * MMC Card Configuration
 */
#ifdef	CONFIG_CMD_MMC
#define	CONFIG_MMC
#define	CONFIG_GENERIC_MMC
#define	CONFIG_PXA_MMC_GENERIC
#define	CONFIG_SYS_MMC_BASE		0xF0000000
#define	CONFIG_CMD_FAT
#define	CONFIG_CMD_EXT2
#define	CONFIG_DOS_PARTITION
#endif

/*
 * LCD
 */
#ifdef CONFIG_LCD
#define	CONFIG_LQ038J7DH53
#define	CONFIG_VIDEO_LOGO
#define	CONFIG_CMD_BMP
#define	CONFIG_SPLASH_SCREEN
#define	CONFIG_SPLASH_SCREEN_ALIGN
#define	CONFIG_VIDEO_BMP_GZIP
#define	CONFIG_VIDEO_BMP_RLE8
#define	CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(2 << 20)
#endif

/*
 * KGDB
 */
#ifdef	CONFIG_CMD_KGDB
#define	CONFIG_KGDB_BAUDRATE		230400	/* kgdb serial port speed */
#endif

/*
 * HUSH Shell Configuration
 */
#define	CONFIG_SYS_HUSH_PARSER		1

#define	CONFIG_SYS_LONGHELP
#ifdef	CONFIG_SYS_HUSH_PARSER
#define	CONFIG_SYS_PROMPT		"$ "
#endif
#define	CONFIG_SYS_CBSIZE		256
#define	CONFIG_SYS_PBSIZE		\
	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define	CONFIG_SYS_MAXARGS		16
#define	CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
#define	CONFIG_SYS_DEVICE_NULLDEV	1

/*
 * Clock Configuration
 */
#define	CONFIG_SYS_CPUSPEED		0x210		/* 416MHz ; N=2,L=16 */

/*
 * DRAM Map
 */
#define	CONFIG_NR_DRAM_BANKS		1		/* 1 bank of DRAM */
#define	PHYS_SDRAM_1			0xa0000000	/* SDRAM Bank #1 */
#define	PHYS_SDRAM_1_SIZE		0x02000000	/* 32 MB */

#define	CONFIG_SYS_DRAM_BASE		0xa0000000	/* CS0 */
#define	CONFIG_SYS_DRAM_SIZE		0x02000000	/* 32 MB DRAM */

#define	CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on */
#define	CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM */

#define	CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_DRAM_BASE

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)

/*
 * NOR FLASH
 */
#ifdef	CONFIG_CMD_FLASH
#define	PHYS_FLASH_1			0x00000000	/* Flash Bank #1 */
#define	PHYS_FLASH_SIZE			0x00080000	/* 512 KB */
#define	CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1

#define	CONFIG_SYS_FLASH_CFI
#define	CONFIG_FLASH_CFI_DRIVER		1

#define	CONFIG_FLASH_CFI_LEGACY
#define	CONFIG_SYS_FLASH_LEGACY_512Kx16

#define	CONFIG_SYS_MONITOR_BASE		0
#define	CONFIG_SYS_MONITOR_LEN		0x40000

#define	CONFIG_SYS_MAX_FLASH_BANKS	1
#define	CONFIG_SYS_MAX_FLASH_SECT	256

#define	CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1

#define	CONFIG_SYS_FLASH_ERASE_TOUT	240000
#define	CONFIG_SYS_FLASH_WRITE_TOUT	240000
#define	CONFIG_SYS_FLASH_LOCK_TOUT	240000
#define	CONFIG_SYS_FLASH_UNLOCK_TOUT	240000
#define	CONFIG_SYS_FLASH_PROTECTION

#define	CONFIG_ENV_IS_IN_FLASH		1
#define	CONFIG_ENV_SECT_SIZE		0x10000
#else
#define	CONFIG_SYS_NO_FLASH
#define	CONFIG_ENV_IS_NOWHERE
#endif

#define	CONFIG_ENV_ADDR			0x40000
#define	CONFIG_ENV_SIZE			0x4000

/*
 * IDE
 */
#ifdef	CONFIG_CMD_IDE
#define	CONFIG_LBA48
#undef	CONFIG_IDE_LED
#undef	CONFIG_IDE_RESET

#define	__io

#define	CONFIG_SYS_IDE_MAXBUS		1
#define	CONFIG_SYS_IDE_MAXDEVICE	1

#define	CONFIG_SYS_ATA_BASE_ADDR	0x20000000
#define	CONFIG_SYS_ATA_IDE0_OFFSET	0x0

#define	CONFIG_SYS_ATA_DATA_OFFSET	0x10
#define	CONFIG_SYS_ATA_REG_OFFSET	0x10
#define	CONFIG_SYS_ATA_ALT_OFFSET	0x10

#define	CONFIG_SYS_ATA_STRIDE		1
#endif

/*
 * GPIO settings
 */
#define	CONFIG_SYS_GAFR0_L_VAL	0x00000000
#define	CONFIG_SYS_GAFR0_U_VAL	0xa5180012
#define	CONFIG_SYS_GAFR1_L_VAL	0x69988056
#define	CONFIG_SYS_GAFR1_U_VAL	0xaaa580aa
#define	CONFIG_SYS_GAFR2_L_VAL	0x6aaaaaaa
#define	CONFIG_SYS_GAFR2_U_VAL	0x01040001
#define	CONFIG_SYS_GAFR3_L_VAL	0x540a950c
#define	CONFIG_SYS_GAFR3_U_VAL	0x00000009
#define	CONFIG_SYS_GPCR0_VAL	0x00000000
#define	CONFIG_SYS_GPCR1_VAL	0x00000000
#define	CONFIG_SYS_GPCR2_VAL	0x00000000
#define	CONFIG_SYS_GPCR3_VAL	0x00000000
#define	CONFIG_SYS_GPDR0_VAL	0xc26b0000
#define	CONFIG_SYS_GPDR1_VAL	0xfcdfaa93
#define	CONFIG_SYS_GPDR2_VAL	0x7bbaffff
#define	CONFIG_SYS_GPDR3_VAL	0x006ff38d
#define	CONFIG_SYS_GPSR0_VAL	0x0d9e45ee
#define	CONFIG_SYS_GPSR1_VAL	0x03affdae
#define	CONFIG_SYS_GPSR2_VAL	0x07554000
#define	CONFIG_SYS_GPSR3_VAL	0x01bc0785

#define	CONFIG_SYS_PSSR_VAL	0x30

/*
 * Clock settings
 */
#define	CONFIG_SYS_CKEN		0x01ffffff
#define	CONFIG_SYS_CCCR		0x02000210

/*
 * Memory settings
 */
#define	CONFIG_SYS_MSC0_VAL	0x7ff844c8
#define	CONFIG_SYS_MSC1_VAL	0x7ff86ab4
#define	CONFIG_SYS_MSC2_VAL	0x7ff87ff8
#define	CONFIG_SYS_MDCNFG_VAL	0x0B880acd
#define	CONFIG_SYS_MDREFR_VAL	0x201fa031
#define	CONFIG_SYS_MDMRS_VAL	0x00320032
#define	CONFIG_SYS_FLYCNFG_VAL	0x00000000
#define	CONFIG_SYS_SXCNFG_VAL	0x40044004

/*
 * PCMCIA and CF Interfaces
 */
#define	CONFIG_SYS_MECR_VAL	0x00000003
#define	CONFIG_SYS_MCMEM0_VAL	0x0001c391
#define	CONFIG_SYS_MCMEM1_VAL	0x0001c391
#define	CONFIG_SYS_MCATT0_VAL	0x0001c391
#define	CONFIG_SYS_MCATT1_VAL	0x0001c391
#define	CONFIG_SYS_MCIO0_VAL	0x00014611
#define	CONFIG_SYS_MCIO1_VAL	0x0001c391

#endif	/* __CONFIG_H */
Commit	Line	Data
6375dada MV	1	/*
	2	* Palm LifeDrive configuration file
	3	*
	4	* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
6375dada MV	7	*/
	8
	9	#ifndef __CONFIG_H
	10	#define __CONFIG_H
	11
	12	/*
	13	* High Level Board Configuration Options
	14	*/
abc20aba	15	#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
6375dada MV	16	#define CONFIG_PALMLD 1 /* Palm LifeDrive board */
6375dada MV	17
89959081 SG	18	/* we will never enable dcache, because we have to setup MMU first */
	19	#define CONFIG_SYS_DCACHE_OFF
	20
6375dada MV	21	/*
	22	* Environment settings
	23	*/
	24	#define CONFIG_ENV_OVERWRITE
	25	#define CONFIG_SYS_MALLOC_LEN (128*1024)
d2942ee5	26	#define CONFIG_SYS_TEXT_BASE 0x0
6375dada MV	27
	28	#define CONFIG_BOOTCOMMAND \
	29	"if mmcinfo && fatload mmc 0 0xa0000000 uboot.script ; then " \
	30	"source 0xa0000000; " \
	31	"else " \
	32	"bootm 0x0x60000; " \
	33	"fi; "
	34	#define CONFIG_BOOTARGS "console=tty0 console=ttyS0,9600"
	35	#define CONFIG_TIMESTAMP
	36	#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
	37	#define CONFIG_CMDLINE_TAG
	38	#define CONFIG_SETUP_MEMORY_TAGS
	39
	40	#define CONFIG_LZMA /* LZMA compression support */
	41
	42	/*
	43	* Serial Console Configuration
	44	*/
	45	#define CONFIG_PXA_SERIAL
	46	#define CONFIG_FFUART 1
ce6971cd	47	#define CONFIG_CONS_INDEX 3
6375dada	48	#define CONFIG_BAUDRATE 9600
6375dada MV	49
	50	/*
	51	* Bootloader Components Configuration
	52	*/
	53	#include <config_cmd_default.h>
	54
	55	#undef CONFIG_CMD_NET
6d8962e8	56	#undef CONFIG_CMD_NFS
6375dada MV	57	#define CONFIG_CMD_ENV
	58	#undef CONFIG_CMD_IMLS
	59	#define CONFIG_CMD_MMC
	60	#define CONFIG_CMD_IDE
	61	#define CONFIG_LCD
0698095a	62	#define CONFIG_PXA_LCD
6375dada MV	63
	64	/*
	65	* MMC Card Configuration
	66	*/
	67	#ifdef CONFIG_CMD_MMC
	68	#define CONFIG_MMC
	69	#define CONFIG_GENERIC_MMC
	70	#define CONFIG_PXA_MMC_GENERIC
	71	#define CONFIG_SYS_MMC_BASE 0xF0000000
	72	#define CONFIG_CMD_FAT
	73	#define CONFIG_CMD_EXT2
	74	#define CONFIG_DOS_PARTITION
	75	#endif
	76
	77	/*
	78	* LCD
	79	*/
	80	#ifdef CONFIG_LCD
	81	#define CONFIG_LQ038J7DH53
	82	#define CONFIG_VIDEO_LOGO
	83	#define CONFIG_CMD_BMP
	84	#define CONFIG_SPLASH_SCREEN
	85	#define CONFIG_SPLASH_SCREEN_ALIGN
	86	#define CONFIG_VIDEO_BMP_GZIP
	87	#define CONFIG_VIDEO_BMP_RLE8
	88	#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
	89	#endif
	90
	91	/*
	92	* KGDB
	93	*/
	94	#ifdef CONFIG_CMD_KGDB
	95	#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */
6375dada MV	96	#endif
	97
	98	/*
	99	* HUSH Shell Configuration
	100	*/
	101	#define CONFIG_SYS_HUSH_PARSER 1
6375dada MV	102
	103	#define CONFIG_SYS_LONGHELP
	104	#ifdef CONFIG_SYS_HUSH_PARSER
	105	#define CONFIG_SYS_PROMPT "$ "
6375dada MV	106	#endif
	107	#define CONFIG_SYS_CBSIZE 256
	108	#define CONFIG_SYS_PBSIZE \
	109	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
	110	#define CONFIG_SYS_MAXARGS 16
	111	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	112	#define CONFIG_SYS_DEVICE_NULLDEV 1
	113
	114	/*
	115	* Clock Configuration
	116	*/
6375dada MV	117	#define CONFIG_SYS_CPUSPEED 0x210 /* 416MHz ; N=2,L=16 */
6375dada MV	118
6375dada MV	119	/*
	120	* DRAM Map
	121	*/
	122	#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
	123	#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
	124	#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
	125
	126	#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
	127	#define CONFIG_SYS_DRAM_SIZE 0x02000000 /* 32 MB DRAM */
	128
	129	#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
	130	#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
	131
	132	#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE
	133
6ef6eb91	134	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
25ddd1fb	135	#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
6ef6eb91	136
6375dada MV	137	/*
	138	* NOR FLASH
	139	*/
	140	#ifdef CONFIG_CMD_FLASH
	141	#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
	142	#define PHYS_FLASH_SIZE 0x00080000 /* 512 KB */
	143	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
	144
	145	#define CONFIG_SYS_FLASH_CFI
	146	#define CONFIG_FLASH_CFI_DRIVER 1
	147
	148	#define CONFIG_FLASH_CFI_LEGACY
	149	#define CONFIG_SYS_FLASH_LEGACY_512Kx16
	150
	151	#define CONFIG_SYS_MONITOR_BASE 0
	152	#define CONFIG_SYS_MONITOR_LEN 0x40000
	153
	154	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	155	#define CONFIG_SYS_MAX_FLASH_SECT 256
	156
	157	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
	158
f90aea2a MV	159	#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
	160	#define CONFIG_SYS_FLASH_WRITE_TOUT 240000
	161	#define CONFIG_SYS_FLASH_LOCK_TOUT 240000
	162	#define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000
6375dada MV	163	#define CONFIG_SYS_FLASH_PROTECTION
	164
	165	#define CONFIG_ENV_IS_IN_FLASH 1
	166	#define CONFIG_ENV_SECT_SIZE 0x10000
	167	#else
	168	#define CONFIG_SYS_NO_FLASH
	169	#define CONFIG_ENV_IS_NOWHERE
	170	#endif
	171
	172	#define CONFIG_ENV_ADDR 0x40000
	173	#define CONFIG_ENV_SIZE 0x4000
	174
	175	/*
	176	* IDE
	177	*/
	178	#ifdef CONFIG_CMD_IDE
	179	#define CONFIG_LBA48
	180	#undef CONFIG_IDE_LED
	181	#undef CONFIG_IDE_RESET
	182
	183	#define __io
	184
	185	#define CONFIG_SYS_IDE_MAXBUS 1
	186	#define CONFIG_SYS_IDE_MAXDEVICE 1
	187
	188	#define CONFIG_SYS_ATA_BASE_ADDR 0x20000000
	189	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0
	190
	191	#define CONFIG_SYS_ATA_DATA_OFFSET 0x10
	192	#define CONFIG_SYS_ATA_REG_OFFSET 0x10
	193	#define CONFIG_SYS_ATA_ALT_OFFSET 0x10
	194
	195	#define CONFIG_SYS_ATA_STRIDE 1
	196	#endif
	197
	198	/*
	199	* GPIO settings
	200	*/
	201	#define CONFIG_SYS_GAFR0_L_VAL 0x00000000
	202	#define CONFIG_SYS_GAFR0_U_VAL 0xa5180012
	203	#define CONFIG_SYS_GAFR1_L_VAL 0x69988056
	204	#define CONFIG_SYS_GAFR1_U_VAL 0xaaa580aa
	205	#define CONFIG_SYS_GAFR2_L_VAL 0x6aaaaaaa
	206	#define CONFIG_SYS_GAFR2_U_VAL 0x01040001
	207	#define CONFIG_SYS_GAFR3_L_VAL 0x540a950c
	208	#define CONFIG_SYS_GAFR3_U_VAL 0x00000009
	209	#define CONFIG_SYS_GPCR0_VAL 0x00000000
	210	#define CONFIG_SYS_GPCR1_VAL 0x00000000
	211	#define CONFIG_SYS_GPCR2_VAL 0x00000000
	212	#define CONFIG_SYS_GPCR3_VAL 0x00000000
	213	#define CONFIG_SYS_GPDR0_VAL 0xc26b0000
	214	#define CONFIG_SYS_GPDR1_VAL 0xfcdfaa93
	215	#define CONFIG_SYS_GPDR2_VAL 0x7bbaffff
	216	#define CONFIG_SYS_GPDR3_VAL 0x006ff38d
	217	#define CONFIG_SYS_GPSR0_VAL 0x0d9e45ee
	218	#define CONFIG_SYS_GPSR1_VAL 0x03affdae
	219	#define CONFIG_SYS_GPSR2_VAL 0x07554000
	220	#define CONFIG_SYS_GPSR3_VAL 0x01bc0785
	221
	222	#define CONFIG_SYS_PSSR_VAL 0x30
	223
	224	/*
	225	* Clock settings
	226	*/
227	#define CONFIG_SYS_CKEN 0x01ffffff
228	#define CONFIG_SYS_CCCR 0x02000210
229
230	/*
231	* Memory settings
232	*/
233	#define CONFIG_SYS_MSC0_VAL 0x7ff844c8
234	#define CONFIG_SYS_MSC1_VAL 0x7ff86ab4
235	#define CONFIG_SYS_MSC2_VAL 0x7ff87ff8
236	#define CONFIG_SYS_MDCNFG_VAL 0x0B880acd
237	#define CONFIG_SYS_MDREFR_VAL 0x201fa031
238	#define CONFIG_SYS_MDMRS_VAL 0x00320032
239	#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
240	#define CONFIG_SYS_SXCNFG_VAL 0x40044004
241
242	/*
243	* PCMCIA and CF Interfaces
244	*/
245	#define CONFIG_SYS_MECR_VAL 0x00000003
246	#define CONFIG_SYS_MCMEM0_VAL 0x0001c391
247	#define CONFIG_SYS_MCMEM1_VAL 0x0001c391
248	#define CONFIG_SYS_MCATT0_VAL 0x0001c391
249	#define CONFIG_SYS_MCATT1_VAL 0x0001c391
250	#define CONFIG_SYS_MCIO0_VAL 0x00014611
251	#define CONFIG_SYS_MCIO1_VAL 0x0001c391
252
253	#endif /* __CONFIG_H */