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Commit | Line | Data |
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6375dada MV |
1 | /* |
2 | * Palm LifeDrive configuration file | |
3 | * | |
4 | * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
6375dada MV |
7 | */ |
8 | ||
9 | #ifndef __CONFIG_H | |
10 | #define __CONFIG_H | |
11 | ||
12 | /* | |
13 | * High Level Board Configuration Options | |
14 | */ | |
abc20aba | 15 | #define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ |
6375dada MV |
16 | #define CONFIG_PALMLD 1 /* Palm LifeDrive board */ |
17 | ||
89959081 SG |
18 | /* we will never enable dcache, because we have to setup MMU first */ |
19 | #define CONFIG_SYS_DCACHE_OFF | |
20 | ||
6375dada MV |
21 | /* |
22 | * Environment settings | |
23 | */ | |
24 | #define CONFIG_ENV_OVERWRITE | |
25 | #define CONFIG_SYS_MALLOC_LEN (128*1024) | |
d2942ee5 | 26 | #define CONFIG_SYS_TEXT_BASE 0x0 |
6375dada MV |
27 | |
28 | #define CONFIG_BOOTCOMMAND \ | |
29 | "if mmcinfo && fatload mmc 0 0xa0000000 uboot.script ; then " \ | |
30 | "source 0xa0000000; " \ | |
31 | "else " \ | |
32 | "bootm 0x0x60000; " \ | |
33 | "fi; " | |
34 | #define CONFIG_BOOTARGS "console=tty0 console=ttyS0,9600" | |
35 | #define CONFIG_TIMESTAMP | |
36 | #define CONFIG_BOOTDELAY 2 /* Autoboot delay */ | |
37 | #define CONFIG_CMDLINE_TAG | |
38 | #define CONFIG_SETUP_MEMORY_TAGS | |
39 | ||
40 | #define CONFIG_LZMA /* LZMA compression support */ | |
41 | ||
42 | /* | |
43 | * Serial Console Configuration | |
44 | */ | |
45 | #define CONFIG_PXA_SERIAL | |
46 | #define CONFIG_FFUART 1 | |
ce6971cd | 47 | #define CONFIG_CONS_INDEX 3 |
6375dada | 48 | #define CONFIG_BAUDRATE 9600 |
6375dada MV |
49 | |
50 | /* | |
51 | * Bootloader Components Configuration | |
52 | */ | |
6375dada | 53 | #define CONFIG_CMD_ENV |
6375dada MV |
54 | #define CONFIG_CMD_MMC |
55 | #define CONFIG_CMD_IDE | |
56 | #define CONFIG_LCD | |
0698095a | 57 | #define CONFIG_PXA_LCD |
6375dada MV |
58 | |
59 | /* | |
60 | * MMC Card Configuration | |
61 | */ | |
62 | #ifdef CONFIG_CMD_MMC | |
63 | #define CONFIG_MMC | |
64 | #define CONFIG_GENERIC_MMC | |
65 | #define CONFIG_PXA_MMC_GENERIC | |
66 | #define CONFIG_SYS_MMC_BASE 0xF0000000 | |
67 | #define CONFIG_CMD_FAT | |
68 | #define CONFIG_CMD_EXT2 | |
69 | #define CONFIG_DOS_PARTITION | |
70 | #endif | |
71 | ||
72 | /* | |
73 | * LCD | |
74 | */ | |
75 | #ifdef CONFIG_LCD | |
76 | #define CONFIG_LQ038J7DH53 | |
77 | #define CONFIG_VIDEO_LOGO | |
78 | #define CONFIG_CMD_BMP | |
79 | #define CONFIG_SPLASH_SCREEN | |
80 | #define CONFIG_SPLASH_SCREEN_ALIGN | |
81 | #define CONFIG_VIDEO_BMP_GZIP | |
82 | #define CONFIG_VIDEO_BMP_RLE8 | |
83 | #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) | |
84 | #endif | |
85 | ||
86 | /* | |
87 | * KGDB | |
88 | */ | |
89 | #ifdef CONFIG_CMD_KGDB | |
90 | #define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */ | |
6375dada MV |
91 | #endif |
92 | ||
93 | /* | |
94 | * HUSH Shell Configuration | |
95 | */ | |
96 | #define CONFIG_SYS_HUSH_PARSER 1 | |
6375dada MV |
97 | |
98 | #define CONFIG_SYS_LONGHELP | |
6375dada MV |
99 | #define CONFIG_SYS_CBSIZE 256 |
100 | #define CONFIG_SYS_PBSIZE \ | |
101 | (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
102 | #define CONFIG_SYS_MAXARGS 16 | |
103 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
104 | #define CONFIG_SYS_DEVICE_NULLDEV 1 | |
105 | ||
106 | /* | |
107 | * Clock Configuration | |
108 | */ | |
6375dada MV |
109 | #define CONFIG_SYS_CPUSPEED 0x210 /* 416MHz ; N=2,L=16 */ |
110 | ||
6375dada MV |
111 | /* |
112 | * DRAM Map | |
113 | */ | |
114 | #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ | |
115 | #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ | |
116 | #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ | |
117 | ||
118 | #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ | |
119 | #define CONFIG_SYS_DRAM_SIZE 0x02000000 /* 32 MB DRAM */ | |
120 | ||
121 | #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ | |
122 | #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ | |
123 | ||
124 | #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE | |
125 | ||
6ef6eb91 | 126 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
25ddd1fb | 127 | #define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1) |
6ef6eb91 | 128 | |
6375dada MV |
129 | /* |
130 | * NOR FLASH | |
131 | */ | |
132 | #ifdef CONFIG_CMD_FLASH | |
133 | #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ | |
134 | #define PHYS_FLASH_SIZE 0x00080000 /* 512 KB */ | |
135 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 | |
136 | ||
137 | #define CONFIG_SYS_FLASH_CFI | |
138 | #define CONFIG_FLASH_CFI_DRIVER 1 | |
139 | ||
140 | #define CONFIG_FLASH_CFI_LEGACY | |
141 | #define CONFIG_SYS_FLASH_LEGACY_512Kx16 | |
142 | ||
143 | #define CONFIG_SYS_MONITOR_BASE 0 | |
144 | #define CONFIG_SYS_MONITOR_LEN 0x40000 | |
145 | ||
146 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
147 | #define CONFIG_SYS_MAX_FLASH_SECT 256 | |
148 | ||
149 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 | |
150 | ||
f90aea2a MV |
151 | #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 |
152 | #define CONFIG_SYS_FLASH_WRITE_TOUT 240000 | |
153 | #define CONFIG_SYS_FLASH_LOCK_TOUT 240000 | |
154 | #define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000 | |
6375dada MV |
155 | #define CONFIG_SYS_FLASH_PROTECTION |
156 | ||
157 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
158 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
159 | #else | |
160 | #define CONFIG_SYS_NO_FLASH | |
161 | #define CONFIG_ENV_IS_NOWHERE | |
162 | #endif | |
163 | ||
164 | #define CONFIG_ENV_ADDR 0x40000 | |
165 | #define CONFIG_ENV_SIZE 0x4000 | |
166 | ||
167 | /* | |
168 | * IDE | |
169 | */ | |
170 | #ifdef CONFIG_CMD_IDE | |
171 | #define CONFIG_LBA48 | |
172 | #undef CONFIG_IDE_LED | |
173 | #undef CONFIG_IDE_RESET | |
174 | ||
175 | #define __io | |
176 | ||
177 | #define CONFIG_SYS_IDE_MAXBUS 1 | |
178 | #define CONFIG_SYS_IDE_MAXDEVICE 1 | |
179 | ||
180 | #define CONFIG_SYS_ATA_BASE_ADDR 0x20000000 | |
181 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0 | |
182 | ||
183 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x10 | |
184 | #define CONFIG_SYS_ATA_REG_OFFSET 0x10 | |
185 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x10 | |
186 | ||
187 | #define CONFIG_SYS_ATA_STRIDE 1 | |
188 | #endif | |
189 | ||
190 | /* | |
191 | * GPIO settings | |
192 | */ | |
193 | #define CONFIG_SYS_GAFR0_L_VAL 0x00000000 | |
194 | #define CONFIG_SYS_GAFR0_U_VAL 0xa5180012 | |
195 | #define CONFIG_SYS_GAFR1_L_VAL 0x69988056 | |
196 | #define CONFIG_SYS_GAFR1_U_VAL 0xaaa580aa | |
197 | #define CONFIG_SYS_GAFR2_L_VAL 0x6aaaaaaa | |
198 | #define CONFIG_SYS_GAFR2_U_VAL 0x01040001 | |
199 | #define CONFIG_SYS_GAFR3_L_VAL 0x540a950c | |
200 | #define CONFIG_SYS_GAFR3_U_VAL 0x00000009 | |
201 | #define CONFIG_SYS_GPCR0_VAL 0x00000000 | |
202 | #define CONFIG_SYS_GPCR1_VAL 0x00000000 | |
203 | #define CONFIG_SYS_GPCR2_VAL 0x00000000 | |
204 | #define CONFIG_SYS_GPCR3_VAL 0x00000000 | |
205 | #define CONFIG_SYS_GPDR0_VAL 0xc26b0000 | |
206 | #define CONFIG_SYS_GPDR1_VAL 0xfcdfaa93 | |
207 | #define CONFIG_SYS_GPDR2_VAL 0x7bbaffff | |
208 | #define CONFIG_SYS_GPDR3_VAL 0x006ff38d | |
209 | #define CONFIG_SYS_GPSR0_VAL 0x0d9e45ee | |
210 | #define CONFIG_SYS_GPSR1_VAL 0x03affdae | |
211 | #define CONFIG_SYS_GPSR2_VAL 0x07554000 | |
212 | #define CONFIG_SYS_GPSR3_VAL 0x01bc0785 | |
213 | ||
214 | #define CONFIG_SYS_PSSR_VAL 0x30 | |
215 | ||
216 | /* | |
217 | * Clock settings | |
218 | */ | |
219 | #define CONFIG_SYS_CKEN 0x01ffffff | |
220 | #define CONFIG_SYS_CCCR 0x02000210 | |
221 | ||
222 | /* | |
223 | * Memory settings | |
224 | */ | |
225 | #define CONFIG_SYS_MSC0_VAL 0x7ff844c8 | |
226 | #define CONFIG_SYS_MSC1_VAL 0x7ff86ab4 | |
227 | #define CONFIG_SYS_MSC2_VAL 0x7ff87ff8 | |
228 | #define CONFIG_SYS_MDCNFG_VAL 0x0B880acd | |
229 | #define CONFIG_SYS_MDREFR_VAL 0x201fa031 | |
230 | #define CONFIG_SYS_MDMRS_VAL 0x00320032 | |
231 | #define CONFIG_SYS_FLYCNFG_VAL 0x00000000 | |
232 | #define CONFIG_SYS_SXCNFG_VAL 0x40044004 | |
233 | ||
234 | /* | |
235 | * PCMCIA and CF Interfaces | |
236 | */ | |
237 | #define CONFIG_SYS_MECR_VAL 0x00000003 | |
238 | #define CONFIG_SYS_MCMEM0_VAL 0x0001c391 | |
239 | #define CONFIG_SYS_MCMEM1_VAL 0x0001c391 | |
240 | #define CONFIG_SYS_MCATT0_VAL 0x0001c391 | |
241 | #define CONFIG_SYS_MCATT1_VAL 0x0001c391 | |
242 | #define CONFIG_SYS_MCIO0_VAL 0x00014611 | |
243 | #define CONFIG_SYS_MCIO1_VAL 0x0001c391 | |
244 | ||
245 | #endif /* __CONFIG_H */ |